Prosecution Insights
Last updated: October 01, 2026
Application No. 18/748,796

Migration of Application Executions Across Processing Units

Non-Final OA §103§112
Filed
Jun 20, 2024
Priority
Jun 30, 2023 — EU 23182888
Examiner
LEE, TAMMY EUNHYE
Art Unit
Tech Center
Assignee
Aptiv Technologies AG
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
364 granted / 434 resolved
+23.9% vs TC avg
Strong +31% interview lift
Without
With
+31.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
11 currently pending
Career history
449
Total Applications
across all art units

Statute-Specific Performance

§101
12.9%
-27.1% vs TC avg
§103
49.4%
+9.4% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
26.6%
-13.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 434 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-15 are pending for examination. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims language in the following claims is not clearly understood: As per claim 1, line 3-5, it is unclear whether “at least one application” in line 4 and “the application” in line 5-6 are referring to one of the “plurality of applications” in line 3 or “applications” in line 1 (i.e. consistent term should be used with “the” or “said” if they are the same) As per claim 4, line 4-7, it is unclear whether “the contents” is referring “at least some contents” in claim 3 (i.e. consistent term should be used with “the” or “said” if they are the same) Line 8, it is unclear whether “the processor” is referring to “the first processor” or “the target processor” in claim 1 (i.e. consistent term should be used with “the” or “said” if they are the same) As per claim 8, line 6, it is unclear whether “contents” is referring to “at least some contents” in claim 3 (i.e. consistent term should be used with “the” or “said” if they are the same) As per claim 12, line 5 and 8, it is unclear whether “a migration” is referring to the same migration in claim 1 (i.e. consistent term should be used with “the” or “said” if they are the same) As per claim 15, it has the same deficiencies as claim 1 above. Appropriate correction is required. As per claims 2-14, they depend from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for at least the same reasons. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-8, 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashani et al. US Pub 2024/0118692 (hereafter Kashani) in view of Sanderson US Pub 2024/0330075 (hereafter Sanderson). As per claim 1, Kashani teaches the invention substantially as claimed including a system for migrating execution of applications across multiple processors on a vehicle, the system comprising: a first processor on the vehicle to execute a plurality of applications until a migration of an execution of at least one application transfers the execution of the application to a target processor with available resources to execute the application (para[0025-0026, 0034, 0039-0040, 0059], FIG. 2-4, a vehicle includes hosts 1-3, where each host executes applications 202, and each host has hardware resources including processors, and performs live migration of workloads (application) from a source host to a target host); at least one target processor including the target processor with the available resources to execute the execution of the application using the available resources (para[0031, 0034, 0040-0041, 0047-0048], host 200B includes the same configuration data (CPUs, accelerators) is selected as a target host with available resources); a first orchestrator that executes on the first processor to initiate the execution of the application and then to manage the migration to the target processor; and a second orchestrator in communication with the first orchestrator and that executes on the target processor to indicate the available resources for taking-over the execution of the application (para[0040, 0049, 0059-0065], processor of the source host performs live migration to the target host by considering the workload requirement information and configuration data, where tunneling agents of source and target hosts are activated and used for live migration); the second orchestrator communicates with the first orchestrator to migrate the execution of the application to the target processor (para[0059-0065], migrate the workloads of the source host to the optimal target host via live migration by communicating with each other’s agents). Kashani does not explicitly teach to resume where the execution left-off on the first processor. However, Sanderson teaches resume where the execution left-off on the first processor (para[0022, 0026, 0034, 0038, 0041, 0063], live migration component resumes the application’s execution on the target system, based on the memory snapshot of an application, thus the target system resumes where the execution left off on the source system). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sanderson’s teaching to Kashani’s invention in order to provide a method of live migration of running application between computer systems while providing a seamless user interface experience, where the suspension and resumption of the application occur in a manner imperceptible to the user and there is no loss of application state or any visible UI interruption (para[0022, 0028]). As per claim 2, Kashani and Sanderson teach the system of claim 1, and Kashani teaches wherein the first orchestrator initiates the execution of the application by executing the application through an initialization process that includes establishing communication on a network of the vehicle (para[0025, 0032, 0038-0039], the vehicle consists of hosts that can communicate with each other on the network using a bus, and the workload (application) is being executed by the processors). As per claim 3, Kashani teaches wherein the first orchestrator and the second orchestrator migrate the execution of the application from the first processor to the target processor by migrating at least some contents of a first random-access memory related to the application and accessible to the first processor to a second random-access memory accessible by the target processor (para[0036, 0063-0064], memory pages used by the application is stored in the memory (RAM), the instructions cause the processor to begin the transmission of associated memory pages (minimum set) from the source host to the target host). As per claim 4, Sanderson teaches prior to the first orchestrator and the second orchestrator migrating the execution of the application from the first processor to the target processor: the contents of the first random-access memory include executable code that causes the first processor to execute initialization functions of the application; and the contents of the second random-access memory include executable code that causes the processor to execute one or more primary functions of the application (para[0041-0042, 0050, 0057], the first system obtains executable file which is in initialization phase (initialization functions), then pausing the application execution for snapshotting of the memory state, and once all memory deltas have been received and applied, at operational phase, execution of the application (primary function) is continued at second system, based on the updated memory state). As per claim 5, Sanderson teaches wherein the contents of the first random-access memory that are migrated to the second random-access memory include current state and data related to the application (para[0041-0043, 0050], snapshot of the current state and data is generated including copy of a set of memory pages used by executable file after the completion of the initialization phase, and migrated to the second system). As per claim 6, Kashani teaches wherein the contents of the first random-access memory that are migrated to the second random-access memory include absolute memory addresses related to different virtual machines executing independently on each of the first processor and the target processor (para[0036, 0039, 0047, 0063-0064], data stored in the memory (associated memory pages) of a VM (source host) is transferred to the target host, where the VM of the source host is halted and new VM is re-created in the target host). As per claim 7, Sanderson teaches wherein the first orchestrator and the second orchestrator migrate the execution of the application from the first processor to the target processor by: migrating the execution of the application from the first processor to the target processor, including: causing, by the first orchestrator, the first processor to cease execution of the application in a current state; and causing, by the second orchestrator, the target processor to resume execution of the application from the current state (para[0022, 0026, 0034, 0038, 0041, 0063], suspend/stop the execution of application in the source system and live migration component resumes the application’s execution on the target system, based on the memory snapshot of an application, thus the target system resumes where the execution left off on the source system). As per claim 8, Kashani teaches wherein: the first processor has a different hardware architecture than the target processor (para[0046-0047, 0057], FIG. 5, each host includes CPUs and has different hardware architecture). In addition, Sanderson teaches the migration of execution of the application from the first processor to the target processor includes migrating a main memory associated with the first processor to the target processor by copying contents of the main memory using an identical data structure without serialization and deserialization of the main memory (para[0041-0043, 0050], snapshot of the current state and data is generated including copy of a set of memory pages used by executable file after the completion of the initialization phase, and migrated to the second system). As per claim 11, Kashani teaches the application is compiled prior to being distributed to the vehicle system (para[0027, 0031], upgrades (application) is compiled as a file prior to distributed to the vehicle). In addition, Sanderson teaches wherein: the application is compiled in a binary format that is independent of hardware architecture of the first processor and the target processor(para[0001, 0014, 0041], computer system is executing the executable file code (binary code) of the application). As per claim 12, Kashani teaches wherein the first orchestrator communicates with the second orchestrator to migrate the execution of the application to the target processor to resume where the execution left-off on the first processor by: checking for whether information communicated indicates either: a migration with the target processor, or a communication from the second orchestrator indicating that the target processor is in a ready state for the migration (para[0058], determine whether live migration is necessary, then perform migration routine); in response to determining there is a migration or in response to receiving the communication, causes the first processor to send data to the second orchestrator to migrate the execution of the application to the target processor (para[0058, 0063-0064], transmit associated memory pages in response to migration is necessary). As per claim 13, Kashani teaches wherein the application is a service application or a device driver application (para[0026], applications are related to vehicle safety, entertainment, propulsion system etc.). As per claim 14, Sanderson teaches wherein the first orchestrator and the second orchestrator: reside in respective application managers executing on the first processor and the target processor; or are external to the respective application managers and are executed in parallel to the respective application managers (para[0025, 0028], live migration component 109a, 109b manages the application state snapshotting, storing memory delta, and transporting the memory delta for the migration, thus reside within the application manager). As per claim 15, it is a method claim of claim 1 above, thus it is rejected for the same rationale. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashani in view of Sanderson as applied to claim 1 above, and further in view of Vangoethem et al. US Pub 2022/0161744 (hereafter Vangoethem). As per claim 9, Kashani and Sanderson teach the system of claim 1 but they do not explicitly teach wherein: the first processor is a zone controller of the vehicle that serves as a hub for sensors within a physical section of the vehicle; and the target processor is a domain controller that performs centralized server functions for the vehicle. Vangoethem teaches the first processor is a zone controller of the vehicle that serves as a hub for sensors within a physical section of the vehicle; and the target processor is a domain controller that performs centralized server functions for the vehicle (para[0058-0059, 0074-0075], computing resources (processors) are allocated to domain controllers and zone controllers). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Vangoethem’s teaching to Kashani and Sanderson’s invention in order to provide an elastic computing which dynamically allocate computing resources according to processing needs to provide sufficient processing and memory resources for enabling the sophisticated multimedia functionality and vehicle control, which communicatively coupled to external computing resources (para[0004-0005]). Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kashani in view of Sanderson as applied to claim 1 above, and further in view of Shi et al. US Pub 2023/0266814 (hereafter Shi). As per claim 10, Kashani and Sanderson the system of claim 1, but they do not explicitly teach wherein during instances of low-power availability, the second orchestrator migrates the application from the target processor back to the first processor. However, Shi during instances of low-power availability, the second orchestrator migrates the application from the target processor back to the first processor (para[0025, 0174], when the resources in a node is insufficient (low power availability), migration the application instance to an idle node based on a live migration, thus the application is migrated back to the first node if the first node is relatively idle node). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shi’s teaching to Kashani and Sanderson’s invention in order to provide a solution that quickly and elastically scales up and down application instances as the traffic of the application changes (para[0019-0020]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhu et al. teaches US 2023/0032278 teaches techniques for memory management for a heterogenous system, for a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced. a first portion of the particular application is executed by the first processor(s) and a second portion of the particular application is executed by the second processor(s). A access request is sent to the VM component, and the VM component migrates the data from the first physical memory to the second physical memory. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMY EUNHYE LEE whose telephone number is (571)270-7773. The examiner can normally be reached Mon, Tues, Thur 9PM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Meng-Ai An can be reached at (571)272-3756. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAMMY E LEE/Primary Examiner, Art Unit 2195
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Prosecution Timeline

Jun 20, 2024
Application Filed
Sep 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+31.2%)
3y 9m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 434 resolved cases by this examiner. Grant probability derived from career allowance rate.

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