DETAILED ACTION
This action is responsive to the application filed 20 Jun 2024. Claims 1-20 are pending. Claims 1, 8 and 15 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Note
The present application has used the limitations of “comprising” “to program… to a single bit per memory cell”. Using BRI, the memory cells can comprise storage of more than two memory states, or the memory cells could have the capacity to program multiple states while using any of the P0-P7 states as a dual P0 and P1.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1, 8, and 15 have the following limitation: “in a first program loop … applying a programming pulse to the selected word line…” And later: “in a second program loop, applying a programming pulse”. It is indefinite whether “applying a programming pulse” in the first and second program loops are the same programming pulse, or a different pulse with a different time length, or voltage as the first applied programming pulse.
Likewise, claims 1, 8, and 15 have the following limitations: “in a first program loop … then conduction a verify operation…” And later: “in a second program loop… then conducting a verify operation.” It is indefinite whether “conducting a verify operation” in the first and second program loops are the same verify operation, or a different verify operation.
Claims 7 and 14 also contain the limitation “the programming pulse” and are rejected under 112(b.
Claims 3, 5, 6, 10, 12, 13, 17, 19, and 20 also contain the limitation “the verify operation.” and are rejected under 112(b)
Claim(s) 2-7, 9-14, and 16-20 depend on rejected claim(s) 1, 8, and 15 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 7, 8, 10, 14, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi, et al, U.S. Patent Application Publication 2011/0292725 (“Choi”).
Regarding claim 1, Choi teaches:
A method of operating a memory device, comprising the steps of: preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes; (Choi, fig 2, “[0074] The memory cell arranged in the memory cell array 1110 may be configured into a plurality of memory blocks… The embodiment illustrated in FIG. 2 assumes that N is equal 64 and that word lines (WLs) are disposed in a consecutive arrangement… [0079] The page buffer circuit 1130 is connected to the memory cell array 1110 through a plurality of bit lines BL0 to BLm,”; a memory array with a controller, voltage generator, and multiple wordlines and multiple bitlines to address memory cells in a string).
in a first program loop to program the memory cells of a selected word line to a single bit per memory cell format, applying a programming pulse to the selected word line and then conducting a verify operation; and (Choi, fig 12, “[0075] Embodiments of the inventive concept include various memory cell arrays comprising flash SLCs and/or MLCs. [0119] FIG. 12 is a timing diagram further describing one approach to a LSB programming operation. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. … Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state P0.”; a memory array is programmed using loops of alternating Vpgm and VFY voltages while the bitlines are held constant).
without pre-charging the memory holes after the first program loop, in a second program loop, applying a programming pulse to the selected word line and then conducting a verify operation. (Choi, fig 12, “[0082] Examples of low voltages include the power source voltage and voltages used as a bit line precharge voltage or a CSL voltage. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. …”; a bitline setup time in fig 12, where selected BL and unselected BLs are set to a fixed voltage during the application of multiple program pulses and verify pulses, without any further “precharging” of the bit lines).
Regarding claim 3, Choi teaches The method as set forth in claim 1, wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage. (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state PO.”; an ISPP program that is performed on the selected word line until the memory cell is “properly programmed” (i.e. operation passes)).
Regarding claim 7, Choi teaches The method as set forth in claim 1, wherein during the programming pulse of each of the program loops, a pass voltage is applied to a plurality of unselected word lines of the plurality of word lines. (Choi, fig 12, “[0120] Then, during a Vpass enable period, a Vpass voltage is applied to all the word lines.”; that Vpass is applied to all of the unselected wordlines when programming the selected wordline).
Regarding claim 8, Choi teaches:
A memory device, comprising: a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes; (Choi, fig 2, “[0074] The memory cell arranged in the memory cell array 1110 may be configured into a plurality of memory blocks… The embodiment illustrated in FIG. 2 assumes that N is equal 64 and that word lines (WLs) are disposed in a consecutive arrangement… [0079] The page buffer circuit 1130 is connected to the memory cell array 1110 through a plurality of bit lines BL0 to BLm,”; a memory array with a controller, voltage generator, and multiple wordlines and multiple bitlines to address memory cells in a string).
circuitry for programming the memory cells of a selected word line of the plurality of word lines to a single bit per memory cell format, the circuitry being configured to; in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation; and (Choi, fig 12, “[0075] Embodiments of the inventive concept include various memory cell arrays comprising flash SLCs and/or MLCs. [0119] FIG. 12 is a timing diagram further describing one approach to a LSB programming operation. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. … Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state P0.”; a memory array is programmed using loops of alternating Vpgm and VFY voltages while the bitlines are held constant).
without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, apply a programming pulse to the selected word line and then conduct a verify operation. (Choi, fig 12, “[0082] Examples of low voltages include the power source voltage and voltages used as a bit line precharge voltage or a CSL voltage. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. …”; a bitline setup time in fig 12, where selected BL and unselected BLs are set to a fixed voltage during the application of multiple program pulses and verify pulses, without any further “precharging” of the bit lines).
Regarding claim 10, Choi teaches The memory device as set forth in claim 8, wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage. (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state PO.”; an ISPP program that is performed on the selected word line until the memory cell is “properly programmed” (i.e. operation passes)).
Regarding claim 14, Choi teaches The memory device as set forth in claim 8, wherein during the programming pulse of each of the program loops, the circuitry applies a pass voltage to a plurality of unselected word lines of the plurality of word lines. (Choi, fig 12, “[0120] Then, during a Vpass enable period, a Vpass voltage is applied to all the word lines.”; that Vpass is applied to all of the unselected wordlines when programming the selected wordline).
Regarding claim 15, Choi teaches:
A computing system, comprising: a processor unit; a plurality of non-volatile memory packages in electrical communication with the processor unit, each of the non-volatile memory packages having a memory block that includes an array of memory cells that are arranged in a plurality of word lines and memory holes and having circuitry for programming the memory cells (Choi, fig 2, “[0074] The memory cell arranged in the memory cell array 1110 may be configured into a plurality of memory blocks… The embodiment illustrated in FIG. 2 assumes that N is equal 64 and that word lines (WLs) are disposed in a consecutive arrangement… [0079] The page buffer circuit 1130 is connected to the memory cell array 1110 through a plurality of bit lines BL0 to BLm,”; a memory array with a controller, voltage generator, and multiple wordlines and multiple bitlines to address memory cells in a string).
of a selected word line of the plurality of word lines to a single bit per memory cell format, the circuitry being configured to; in a first program loop, apply a programming pulse to the selected word line and then conduct a verify operation; and (Choi, fig 12, “[0075] Embodiments of the inventive concept include various memory cell arrays comprising flash SLCs and/or MLCs. [0119] FIG. 12 is a timing diagram further describing one approach to a LSB programming operation. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. … Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state P0.”; a memory array is programmed using loops of alternating Vpgm and VFY voltages while the bitlines are held constant).
without pre-charging the memory holes after the verify operation of the first program loop, in a second program loop, apply a programming pulse to the selected word line and then conduct a verify operation. (Choi, fig 12, “[0082] Examples of low voltages include the power source voltage and voltages used as a bit line precharge voltage or a CSL voltage. [0120] Referring to FIG. 12, during an LSB BL setup period, the power source voltage VDD is applied to a program-inhibit bit line, OV is applied to a program bit line, and 0V is applied to all word lines. …”; a bitline setup time in fig 12, where selected BL and unselected BLs are set to a fixed voltage during the application of multiple program pulses and verify pulses, without any further “precharging” of the bit lines).
Regarding claim 17, Choi teaches The computing system as set forth in claim 15, wherein programming continues through a plurality of program loops until the verify operation passes or until the programming voltage reaches a predetermined maximum programming voltage. (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N to the selected word line until the selected memory cell is properly programmed to the intermediate program state PO.”; an ISPP program that is performed on the selected word line until the memory cell is “properly programmed” (i.e. operation passes)).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Yang, et al, U.S. Patent Application Publication 2023/0101019 (“Yang-019”).
Regarding claim 2, Choi teaches the method as set forth in claim 1.
Choi teaches wherein between the first and second program loops, a programming voltage is increased by a step size, and (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N”; that Vpgm can be applied stepwise in an ISPP method).
Choi does not explicitly teach wherein the step size is no greater than 0.2 V.
Yang-019 teaches wherein the step size is no greater than 0.2 V. (Yang-019, fig 6, “[0139] For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts).”; that ISPP can be done in steps of 0.1V to 1.0V).
In view of the teachings of Yang-019 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-019 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-019, in the same or in a similar field of endeavor with Choi, can combine Yang-019’s specific ISPP step size with Choi’s unspecified voltages. Yang-019’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Choi teaches the memory device as set forth in claim 8.
Choi teaches wherein between the first and second program loops, (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N”; that Vpgm can be applied stepwise in an ISPP method).
Choi does not explicitly teach the circuitry increases a programming voltage by a step size that is no greater than 0.2 V.
Yang-019 teaches the circuitry increases a programming voltage by a step size that is no greater than 0.2 V. (Yang-019, fig 6, “[0139] For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts).”; that ISPP can be done in steps of 0.1V to 1.0V).
In view of the teachings of Yang-019 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-019 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-019, in the same or in a similar field of endeavor with Choi, can combine Yang-019’s specific ISPP step size with Choi’s unspecified voltages. Yang-019’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 16, Choi teaches the computing system as set forth in claim 15.
Choi teaches wherein between the first and second program loops, (Choi, fig 12, “[0120] Finally, during an LSB program execution period, a conventionally understood Incremental Step Pulse Program (ISPP)defined, programming voltage (Vpgm) is iteratively applied over programming loops 1 to N”; that Vpgm can be applied stepwise in an ISPP method).
Choi does not explicitly teach the circuitry increases a programming voltage by a step size that is no greater than 0.2 V.
Yang-019 teaches the circuitry increases a programming voltage by a step size that is no greater than 0.2 V. (Yang-019, fig 6, “[0139] For example, the next pulse will have a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1-1.0 volts).”; that ISPP can be done in steps of 0.1V to 1.0V).
In view of the teachings of Yang-019 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-019 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-019, in the same or in a similar field of endeavor with Choi, can combine Yang-019’s specific ISPP step size with Choi’s unspecified voltages. Yang-019’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Jain, et al, U.S. Patent Application Publication 20230153248 (“Jain”).
Regarding claim 4, Choi teaches the method as set forth in claim 3.
Choi does not explicitly teach wherein the predetermined maximum programming voltage is no greater than 17 V.
Jain teaches wherein the predetermined maximum programming voltage is no greater than 17 V. (Jain, fig 5B, “[0104] Typically, the program voltage applied to the control terminals (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6, the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level)”; that the maximum Vpgm can be set at 16V, which is less than 17V).
In view of the teachings of Jain it would have been obvious for a person of ordinary skill in the art to apply the teachings of Jain to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Jain, in the same or in a similar field of endeavor with Choi, can combine Jain’s specific maximum programming voltage with Choi’s unspecified voltages. Jain’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, Choi teaches the memory device as set forth in claim 10.
Choi does not explicitly teach wherein the predetermined maximum programming voltage is no greater than 17 V.
Jain teaches wherein the predetermined maximum programming voltage is no greater than 17 V. (Jain, fig 5B, “[0104] Typically, the program voltage applied to the control terminals (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6, the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level)”; that the maximum Vpgm can be set at 16V, which is less than 17V).
In view of the teachings of Jain it would have been obvious for a person of ordinary skill in the art to apply the teachings of Jain to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Jain, in the same or in a similar field of endeavor with Choi, can combine Jain’s specific maximum programming voltage with Choi’s unspecified voltages. Jain’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 18, Choi teaches the computing system as set forth in claim 17.
Choi does not explicitly teach wherein the predetermined maximum programming voltage is no greater than 17 V.
Jain teaches wherein the predetermined maximum programming voltage is no greater than 17 V. (Jain, fig 5B, “[0104] Typically, the program voltage applied to the control terminals (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the program pulses is increased with each successive pulse by a predetermined step size. In step 602 of FIG. 6, the programming voltage signal (Vpgm) is initialized to the starting magnitude (e.g., ˜12-16V or another suitable level)”; that the maximum Vpgm can be set at 16V, which is less than 17V).
In view of the teachings of Jain it would have been obvious for a person of ordinary skill in the art to apply the teachings of Jain to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Jain, in the same or in a similar field of endeavor with Choi, can combine Jain’s specific maximum programming voltage with Choi’s unspecified voltages. Jain’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Kim, et al, U.S. Patent Application Publication 20120155168 (“Kim”).
Choi teaches the method as set forth in claim 3.
Choi does not explicitly teach wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
Kim teaches wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V. (Kim, fig 58, “[0082] As will be explained below, an embodiment of the inventive concept can maintain a sensing margin by distributing a portion of a program state’s threshold voltages below 0V and by securing a sufficient distance between threshold voltages. An example of this is illustrated in FIG. 1, where a portion of a first program state P1 is distributed below 0V. That is, a verification voltage of the first program state P1 is a negative voltage. ”; that a P1 distribution value can be negative, or below 2 V; that a MLC can be programmed using only P0 and P1 values).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Kim, in the same or in a similar field of endeavor with Choi, can combine Kim’s specific maximum memory cell threshold volage with Choi’s unspecified voltages. Kim’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Choi, as modified by Kim, in view of Yang, et al, U.S. Patent Application Publication 2020/0365218 (“Yang-218”).
Choi, as modified by Kim, teaches the method as set forth in claim 5.
Choi, as modified by Kim, does not explicitly teach wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.
Yang-218 teaches wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V. (Yang-218, fig 7B, “[0124] FIG. 7B shows eight possible threshold voltage distributions 722-736 after programming in order to illustrate a possible problem that may occur with a group of memory cells having severe mis-shape. Distribution 722 corresponds to state S0; distribution 724 corresponds to state S1; distribution 726 corresponds to state S2”; that the “window” between probability distributions can be less than 0.5V after programming is completed; that the window can shift after programming and the window can become smaller; that the windows between the distributions can overlap over time and/or PE cycles).
In view of the teachings of Yang-218 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-218 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-218, in the same or in a similar field of endeavor with Choi, can combine Yang-218’s specific voltage window between memory cell threshold voltages with Choi’s unspecified voltages. Yang-218’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi, as modified by Jain, in view of Kim.
Regarding claim 12, Choi, as modified by Jain, teaches the memory device as set forth in claim 11.
Choi, as modified by Jain, does not explicitly teach wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
Kim teaches wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V. (Kim, fig 58, “[0082] As will be explained below, an embodiment of the inventive concept can maintain a sensing margin by distributing a portion of a program state’s threshold voltages below 0V and by securing a sufficient distance between threshold voltages. An example of this is illustrated in FIG. 1, where a portion of a first program state P1 is distributed below 0V. That is, a verification voltage of the first program state P1 is a negative voltage. ”; that a P1 distribution value can be negative, or below 2 V; that a MLC can be programmed using only P0 and P1 values).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Kim, in the same or in a similar field of endeavor with Choi, can combine Kim’s specific maximum memory cell threshold volage with Choi’s unspecified voltages. Kim’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 19, Choi, as modified by Jain, teaches the computing system as set forth in claim 18.
Choi, as modified by Jain, does not explicitly teach wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V.
Kim teaches wherein after the verify operation passes, all of the memory cells of the selected word line have threshold voltages below 2 V. (Kim, fig 58, “[0082] As will be explained below, an embodiment of the inventive concept can maintain a sensing margin by distributing a portion of a program state’s threshold voltages below 0V and by securing a sufficient distance between threshold voltages. An example of this is illustrated in FIG. 1, where a portion of a first program state P1 is distributed below 0V. That is, a verification voltage of the first program state P1 is a negative voltage. ”; that a P1 distribution value can be negative, or below 2 V; that a MLC can be programmed using only P0 and P1 values).
In view of the teachings of Kim it would have been obvious for a person of ordinary skill in the art to apply the teachings of Kim to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Kim, in the same or in a similar field of endeavor with Choi, can combine Kim’s specific maximum memory cell threshold volage with Choi’s unspecified voltages. Kim’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Choi, as modified by Jain and Kim, in view of Yang-218.
Choi, as modified by Jain and Kim, teaches the memory device as set forth in claim 12.
Choi, as modified by Jain and Kim, does not explicitly teach wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.
Yang-218 teaches wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V. (Yang-218, fig 7B, “[0124] FIG. 7B shows eight possible threshold voltage distributions 722-736 after programming in order to illustrate a possible problem that may occur with a group of memory cells having severe mis-shape. Distribution 722 corresponds to state S0; distribution 724 corresponds to state S1; distribution 726 corresponds to state S2”; that the “window” between probability distributions can be less than 0.5V after programming is completed; that the window can shift after programming and the window can become smaller; that the windows between the distributions can overlap over time and/or PE cycles).
In view of the teachings of Yang-218 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-218 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-218, in the same or in a similar field of endeavor with Choi, can combine Yang-218’s specific voltage window between memory cell threshold voltages with Choi’s unspecified voltages. Yang-218’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Yang-218.
Choi teaches the computing system as set forth in claim 17.
Choi does not explicitly teach wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V.
Yang-218 teaches wherein after the verify operation passes, the data has a threshold voltage window of no greater than 0.5 V. (Yang-218, fig 7B, “[0124] FIG. 7B shows eight possible threshold voltage distributions 722-736 after programming in order to illustrate a possible problem that may occur with a group of memory cells having severe mis-shape. Distribution 722 corresponds to state S0; distribution 724 corresponds to state S1; distribution 726 corresponds to state S2”; that the “window” between probability distributions can be less than 0.5V after programming is completed; that the window can shift after programming and the window can become smaller; that the windows between the distributions can overlap over time and/or PE cycles).
In view of the teachings of Yang-218 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Yang-218 to Choi before the effective filing date of the claimed invention in order to teach programming an SLC memory cell. The teachings of Yang-218, in the same or in a similar field of endeavor with Choi, can combine Yang-218’s specific voltage window between memory cell threshold voltages with Choi’s unspecified voltages. Yang-218’s specific voltage and Choi’s voltage merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825