DETAILED ACTION
Response to Amendment
Applicant’s amendment, filed 01/15/26, for application number 18/748,989 has been received and entered into record. Claims 1, 3, 4, 6, 7, 13, 15, 16, and 18 have been amended, Claim 17 has been cancelled, and Claim 21 has been newly added. Therefore, Claims 1-16 and 18-21 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 6-12 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the outstanding Double Patenting rejection were overcome.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 21, the limitation recites, “wherein the distribution of the at least one module to the at least one module loader occurs in parallel.” However, the limitation refers to the distribution occurring in parallel, but not the task or operation to which it is being performed in parallel. That is, a task cannot be performed in parallel to itself, as performing something in parallel would require two tasks, at minimum, for the first task to be performed concurrently (i.e. in parallel) with the second. As such, it is unclear to what task or operation the distribution of the limitation is being performed in parallel. For the purposes of examination, the claim is interpreted to read, “wherein the distribution of the at least one module to the at least one module loader occurs in parallel to a second computing task.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 13, 15, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al., US 2005/0086667 A1 (as listed in the IDS), and in view of Butera et al., US 2018/0113838 A1.
Regarding Claim 1, Jin discloses an electronic device [Fig. 1], comprising:
a processor including a plurality of cores [multiple processors responsible for dispatch of drivers may be separate physical processors or may be separate logical processors, par 21]; and
memory electrically connected with the processor and storing instructions [the computer 700 further comprises a random access memory (RAM) or other dynamic storage device as a main memory 715 for storing information and instructions to be executed by the processors 710, par 58], wherein the instructions, when executed by the processor, cause the electronic device to:
load a plurality of modules for booting an operating system of the electronic device [once … a driver is identified, the processor executes the driver. After the execution of the driver, the processor returns to the discovered driver queue to attempt to obtain another driver ready for execution. The process continues until all the drivers are dispatched from the discovered driver queue, and the dispatching process is completed. At this point, the bootstrap processor is ready to boot the operating system (OS), par 25],
identify at least one module among the plurality of modules for which loading is not completed and for which a dependency is cleared [dependencies may exist between the drivers thereby affecting the order of execution. A driver generally is not executed until its dependencies have been satisfied. Whether a driver is ready for execution may be determined by evaluating the dependencies of the driver. At any time in an initiation process there may be multiple drivers that ready for execution that do not share any dependencies. Because there are no dependencies between these drivers, an embodiment of a scheduling algorithm may provide for execution of the ready drivers wholly or partially in parallel, par 26], and
select at least one module loader among the module loaders and distribute the at least one module to the at least one module loader [implicitly disclosed: "The process continues until all the drivers are dispatched from the discovered driver queue, and the dispatching process is completed. At this point, the bootstrap processor is ready to boot the operating system (OS), par 25].
However, Jin does not explicitly teach the steps of identify state information and priority information for each of module loaders allocated to the plurality of cores, as the at least one module is identified, and selecting a module loader based on determining an active/idle state of the state information and a priority value of the priority information.
In the analogous art of multicore and multiprocessing management, Butera teaches the steps of identify state information and priority information for each of module loaders allocated to the plurality of cores, as the at least one module is identified, and selecting a module loader based on determining an active/idle state of the state information and a priority value of the priority information [controller selecting a configuration vector in an idle state based on the priority number of the configuration vector (the configuration vector being equivalent to a module loader, as virtual circuits (VCs) may include processor tiles, and processor tiles of VCs may include a configuration vector, and a configuration vector in turn may represent a VC segment including the processor tile; that is, a configuration vector, presenting VC segments, may be used to perform tasks based on the configurations loaded within), par 113].
It would have been obvious to one of ordinary skill in the art, having the teachings of Jin and Butera before him before the effective filing date of the claimed invention, to incorporate the state and priority information identification as taught by Butera, into the device as disclosed by Jin, to ensure efficient use of system resources [Butera, par 67].
Regarding Claim 5, Jin and Butera disclose the electronic device of Claim 1. Butera further teaches selecting the at least one module loader based on whether the at least one module loader is in an idle state [controller selecting a configuration vector in an idle state based on the priority number of the configuration vector (the configuration vector being equivalent to a module loader, as virtual circuits (VCs) may include processor tiles, and processor tiles of VCs may include a configuration vector, and a configuration vector in turn may represent a VC segment including the processor tile; that is, a configuration vector, presenting VC segments, may be used to perform tasks based on the configurations loaded within), par 113].
Regarding Claim 13, Jin discloses an operation method of an electronic device [using the device of Fig. 1]. Claim 13 repeats the same limitations as recited in Claim 1, and is rejected accordingly.
Regarding Claim 15, Jin and Butera disclose the operation method of Claim 13. Claim 15 repeats the same limitations as recited in Claim 3, and is rejected accordingly.
Regarding Claim 21, Jin and Butera disclose the electronic device of Claim 1. Jin further discloses wherein the distribution of the at least one module to the ate least one module loader occurs in parallel [a symmetric scheduling algorithm is provided that doesn't differentiate between a bootstrap processor (BSP) and other processors in dispatching EFI drivers in parallel, thereby allowing efficient parallel operations, par 18].
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jin and Butera, and further in view of Sauzede et al., US 9,600,397 B2 (as listed in the IDS).
Regarding Claim 2, Jin and Gillespie disclose the electronic device of Claim 1. However, the combination of references does not explicitly teach wherein the instructions that, when executed by the processor, further cause the electronic device to identify the at least one module based on a module information table stored in the memory.
In the analogous art of loading software modules, Sauzede teaches identifying the at least one module based on a module information table stored in the memory [the different memory addresses and identifiers of the different sections of the module have, for example, been stored within a predetermined variable (a table, for example) within the memory MM, col. 4, ll. 35-38].
It would have been obvious to one of ordinary skill in the art, having the teachings of Jin, Butera, and Sauzede before him before the effective filing date of the claimed invention, to incorporate the module identification as taught by Sauzede into the device as disclosed by Jin and Butera, to allow for checking of successful loading of software modules [Sauzede, col. 1, ll. 38-41].
Regarding Claim 14, Jin and Butera disclose the operation method of Claim 13. Claim 14 repeats the same limitations as recited in Claim 2, and is rejected accordingly.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jin, Butera, and further in view of Gillespie et al., US 2011/0283098 A1 (as listed in the IDS).
Regarding Claim 3, Jin and Butera disclose the electronic device of Claim 1. However, the combination of references does not explicitly teach identifying the state information and the priority information based on a core information table stored in the memory.
In the analogous art of system boot management, Gillespie teaches identifying the state information and the priority information based on a core information table stored in the memory [the first processor 114 periodically queries the second processor 116 or checks the status of a shared table to determine when drivers have been fetched and are ready to be executed, par 18].
It would have been obvious to one of ordinary skill in the art, having the teachings of Jin and Butera before him before the effective filing date of the claimed invention, to incorporate the state and priority information identification as taught by Gillespie, into the device as disclosed by Jin and Butera, to reduce device boot times [Gillespie, par 1].
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jin, Butera, and Sauzede, and further in view of Yang et al., US 2018/0307498 A1.
Regarding Claim 4, Jin, Butera, and Sauzede disclose the electronic device of Claim 2. However, the combination of references does not explicitly teach wherein the instructions that, when executed by the processor, further cause the electronic device to: update the module information table based on the at least one module loader for which loading of the distributed at least one module is completed.
In the analogous art of driver loading, Yang teaches updating the module information table based on the at least one module loader for which loading of the distributed at least one module is completed [when the server determines that the VM is successfully started (before the VM loads the driver or after the VM loads the driver), the server may further update the first mapping table according to the correspondence between the first global index and the VM, par 66].
It would have been obvious to one of ordinary skill in the art, having the teachings of Jin, Butera, Sauzede, and Yang before him before the effective filing date of the claimed invention, to incorporate the module information updating as taught by Yang into the device as disclosed by Jin, Butera, and Sauzede to prevent reallocation of functions already assigned [Yang, par 66].
Regarding Claim 16, Jin, Butera, and Sauzede disclose the operation method of Claim 14. Claim 16 repeats the same limitations as recited in Claim 4, and is rejected accordingly.
Response to Arguments
Applicant’s arguments filed 01/15/26 have been considered but are moot due to the new rejection based on the references cited above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175