Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1.
b. Claims 1-8 are pending on the application.
Drawings
2. The drawings were received on 06/20/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 06/20/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Recited to claim 4: The language “any one of claim 1” renders the scope indefinite as the phase is typically used for multiple dependency, e.g. “any one of claims 1-3”. We cannot pick “any one of” when the choice is singular claim 1. Word omitted. In the interest of compact prosecution, this claim will be read as, “to claim 1”.
Recited to claim 8: The language “any one of claim 1” renders the scope indefinite as the phase is typically used for multiple dependency, e.g. “any one of claims 1-3”. We cannot pick “any one of” when the choice is singular claim 1. Word omitted. In the interest of compact prosecution, this claim will be read as, “to claim 1”.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-2 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al (Pat No.: US 7,843,716 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Kang et al in Figures 1-10 are directly discloses a non-volatile memory device (memory device 1, Figures 1, 7 and 10) comprising:
a first current mirror (a first current mirror 142, Figs. 7 and 10);
a second current mirror (a second current mirror 144 and 145, Figs. 7 and 10);
a first resistor (a memory cell resistor MC at (3,3), Figs. 7 and 10) portion connected to a first MOS transistor included in the first current mirror (a current memory cell Icell1, Figs. 7 and 10);
a second resistor (a reference cell resistor RC at (3,3) and at(4,3), Figs. 10 and 7) portion connected to a second MOS transistor included in the second current mirror (a current reference cell Iref1, Figs. 7 and 10); and
a sensing (a sense amplifier 146, Figs 7 and 10) portion configured to sense a magnitude relationship between a first current (a current memory cell Icell1) through the first MOS transistor and a second current (a current reference cell Iref1) through the second MOS transistor (the first current mirror 142 and the second current mirror 144, 145 generate the output current Icell2 and Iref1, Iref2 coupled to the sense amplifier 145, Figs, 7 and 10),
wherein
the first resistor (the memory cell resistor MC at (3,3), Figs 7 and 10) portion includes a first memory element, which is programmable, and according to whether the first memory element is programmed, a resistance value of the first resistor portion changes (the sense amplifier 146 coupled to the first and second current mirror circuit 142 and 144, 145 for compare a level of a current flowing through the selected memory cell MC and a bias level varying to a cell current flowing through each selected reference cell resistor RC, see at least in Figures 7, 10, column 8, lines 13-55 and column 9, lines 49-67 and the related disclosures).
Regarding dependent claim 2, Kang et al in Figures 1-10 are directly discloses a non-volatile memory device (memory device 1, Figures 1, 7 and 10) the first resistor (the memory cell resistor MC at (3,3), Figs 7 and 10) portion includes: a first resistor element connected to the first MOS transistor (a mos transistors mp1, mp2, Fig. 10); a second resistor element connected in series with the first resistor element (a mos transistor mp3, mp4, Fig. 10); and the first memory element connected in parallel with the second resistor element (the mos transistors mp1, mp2 , mp3 and mp4 are coupled to the sense amplifier 146, Figs. 7 and 10).
Regarding dependent claim 8, Kang et al in Figures 1-10 are directly discloses a non-volatile memory device (memory device 1, Figures 1, 7 and 10) further comprising: a clamp circuit (a read circuit 140, Fig. 1) configured to clamp a gate voltage fed to a gate of the first memory element at an upper-limit voltage (the read circuit 140 may compare a first and a second bias level varying to a cell current flowing through the selected nonvolatile memory cell MC and reference cell RC, column 6, lines 54-63).
Allowable Subject Matter
7. Claims 3-7, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 3, the prior art fails to tech or suggest the claimed limitations, namely the first memory element stores first characteristics corresponding to a relationship between a gate voltage applied to a gate of the first memory element and an on resistance thereof as observed before the first memory element is programmed, the first memory element stores second characteristics corresponding to a relationship between the gate voltage and the on resistance as observed after the first memory element is programmed, and a read operation is executed using the gate voltage limited within a range between a first predetermined voltage, which is the gate voltage that divides the first characteristic between regions in which the on resistance is high and low respectively, and a second predetermined voltage, which is the gate voltage that divides the second characteristic between regions in which the on resistance is high and low respectively.
With respected to dependent claims 4-7, the prior art fails to tech or suggest the claimed limitations, namely a gate of the first memory element can be fed with, as a gate voltage, a supply voltage, and when during start-up of the supply voltage the gate voltage reaches a lower-limit voltage, the first and second currents start to pass.
[Claim 5] The non-volatile memory according to claim 4, further comprising: a constant current source configured to supply the first and second current mirrors with a constant current, wherein when the gate voltage reaches the lower-limit voltage, the constant current source starts to supply the constant current, further comprising: a second memory element connected to a node to which the first and second resistor portions are connected, the second memory element being used without being programmed, wherein a gate of the second memory element is connected to the gate of the first memory element, the second memory element is connected to all of a plurality of sets each comprising the first and second resistor portions.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Amanai et al (US. 8,004,902 B2) discloses a nonvolatile memory device includes a memory cell that store data.
Murata (US. 2010/0329025 A1) discloses a readout circuit including a memory cell array that includes a readout target memory cell.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov