Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 18/749105 has claims 1-20 pending. The effective filing date of this application is 12/28/2023.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7-11 and 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (2019/0164615) hereinafter Kim in view of Park et al (2021/0208815) hereinafter Park.
Regarding claim 1, Kim discloses A method of operating a storage device, the method comprising:
transmitting a first command set corresponding to a first read scheme to a nonvolatile memory (Kim: [0092]: “it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”) based on a data read request having a first attribute (Kim: [0092]: “The read request monitor 1205 may receive the read request information Inf_RQ from the read request buffer 1201. The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”), the data read request being received from a device external to the storage device or internally generated in the storage device (Kim: [0011]: “The memory controller may include a read request buffer configured to receive a read request from a host, a command generator configured to receive the read request from the read request buffer and generate a read command based on the received read request, and a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request”),
determining that an attribute of the data read request has changed (Kim: [0092]: “The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”); and
transmitting the first command set, in place of the second command set, to the nonvolatile memory or transmitting the second command set, in place of the first command set, to the nonvolatile memory, based on determining that the attribute of the data read request has changed (Kim: [0092]: “If it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”).
Kim does not disclose the rest of the limitations.
However, Park discloses:
the first command set including a data read command and a first number of status check commands (Park: [0008]: “issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array in response to the first command, issuing, by the controller, in a first read mode, a second command for transferring to the controller status information indicating whether a read operation of the memory cell array according to the first command has been completed”), or
transmitting a second command set corresponding to a second read scheme to the nonvolatile memory based on the data read request having a second attribute, the second command set including the data read command and a second number of status check commands, the second read scheme being different from the first read scheme, the second attribute being different from the first attribute, the second number being different from the first number;
receiving read data corresponding to the data read command from the nonvolatile memory (Park: [0008]: “transferring, by the nonvolatile memory device to the controller, the first data to the controller”).
Disclosures by Kim and Park are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim to include response information indicating a read operation has been completed disclosed by Park. The motivation for including the response information indicating a read operation has been completed by paragraph [0005] of Park is for improving efficiency of input/output operations between the nonvolatile memory device and the controller.
Regarding claim 7, Kim combined further discloses The method of claim 1, wherein the attribute of the data read request is determined based on a type of the data read request (Kim: [0011]: “determine, based on a stream ID of the received read request, whether the received read request is a sequential read request”).
Regarding claim 8, Kim combined further discloses The method of claim 7, wherein the data read request is one of an external read request that is received from a host device located outside the storage device, an internal read request that is internally generated in the storage device, a random read request associated with discontinuous logical addresses, or a sequential read request associated with continuous logical addresses (Kim: [0011]: “determine, based on a stream ID of the received read request, whether the received read request is a sequential read request with respect to an immediately previous read request having the same stream ID as the received read request”).
Regarding claim 9, Kim combined further discloses The method of claim 1, wherein the attribute of the data read request is determined based on a queue depth that represents a number of a plurality of data input/output (I/O) requests waiting to be performed in the storage device (Kim: Fig. 3: the number of read request in RQ; [0074]: “The number of received read requests having consecutive addresses at which it is determined that sequential read requests”).
Regarding claim 10, Kim combined further discloses The method of claim 9, wherein
when the queue depth is less than a reference value, the data read request has the first attribute, and the first command set corresponding to the first read scheme is transmitted to the nonvolatile memory (Kim: [0074]: “the memory controller 1200 may also determine that sequential read requests are being received when ten or more read requests for data having consecutive addresses are successively received”), or
when the queue depth is greater than or equal to the reference value, the data read request has the second attribute, and the second command set corresponding to the second read scheme is transmitted to the nonvolatile memory.
Regarding claim 11, Kim combined further discloses The method of claim 1, wherein:
the data read request is received from a host device located outside the storage device (Kim: [0077]: “a plurality of read requests RQ1 to RQ4 may be transmitted to the memory system 1000 by a plurality of applications App.1 to App.4 that are internally executed in the hos”), and
the attribute of the data read request is determined based on a characteristic of the host device (Kim: [0078]: “the read requests RQ1 to RQ4, generated by respective applications App.1 to App.4, may be shuffled and transmitted to the memory system 1000. Therefore, when the read requests generated by respective applications App.1 to App.4 are sequential read requests”).
Regarding claim 13, Kim combined further discloses The method of claim 1, wherein:
the storage device includes a plurality of physical functions (Kim: [0011]: “The memory controller may include a read request buffer configured to receive a read request from a host, a command generator configured to receive the read request from the read request buffer and generate a read command based on the received read request, and a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request with respect to an immediately previous read request having the same stream ID as the received read request”), and
the attribute of the data read request is determined based on characteristics of the plurality of physical functions (Kim: [0011]: “a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request with respect to an immediately previous read request having the same stream ID as the received read request”).
Regarding claim 14, Kim combined further discloses The method of claim 1, further comprising: determining the attribute of the data read request (Kim: [0011]: “a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request with respect to an immediately previous read request having the same stream ID as the received read request”).
Regarding claim 15, Kim combined further discloses The method of claim 14, wherein the attribute of the data read request is determined based on at least one of a type of the data read request (Kim: [0011]: “a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request with respect to an immediately previous read request having the same stream ID as the received read request”), a queue depth of the storage device, a characteristic of a host device that is located outside the storage device and provides the data read request, and characteristics of a plurality of physical functions that are included in the storage device.
Regarding claim 16, Kim discloses A storage device comprising:
at least one nonvolatile memory (Kim Fig. 1: memory device 1110; [054]: “the memory device 1110 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate SDRAM (GDDR SDRAM), a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM) or a flash memory”); and
a storage controller configured to control an operation of the nonvolatile memory (Kim: Fig. 1: memory controller 1200), wherein the storage controller is configured to:
transmit a first command set corresponding to a first read scheme to the nonvolatile memory (Kim: [0092]: “it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”) based on a data read request having a first attribute (Kim: [0092]: “The read request monitor 1205 may receive the read request information Inf_RQ from the read request buffer 1201. The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”), or
transmit a second command set corresponding to a second read scheme to the nonvolatile memory based on the data read request having a second attribute, the second command set including the data read command and a second number of status check commands, the second read scheme being different from the first read scheme, the second attribute being different from the first attribute, the second number being different from the first number,
the data read request being received from a device external to the storage device or internally generated in the storage device (Kim: [0011]: “The memory controller may include a read request buffer configured to receive a read request from a host, a command generator configured to receive the read request from the read request buffer and generate a read command based on the received read request, and a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request”),
determining that an attribute of the data read request has changed (Kim: [0092]: “The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”); and
transmit the first command set, in place of the second command set, to the nonvolatile memory or transmit the second command set, in place of the first command set, to the nonvolatile memory, based on determining that that attribute of the data read request has changed (Kim: [0092]: “If it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”).
Kim does not disclose the first command set including a data read command and a first number of status check commands and receive read data corresponding to the data read command from the nonvolatile memory.
However, Park discloses the first command set including a data read command and a first number of status check commands (Park: [0008]: “issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array in response to the first command, issuing, by the controller, in a first read mode, a second command for transferring to the controller status information indicating whether a read operation of the memory cell array according to the first command has been completed”),
receive read data corresponding to the data read command from the nonvolatile memory (Park: [0008]: “transferring, by the nonvolatile memory device to the controller, the first data to the controller”).
Disclosures by Kim and Park are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim to include response information indicating a read operation has been completed disclosed by Park. The motivation for including the response information indicating a read operation has been completed by paragraph [0005] of Park is for improving efficiency of input/output operations between the nonvolatile memory device and the controller.
Regarding claim 17, Kim combined further discloses The storage device of claim 16, wherein the storage controller includes:
an analysis logic circuit configured to obtain at least one parameter by analyzing the data read request (Kim: [0070]: “The memory controller 1200 may analyze a plurality of received read requests, and may perform a read-look-ahead (RLA) operation. That is, when the read requests received from the host 2000 indicate consecutive addresses, the memory controller 1200 may determine that the corresponding read requests are sequential read requests”);
a determination logic circuit configured to generate a determination signal representing the attribute of the data read request based on the parameter (Kim: [0013]: “the read request monitor may be configured to, when the received read request is determined to be the sequential read request, generate a control signal for controlling the command generator to generate a read-ahead command”); and
a read scheme control logic circuit configured to output the first command set or the second command set based on the determination signal (Kim: [0014]: “the command generator may be configured to generate the read-ahead command in response to the control signal and transfer the read-ahead command to the memory device”).
Regarding claim 18, Kim combined further discloses The storage device of claim 17, wherein the read scheme control logic circuit is configured to generate only one of the first command set and the second command set based on the determination signal (Kim: [0014]: “the command generator may be configured to generate the read-ahead command in response to the control signal and transfer the read-ahead command to the memory device, wherein the read-ahead command is configured to perform a read-look-ahead operation on data corresponding to an address consecutive to an address of the received read request”).
Regarding claim 19, Kim combined further discloses The storage device of claim 17, wherein the read scheme control logic circuit includes:
a first logic circuit configured to generate the first command set corresponding to the first read scheme (Kim: [0092]: “The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”);
a second logic circuit configured to generate the second command set corresponding to the second read scheme (Kim: [0069]: “The read requests RQ from the host 2000 are transferred to the memory controller 1200 in the memory system 1000. The memory controller 1200 may generate a read command based on the received read requests RQ, and may transfer the read command to the memory device 1100”; [0087]: “read requests received by a memory controller of the system are determined to be random read requests”); and
a multiplexer configured to output the first command set corresponding to the first read scheme or the second command set corresponding to the second read scheme based on the determination signal (Kim: [0092]: “it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park and further in view of Khalili et al (2020/0034061) hereinafter Khalili.
Regarding claim 2, Kim and Park do not disclose the current limitations of claim 2.
However, Khalili discloses The method of claim 1, wherein: the first read scheme improves latency performance of a data read operation (Khalili: [0020]: “a system that can access a storage media with a focus on latency or a focus on bandwidth depending on the number of read requests pending”; [0038]: “when there are no reads outstanding, media controller 130 will be in sector-read mode to optimize for latency”), and the second read scheme improves bandwidth performance of the data read operation (Khalili: [0020]: “media controller 130 to dynamically swap between a read mode focused on read latency and a read mode focused on bandwidth utilization”).
Disclosures by Kim, Park and Khalili are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park to include dynamically switching between a first read mode of accessing data chunks sequentially and a second read mode of prefetching data blocks disclosed by Khalili. The motivation for dynamically switching between a first read mode of accessing data chunks sequentially and a second read mode of prefetching data blocks by paragraph [0017] of Khalili is for optimizing media access for either read latency or bandwidth.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park in view of Khalili and further in view of Kanamori et al (2021/0216248) hereinafter Kanamori.
Regarding claim 3, Part further discloses The method of claim 2, wherein the second number (Park: [0006]: “issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array into a page buffer of the nonvolatile memory device, in response to the first command, issuing, by the controller, a second command to the nonvolatile memory device, and outputting, by the nonvolatile memory device to the controller, in response to the second command, status information indicating whether a read operation according to the first command has been completed”) is less than the first number (disclosed by Kanamori below);
Disclosures by Kim, Park and Khalili are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Khalili to include response information indicating a read operation has been completed disclosed by Park. The motivation for including the response information indicating a read operation has been completed by paragraph [0005] of Park is for improving efficiency of input/output operations between the nonvolatile memory device and the controller.
Kim, Park and Khalili do not disclose the rest limitations of the current claim.
However, Kanamori discloses the first number (Kanamori: [0073]: “The controller 3 issues a first status read command SR1 to the NAND flash memory 2. With the status read command SR1, the controller 3 acquires the status of the NAND flash memory 2 and a read operation duration time T1”; [0075]: “When the read operation duration time T1 has elapsed, the controller 3 issues a second status read command SR2 to the NAND flash memory 2”)).
Disclosures by Kim, Park, Khalili and Kanamori are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park/Khalili to include performing a status polling to confirm the execution status of the flash memory disclosed by Kanamori. The motivation for performing a status polling to confirm the execution status of the flash memory by paragraph [0065] of Kanamori is for improving the performance of the entire memory system.
Regarding claim 4, Kanamori and Park further discloses The method of claim 3, wherein the first number is two and the second number is one (regarding claim 3 the number of issuing status read command are 2 as disclosed by Kanamori and the number of a status read command is 1 as disclosed by Park).
Disclosures by Kim, Park, Khalili and Kanamori are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park/Khalili to include performing a status polling to confirm the execution status of the flash memory disclosed by Kanamori. The motivation for performing a status polling to confirm the execution status of the flash memory by paragraph [0065] of Kanamori is for improving the performance of the entire memory system.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park and further in view of Chung et al (2014/0089568) hereinafter Chung.
Regarding claim 5, Kim and Park do not disclose the current limitations of claim 5.
However, Chung discloses The method of claim 1, wherein, in the first read scheme:
the data read command is transmitted to the nonvolatile memory, during a first time interval after the data read command is transmitted, a first operation in which the read data is retrieved from the nonvolatile memory is performed (Chung: Fig. 8A: eMMC returns a response R1 to the data read command RD to the host; [0065]: “Referring to FIG. 8A, when a host sends a data read command RD or 411 to the eMMC via the command/response line 102, the eMMC returns a response R1 or 412 to the data read command RD or 411 to the host via the command/response line 102 ”),
after the first time interval, a first status check command for checking a completion of the first operation is transmitted to the nonvolatile memory (Fig. 8A: data read command 431 is sent after the response R1; [0065]: “The eMMC prepares to read data from a flash memory NAND in response to the data read command RD or 411 (431)”),
during a second time interval after the first time interval and after the first status check command is transmitted, a second operation in which the read data is output from the nonvolatile memory and a third operation in which an execution of a next command after the data read command is prepared are performed (Fig. 8A: [0065]: “reads data from flash memory cells (432 and 433), and transmits the "read data" 421 to the host via the data bus 103. In this normal read operation, the host can send a subsequent data read command RD or 414 only after receiving the data 421 corresponding to the data read command RD or 411”), and
after the second time interval, a second status check command for checking a completion of the third operation is transmitted to the nonvolatile memory (Fig. 8A: data read command 431 is sent after the read command RD).
Disclosures by Kim, Park and Chung are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park to include correcting input timing for the data signals provided by the eMMC disclosed by Chung. The motivation for correcting input timing for the data signals provided by the eMMC by paragraph [0002] of Chung is for securing an improved data valid window for data received by a host.
Regarding claim 6, Kim and Park do not disclose the current limitations of claim 6.
However, Chung further discloses The method of claim 5, wherein, in the second read scheme:
the data read command is transmitted to the nonvolatile memory, during a third time interval after the data read command is transmitted, the first operation and the third operation are performed (Chung: Fig. 8B: first read command 441 is sent from the host. After the eMMC returns a response R1 to the first data read command 441 to the host, the host sends the second multi-queue read command RD or 443 for reading next data to the eMMC; [0067]: “Upon receiving the response R1 or 442 from the eMMC 300, the host 200 sends a second multi-queue read command RD or 443. In other words, the host 200 may send the second multi-queue read command RD or 443 for reading next data to the eMMC 300 during a time period in which data corresponding to the first multi-queue read command RD or 441 is being retrieved, but has not yet been received”),
after the third time interval, a third status check command for checking a completion of the first operation and the third operation is transmitted to the nonvolatile memory (Fig. 8B: data read command 461 and 471 are sent after the response R1), and
during a fourth time interval after the third time interval and after the third status check command is transmitted, the second operation is performed (Fig. 8B: eMMC reads data from flash memory cells (463 and 473)).
Disclosures by Kim, Park and Chung are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park to include correcting input timing for the data signals provided by the eMMC disclosed by Chung. The motivation for correcting input timing for the data signals provided by the eMMC by paragraph [0002] of Chung is for securing an improved data valid window for data received by a host.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park and further in view of Roberts (2022/0113881) hereinafter Roberts.
Regarding claim 12, Kim and Park do not disclose the current limitations of claim 12.
However, Roberts discloses The method of claim 11, wherein:
the storage device is controlled by a plurality of host devices (Roberts: Fig. 1: memory system connects to at least one host system 102: [0024]: “the apparatus 100 includes at least one host 102 (e.g., host system or host device)”),
a plurality of domains are formed by the plurality of host devices ([0021]: “there is variability in host memory sensitivity (e.g., bandwidth or latency sensitivity), which the adaptive controller can monitor through memory performance metrics of the host or a processor of the host”), and
the characteristic of the host device corresponds to characteristics of the plurality of domains ([0022]: “the adaptive controller can determine (e.g., predict) memory performance demand of the host processor, such as latency demand or bandwidth demand, for the memory domain. The adaptive controller may alter, using the determined memory performance demand, a voltage or a temperature of the memory domain to enable memory access performance that is tailored to meet the memory performance demand of the host processor”).
Disclosures by Kim, Park and Roberts are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park to include determining memory performance demand of the host processor for the memory domain disclosed by Roberts. The motivation for determining memory performance demand of the host processor for the memory domain by paragraph [0021] of Roberts is for optimizing performance of the memory domain for short-term or long-term changes in memory access.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park in view of Chung and further in view of Khalili.
Regarding claim 20, Kim discloses A method of operating a storage device, the method comprising:
receiving a data read request from a host device (Kim: [0092]: “it is determined that the corresponding read request is a sequential read request, the read request monitor 1205 may generate the control signal CTR for generating a command for executing a read-look-ahead operation, and may transfer the control signal CTR to the command generator 1203. As described above, the command generator 1203 may generate a read command for executing the read-look-ahead operation in response to the control signal CTR”) located outside the storage device ([0011]: “The memory controller may include a read request buffer configured to receive a read request from a host, a command generator configured to receive the read request from the read request buffer and generate a read command based on the received read request, and a read request monitor configured to receive read request information about the received read request from the read request buffer and determine, based on a stream ID of the received read request, whether the received read request is a sequential read request”);
determining an attribute of the data read request (Kim: [0092]: “The read request monitor 1205 may receive the read request information Inf_RQ from the read request buffer 1201. The read request monitor 1205 may determine, based on the received read request information Inf_RQ, whether the corresponding read request is a sequential read request or a random read request”);
receiving read data from the nonvolatile memory, the read data corresponding to the data read command that is transmitted based on the first read scheme (Kim : [0030]: “the controller may provide, during the read-look-ahead operation, the buffered data to the host when the controller determines a read request subsequent to the current read request as the sequential read request having the information of the same stream ID as the current read request”) or the second read scheme, wherein the first read scheme represents a scheme which improves latency performance of a data read operation (Kim: [0028]: “the controller is configured to perform a read-look-ahead operation on the memory device based on a number of sequential read requests”),
Kim does not disclose the rest of limitation.
However, Park discloses
transmitting a first command set corresponding to a first read scheme to a nonvolatile memory based on the data read request having a first attribute, the first command set including a data read command and a first number of status check commands (Park: [0008]: “issuing, by the controller, a first command to the nonvolatile memory device, reading, by the nonvolatile memory device, first data from a memory cell array in response to the first command, issuing, by the controller, in a first read mode, a second command for transferring to the controller status information indicating whether a read operation of the memory cell array according to the first command has been completed”); or
transmitting a second command set corresponding to a second read scheme to the nonvolatile memory based on the data read request having a second attribute, the second command set including the data read command and a second number of status check commands, the second read scheme being different from the first read scheme, the second attribute being different from the first attribute, the second number being less than the first number;
Disclosures by Kim and Park are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim to include response information indicating a read operation has been completed disclosed by Park. The motivation for including the response information indicating a read operation has been completed by paragraph [0005] of Park is for improving efficiency of input/output operations between the nonvolatile memory device and the controller.
Kim and Park do not disclose the rest of limitations
However, Chung discloses
wherein, in the first read scheme: the data read command is transmitted to the nonvolatile memory, during a first time interval after the data read command is transmitted, a first operation in which the read data is retrieved from the nonvolatile memory is performed (Chung: Fig. 8A: eMMC returns a response R1 to the data read command RD to the host; [0065]: “Referring to FIG. 8A, when a host sends a data read command RD or 411 to the eMMC via the command/response line 102, the eMMC returns a response R1 or 412 to the data read command RD or 411 to the host via the command/response line 102 ”), after the first time interval, a first status check command for checking a completion of the first operation is transmitted to the nonvolatile memory (Fig. 8A: data read command 431 is sent after the response R1; [0065]: “The eMMC prepares to read data from a flash memory NAND in response to the data read command RD or 411 (431)”), during a second time interval after the first time interval and after the first status check command is transmitted, a second operation in which the read data is output from the nonvolatile memory and a third operation in which an execution of a next command after the data read command is prepared are performed (Fig. 8A: [0065]: “reads data from flash memory cells (432 and 433), and transmits the "read data" 421 to the host via the data bus 103. In this normal read operation, the host can send a subsequent data read command RD or 414 only after receiving the data 421 corresponding to the data read command RD or 411”), and after the second time interval, a second status check command for checking a completion of the third operation is transmitted to the nonvolatile memory (Fig. 8A: data read command 431 is sent after the read command RD),
wherein, in the second read scheme: the data read command is transmitted to the nonvolatile memory, during a third time interval after the data read command is transmitted, the first operation and the third operation are performed (Chung: Fig. 8B: first read command 441 is sent from the host. After the eMMC returns a response R1 to the first data read command 441 to the host, the host sends the second multi-queue read command RD or 443 for reading next data to the eMMC; [0067]: “Upon receiving the response R1 or 442 from the eMMC 300, the host 200 sends a second multi-queue read command RD or 443. In other words, the host 200 may send the second multi-queue read command RD or 443 for reading next data to the eMMC 300 during a time period in which data corresponding to the first multi-queue read command RD or 441 is being retrieved, but has not yet been received”), after the third time interval, a third status check command for checking a completion of the first operation and the third operation is transmitted to the nonvolatile memory (Fig. 8B: data read command 461 and 471 are sent after the response R1), and during a fourth time interval after the third time interval and after the third status check command is transmitted, the second operation is performed (Fig. 8B: eMMC reads data from flash memory cells (463 and 473)).
Disclosures by Kim, Park and Chung are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park to include correcting input timing for the data signals provided by the eMMC disclosed by Chung. The motivation for correcting input timing for the data signals provided by the eMMC by paragraph [0002] of Chung is for securing an improved data valid window for data received by a host.
Kim, Part and Chung do not disclose the rest limitations.
However, Khalili discloses
wherein the second read scheme represents a scheme which improves bandwidth performance of the data read operation (Khalili: [0020]: “media controller 130 to dynamically swap between a read mode focused on read latency and a read mode focused on bandwidth utilization”).
Disclosures by Kim, Park, Chung and Khalili are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate efficiently performing read requests in real time in a multi-stream environment taught by Kim/Park/Chung to include dynamically switching between a first read mode of accessing data chunks sequentially and a second read mode of prefetching data blocks disclosed by Khalili. The motivation for dynamically switching between a first read mode of accessing data chunks sequentially and a second read mode of prefetching data blocks by paragraph [0017] of Khalili is for optimizing media access for either read latency or bandwidth.
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/HAN V DOAN/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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