Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 10, 12-15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUN et al. (cited by the applicant), hereafter referred to as “SUN”.
Regarding claims 1, 2, 6, 10, 12-15, and 19, in the embodiment of Fig. 3, Sun discloses:
A multi-stage pseudo-Doherty load modulated balanced amplifier circuit, providing an amplified radio frequency output signal (Fig. 3, power amplifier circuit, consists of multiple Doherty amplifiers per paragraph [0003], Output port 30 would inherently provide an amplified radio frequency signal in a wireless communication system per paragraph [0002], per claims 1 and 15) comprising:
a control stage comprising a control amplifier (power amplifier branch 11 functions as the control stage comprising the control amplifier);
a first balanced stage (power amplifier branch 12 forms the first balanced stage) comprising a first balanced amplifier (power amplifier sub-branch 125) and a first output coupler (coupler 211), the first balanced amplifier coupled to the first output coupler and configured to be biased in class C (paragraph [0036], N-1 branches (i.e. power amplifier branch 12 and 13) operates in Class C), the first output coupler having a port (an isolation port per claim 15, 211 isolated port as described in paragraph [0058]) connected to an output (11 output) of the control amplifier (paragraph [0058], isolated port of the coupler 211 is connected to the output port of the power amplifier branch 11, per claims 1 and 15); and
a second balanced stage (power amplifier branch 13 forms the second balanced stage) comprising a second balanced amplifier (power amplifier sub-branch 135) and a second output coupler (coupler 212), the second balanced amplifier coupled to the second output coupler (via an isolation port, as mentioned in paragraph [0058], per claim 15)(135 output to port 132 of coupler 212) and configured to be biased in class C (per paragraph [0036]), the second output coupler having an isolation port (isolated port of coupler 212, per claims 1, 6 and 15) connected to an output (note that the output of coupler 211 would inherently be a radio frequency output port as part of a wireless communication system per paragraph [0002], per claims 1 and 15) of the first balanced stage (per paragraph [0058] lines 8-10), wherein
the first balanced stage, the second balanced stage, and the control amplifier are configured to receive separate drive signals (power amplifier branches 11, 12 and 13 are shown to receive Input_1, Input_2 and Input_3 in Fig. 3, per claims 2 and 15), and
the multi-stage pseudo-Doherty load modulated balanced amplifier further comprising one or more additional balanced stages each comprising an additional balanced amplifier configured to be biased in class C (N-1 second amplifier branches operate in class C operating mode per paragraph [0006]) and an additional output coupler, the additional output coupler of each of the one or more additional balanced stages having a port driven by another stage of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit (power amplifier branch 1N function as additional balanced stages to include additional balanced amplifier and output coupler (i.e. amplifier 1N5 and coupler 21(N-1)), as shown in Fig. 3, per claims 10 and 19), and wherein
the multi-stage pseudo-Doherty load modulated balanced amplifier circuit is operable in a plurality of power modes, comprising a high power mode where the control amplifier modulates the first balanced amplifier from peak efficiency to peak output power, and the plurality of power modes comprise a high power mode where separate drive signals for the control stage and the first balanced stage change power and phase (paragraph [0071]-[0077], describes a plurality of power modes based on peak power and different phases, per claims 12-14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over SUN et al. in view of Hellberg (both cited by the applicant), hereafter referred to as “SUN” and “Hellberg”, respectively.
Regarding claims 3, 11, and 16, in the embodiment of Fig. 3, SUN discloses:
generating separate drive signals (power amplifier branches 11, 12 and 13 are shown to receive Input_1, Input_2 and Input_3 in Fig. 3, per claims 3 and 16) and two stages of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit (Fig. 3, elements 11, 12, 13, and 1N form at least two stages of the circuit per claim 11).
However, SUN is silent in teaching a digital splitter and a radio frequency power divider coupled to two stages of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit, the radio frequency power divider configured to divide power of a combined drive signal to the two stages of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit.
Hellberg teaches:
a digital splitter generating separate drive signals (as mentioned in paragraphs [0070] and [0077], digital signals from DACs to different amplifier stages (i.e. balanced amplifiers 906 and 904)) and
a radio frequency power divider (Fig. 2, RF input signal split 208) coupled to two stages of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit (shown to be coupled to control amplifier 206 as one stage per paragraph [0006] lines 4-6, and transistors 210 (labeled 208 in Fig. 2) and 212 form the second stage per paragraph [0005]), the radio frequency power divider configured to divide power of a combined drive signal to the two stages of the multi-stage pseudo-Doherty load modulated balanced amplifier circuit (Fig. 2, 208 shown to split RF IN, different amplifier stages employ different shaped drive signals per paragraph [0077]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention for the inputs of the amplifier circuit as taught by SUN (Fig. 3), to include a digital splitter as taught by Hellberg (as described in paragraphs [0070] and [0077]) to employ differently shaped drive signals to the different amplifier stages (paragraph [0077]), thereby suggesting the obviousness of such a combination. Furthermore, it would have been obvious for the amplifier circuit as taught by SUN (Fig. 3) to further include a radio frequency power divider as taught by Hellberg (Fig. 2) to control the balanced amplifier and control amplifier depending on the transition point (paragraph [0006]), thereby suggesting the obviousness of such a combination.
Claims 4, 5, 7-9, 17, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over SUN et al. and Hellberg in further view of Koren et al. and Muller et al. (all cited by the applicant), hereafter referred to as “SUN”, “Hellberg”, “Koren” and “Muller”, respectively.
Regarding claims 4, 5, 7-9, 17, 18 and 20, Sun and Hellberg discloses:
A multi-stage pseudo-Doherty load modulated balanced amplifier circuit (Sun, Fig. 3) comprising:
a control stage comprising a control amplifier (power amplifier branch 11 functions as the control stage comprising the control amplifier);
a first balanced stage (power amplifier branch 12 forms the first balanced stage) comprising a first balanced amplifier (power amplifier sub-branch 125), , and
a first output coupler (coupler 211), the first balanced amplifier coupled to the first output coupler and configured to be biased in class C (paragraph [0036], N-1 branches (i.e. power amplifier branch 12 and 13) operates in Class C), the first output coupler having an isolation port (211 isolated port) connected to an output (11 output) of the control amplifier (paragraph [0058], isolated port of the coupler 211 is connected to the output port of the power amplifier branch 11); and
a second balanced stage (power amplifier branch 13 forms the second balanced stage) comprising a second balanced amplifier (power amplifier sub-branch 135), and
a second output coupler (coupler 212), the second balanced amplifier coupled to the second output coupler (135 output to port 132 of coupler 212) and configured to be biased in class C (per paragraph [0036]), the second output coupler having a radio frequency output port (SUN, Fig. 3, Output port 30, per claim 8), and an isolation port (isolated port of coupler 212) connected to an output of the first balanced stage (per paragraph [0058] lines 8-10), the first balanced stage and the second balanced stage configured to receive separate drive signals (power amplifier branches 11, 12 and 13 are shown to receive Input_1, Input_2 and Input_3 in Fig. 3, per claim 20), and
and
a digital splitter (Hellberg, paragraphs [0070] and [0077], digital signals from DACs to different amplifier stages (i.e. balanced amplifiers 906 and 904), per claims 4, 5, 17, and 18).
However, SUN and Hellberg are silent in teaching
the digital splitter is configured to implement non-linear frequency selective functions and a controller configured to update the digital splitter based on outputs of currents sensors associated with the first balanced amplifier, the second balanced amplifier, and the control amplifier, and the amplified radio frequency output signal; wherein
a first, second, and third current sensor configured to provide an indication of direct current input power of the first balanced stage, the second balanced stage, and the control stage, and a radio frequency coupler and a controller, the radio frequency coupler connected to a radio frequency output port of the second output coupler, the radio frequency coupler coupled to the controller, and the controller coupled to the first current sensor and the second current sensor.
Koren and Muller teaches:
the digital splitter is configured to implement non-linear frequency selective functions and a controller (Muller, predistortion unit 2 uses a control signal to select complex predistortion coefficients, paragraph [0040]) configured to update the digital splitter based on outputs of currents sensors associated with the first balanced amplifier, the second balanced amplifier, and the control amplifier, and the amplified radio frequency output signal; (Koren, Fig. 4, Signal processing module 140, non-linear filter processes the signal to analog region 310 based on detected DC power input from supply voltage sensor 230, paragraphs [0041] and [0052], power sensor 290 is connected to output of non-linear amplifier 110 and sends indicator to configuration module 130, which selects pre-distortion coefficient values per paragraphs [0057]-[0058]), and
a first, second, and third current sensor configured to provide an indication of direct current input power of the first balanced stage, the second balanced stage, and the control stage (paragraph [0036]), and
a radio frequency coupler (Muller, Fig. 7, directional couplers 28 and 29), the radio frequency coupler connected to a radio frequency output port of the second output coupler (28 and 29 is connected to the output of amplifier 8), the radio frequency coupler coupled to the controller, and the controller coupled to the first current sensor and the second current sensor (Muller, Fig. 1, Current Sensor CurS).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention for digital splitter as taught by Hellberg (paragraphs [0070] and [0077]), to implement non-linear frequency selective functions as taught by Koren (Koren, paragraphs [0041] and [0052]) and a controller configured to update the digital splitter as taught by Muller (Muller, Fig. 1, paragraph [0040]) to output the baseband signal in undistorted form (paragraph [0041]), thereby suggesting the obviousness of such a combination. Furthermore, it would have been obvious to include current sensors to provide an indication of direct current input power as taught by Muller (Muller, Fig. 1, Current Sensor CurS) to the first balanced stage, the second balanced stage, and the control stage as taught by SUN (Fig. 3), to measure the operating parameters current drawn (paragraph [0036]), thereby suggesting the obviousness of such a combination. It would further be obvious for the coupler output as taught by SUN (Fig. 3) to include a radio frequency coupler as taught by Muller (Muller, Fig. 7, directional couplers 28 and 29) to ascertain the amplitude magnitude and also the phase of a signal (Muller, paragraph [0056]), thereby suggesting the obviousness of such a combination.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571) 272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights