DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
On Paragraph 1, line 8, replace “U.S. Application No. _________” with “U.S. Application No. 18/749,388”.
On Paragraph 75, line 3, insert “to” between “provide a second drive signal” and “a balanced amplifier”.
Appropriate correction is required.
Claim Objections
Claims 12-19 are objected to because of the following informality: On claim 12, line 3, insert “a” between “generating” and “test signal”. Claims 13-19 are likewise objected to under this logic by virtue of their dependency on claim 12.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the balanced amplifier" in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “a balanced amplifier” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim 7 recites the limitation “the efficiency for test sections of the load modulated balanced amplifier starting with a test section associated with a lowest power of the plurality of test sections” in lines 1-3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “an efficiency for a plurality of test sections of the load modulated balanced amplifier starting with a test section associated with a lowest power of the plurality of test sections” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claim 8 is likewise rejected under this logic by virtue of its dependency on claim 7.
Claim 9 recites the limitation “the efficiency of the pseudo-Doherty load modulated balanced amplifier” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “an efficiency of the pseudo-Doherty load modulated balanced amplifier” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-10, and 12-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Du et al. (Patent Publication Number WO 2024/045144 A1), hereafter referred to as Du.
Regarding claim 1, Du discloses:
A transceiver for driving a pseudo-Doherty load modulated balanced amplifier (Du, Fig. 7), the transceiver comprising: a digital splitter (Fig. 7, 760) configured to provide drive signals to the pseudo-Doherty load modulated balanced amplifier (Fig. 7, see connection between 760 and amplifiers 700 and 710); and a controller (Fig. 7, 702 and 712) configured to: generate a measure of efficiency of the pseudo-Doherty load modulated balanced amplifier based on an observed radio frequency output power of the pseudo-Doherty load modulated balanced amplifier and an output signal from a current sensor associated with the pseudo-Doherty load modulated balanced amplifier (Page 3, Paragraph 3, lines 1-14); and configure the digital splitter based on the measure of efficiency of the pseudo-Doherty load modulated balanced amplifier (Page 3, Paragraph 2, lines 11-13).
Regarding claim 4, Du further discloses:
wherein the controller is configured to generate measures of efficiency of the pseudo-Doherty load modulated balanced amplifier for a plurality of configurations (Du, Page 10, Paragraph 6, lines 1-7, see also Page 3, Paragraph 3, lines 1-14), and to configure the digital splitter based on the measures of efficiency of the pseudo-Doherty load modulated balanced amplifier for the plurality of configurations (Page 3, Paragraph 2, lines 11-13).
Regarding claim 5, Du further discloses:
wherein the controller is configured to generate measures of efficiency of the pseudo-Doherty load modulated balanced amplifier for a plurality of power regions (Du, Page 10, Paragraph 6, lines 1-7, see also Page 3, Paragraph 3, lines 1-14), and to configure the digital splitter based on the measures of efficiency of the pseudo-Doherty load modulated balanced amplifier for the plurality of power regions (Page 3, Paragraph 2, lines 11-13).
Regarding claim 6, Du further discloses:
wherein the plurality of power regions comprise a power region in which (i) power and phase of the drive signals change (Du, Page 10, Paragraph 7, lines 5-11) and (ii) a control amplifier is used to modulate a load of the balanced amplifier of the pseudo-Doherty load modulated balanced amplifier from peak efficiency to peak power (Page 10, Paragraph 7, lines 5-11).
Regarding claim 7, Du further discloses:
wherein the controller is configured to estimate the efficiency for test sections of the load modulated balanced amplifier starting with a test section associated with a lowest power of the plurality of test sections (Du, Fig. 7, consider test section 700, see also Page 3, Paragraph 2, lines 11-13).
Regarding claim 8, Du further discloses:
wherein each of the test sections (Fig. 7, consider test section formed by 700 and 710) is divided into a balanced stage (Fig. 7, consider 710) and a control stage (Fig. 7, consider 700), and wherein the control stage of at least one of the test sections comprises a balanced amplifier (Fig. 7, consider balanced amplifier 705/707) and a control amplifier (Fig. 7, consider control amplifier 702).
Regarding claim 9, Du further discloses:
wherein the controller is configured to estimate the efficiency of the pseudo-Doherty load modulated balanced amplifier based on an output signal from a second current sensor associated with the pseudo-Doherty load modulated balanced amplifier (Du, Page 3, Paragraph 3, lines 1-14), and wherein the current sensor and the second current sensor are associated with different stages of the pseudo-Doherty load modulated balanced amplifier (Fig. 7, consider elements 700 and 710 as different stages of the pseudo-Doherty load modulated balanced amplifier).
Regarding claim 10, Du further discloses:
wherein the controller is configured to adaptively update the digital splitter (Du, Page 3, Paragraph 2, lines 11-13 and Paragraph 3, lines 1-14).
Regarding claim 12, Du discloses:
A method of drive signal extraction for driving a pseudo-Doherty load modulated balanced amplifier (Du, Fig. 7), the method comprising: generating test signal for the pseudo-Doherty load modulated balanced amplifier (Fig. 7, consider test section 700, see also Page 3, Paragraph 2, lines 11-13); receiving an observed radio frequency output power of the pseudo-Doherty load modulated balanced amplifier associated with the test signal (Page 3, Paragraph 3, lines 1-14); determining efficiency of the pseudo-Doherty load modulated balanced amplifier based on the observed radio frequency output power (Page 3, Paragraph 3, lines 1-14); and configuring a digital splitter based on the determining (Page 3, Paragraph 2, lines 11-13), wherein the digital splitter provides drive signals for stages of the pseudo-Doherty load modulated balanced amplifier (Fig. 7, consider connection between digital splitter 760 and amplifying stages 700 and 710).
Regarding claim 13, Du further discloses:
wherein the determining efficiency comprises determining efficiency for a plurality of power regions (Du, Page 10, Paragraph 6, lines 1-7, see also Page 3, Paragraph 3, lines 1-14).
Regarding claim 14, Du further discloses:
wherein the plurality of power regions include a power region where power and phase of the drive signals change (Du, Page 10, Paragraph 7, lines 5-11).
Regarding claim 15, Du further discloses:
wherein the plurality of power regions include a power region where a control amplifier (Du, Fig. 7, see control amplifiers 702 and 712) is used to modulate a balanced amplifier of the pseudo-Doherty load modulated balanced amplifier from peak efficiency to peak power (Page 10, Paragraph 7, lines 5-11).
Regarding claim 16, Du further discloses:
wherein the determining efficiency is based on output signals from current sensors associated with component amplifiers of the pseudo-Doherty load modulated balanced amplifier (Du, Page 3, Paragraph 3, lines 1-14, consider also Fig. 7, with elements 700 and 710 as different stages of the pseudo-Doherty load modulated balanced amplifier).
Regarding claim 17, Du further discloses:
wherein the pseudo-Doherty load modulated balanced amplifier is a multi-stage pseudo-Doherty load modulated balanced amplifier having three or more stages (Du, Fig. 14, consider 810, 820, and 830 as three stages of the pseudo-Doherty load modulated balanced amplifier), and wherein the generating, the receiving, and the determining are performed for each stage of a multi-stage load modulated balanced amplifier (Page 3, Paragraph 3, lines 1-14).
Regarding claim 18, Du further discloses:
wherein the multi-stage pseudo-Doherty load modulated balanced amplifier comprises a control amplifier (Du, Fig. 7, 702), a first balanced amplifier (Fig. 7, see 705 and 707), a first output coupler (Fig. 7, 704) configured to combine output signals of the first balanced amplifier (Fig. 7, see that coupler 704 combines signals from 705 and 707) and having an isolation port connected to an output of the control amplifier (Fig. 7, see connection between coupler 704 and control amplifier 702), a second balanced amplifier (Fig. 7, see 715 and 717), and a second output coupler (Fig. 7, 714) configured to combine output signals of the second balanced amplifier (Fig. 7, see that coupler 714 combines signals from 715 and 717) and having an isolation port connected to a port of the first output coupler (Fig. 7, see connection between 704 and 714).
Regarding claim 19, Du further discloses:
wherein: the generating, the receiving, and the determining are performed for test sections of the pseudo-Doherty load modulated balanced amplifier starting with a section associated with a lowest power of the test sections (Du, Fig. 7, consider test section 700, see also Page 3, Paragraph 2, lines 11-13); each of the test sections (Fig. 7, consider test section formed by 700 and 710) is divided into a balanced stage (Fig. 7, consider 710) and a control stage (Fig. 7, consider 700); and the control stage of at least one of the test sections comprises a balanced amplifier (Fig. 7, consider balanced amplifier 705/707) and a control amplifier (Fig. 7, consider control amplifier 702).
Regarding claim 20, Du discloses:
A system (Du, Fig. 7) comprising: a digital splitter (Fig. 7, 760) configured to split a combined drive signal into at least a first drive signal and a second drive signal (Fig. 7, see connection between 760 and amplifiers 700 and 710); a pseudo-Doherty load modulated balanced amplifier (Fig. 7, see 700 and 710) comprising a control amplifier (Fig. 7, 702) configured to amplify the first drive signal (Fig. 7, see connection between 702 and 760), an input coupler (Fig. 7, 703) configured to receive the second drive signal (Fig. 7, see connection between 702 and 760), and a balanced amplifier (Fig. 7, see 705 and 707) having inputs connected to the input coupler (Fig. 7, see connection between 705, 707, and 703); and a controller (Fig. 7, 702 and 712) configured to: determine a measure of efficiency of the pseudo-Doherty load modulated balanced amplifier based on an observed radio frequency output power of the pseudo-Doherty load modulated balanced amplifier and an output signal from a current sensor associated with the pseudo-Doherty load modulated balanced amplifier (Page 3, Paragraph 3, lines 1-14); and configure the digital splitter based on the measure of efficiency of the pseudo-Doherty load modulated balanced amplifier (Page 3, Paragraph 2, lines 11-13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Du as applied to claim 1 above, and further in view of Koren et al. (Patent Publication Number US 2011/0140779 A1), as cited by applicant, hereafter referred to as Koren.
Regarding claim 2, Du fails to disclose:
wherein the digital splitter comprises frequency selective non-linear filters.
However, Koren teaches wherein the digital splitter comprises frequency selective non-linear filters (Koren, Fig. 8, 140, see also Paragraph 41, lines 1-6).
Du and Koren are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Du to incorporate the teachings of Koren to include the filters of Koren in the circuit of Du, which would have the effect of enabling compensation for non-linearity in the amplifier of Du (Koren, Paragraph 40, lines 1-5).
Regarding claim 3, Du fails to disclose:
wherein the digital splitter further comprises a frequency selective linear filter cascaded with a frequency selective non-linear filter of the frequency selective non-linear filters.
However, Koren further teaches wherein the digital splitter further comprises a frequency selective linear filter (Koren, Fig. 8, see 606 and 608) cascaded with a frequency selective non-linear filter of the frequency selective non-linear filters (Fig. 8, see cascaded connection between 140 and 606/608).
Du and Koren are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Du to incorporate the teachings of Koren to include the filters of Koren in the circuit of Du, which would have the effect of enabling compensation for non-linearity in the amplifier of Du (Koren, Paragraph 40, lines 1-5).
Regarding claim 11, Du fails to disclose:
further comprising a digital predistortion system having an output connected to an input of the digital splitter.
However, Koren teaches further comprising a digital predistortion system having an output connected to an input of the digital splitter (Koren, Fig. 8, 140, consider connection between output of 140 and input of power amplifier 110, and that the digital splitter 760 of Du, Fig. 7, is at the input of its power amplifier).
Du and Koren are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Du to incorporate the teachings of Koren to include the digital predistortion system of Koren in the circuit of Du, which would have the effect of enabling compensation for non-linearity in the amplifier of Du (Koren, Paragraph 40, lines 1-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ding et al. (Patent Publication Number WO 2024/032553 A1) discloses (Fig. 3) a pseudo-Doherty load modulated balanced amplifier with multiple stages.
Liu (Patent Publication Number US 2014/0320214 A1) discloses (Fig. 16) a pseudo-Doherty load modulated balanced amplifier with multiple stages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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