DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The examiner has reviewed the remarks with respect to the 112 issue and with further analysis of claims 8-14, it has been determined that the claims as written, with remarks, overcome the 112 issue. A summary of the interview was filed by applicants representative and is of record.
The examiner maintains the art rejection in light of the Guo et al reference, The NPL reference to Guo et al, see figure description, shows a system/protocol/algorithm where
a quantum fan-out operation is highlighted by constructing a fan-out gate using ladders of
CNOT gates(parallel) in a constant depth( 1 layer of operation shown), using a dynamic
quantum circuit(see figure 1, steps a thru c with reversal of process b and c to return the
ancillary qubits).
Regarding the “ladder” the examiner maintains the “ladder” could simply be oriented differently(REFERENCE) if the claim is read broadly, see figures below for example:
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REFERENCE
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APPLICATION
The examiner would like to discuss the application with applicants representative in hopes of advancing prosecution.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guo et al (NPL citation by Applicants ( “Implementing a Fast Unbounded Quantum Fanout Gate Using Power-Law Interactions” July 2020, arXiv:2007.00662v1 [quant-ph])
Re claims 1 and 8:
The NPL reference to Guo et al, see figure below, shows a system/protocol/algorithm where
a quantum fan-out operation is highlighted by constructing a fan-out gate using ladders of
CNOT gates(parallel) in a constant depth( 1 layer of operation shown), using a dynamic
quantum circuit(see figure 1, steps a thru c with reversal of process b and c to return the
ancillary qubits); and implementing said
quantum fan-out operation by said fan-out gate using ancilla qubits(see figure highlights by
examiner) and feed-forward(“broadcast”)
operations.
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Re claims 2 and 9: fan-out gate is constructed from two ladders(neighboring one step ladders)
of CNOT gates(one step ladders shown).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference to Guo et al(NPL cited by applicants( “Implementing a Fast Unbounded Quantum Fanout Gate Using Power-Law Interactions” July 2020, arXiv:2007.00662v1 [quant-ph])) in view of Chen et al (US 2023/0196156).
The NPL reference to Guo et al, see figure below, shows a system/protocol where
a quantum fan-out operation is highlighted by constructing a fan-out gate using ladders of
CNOT gates(parallel) in a constant depth( 1 layer of operation shown), using a dynamic
quantum circuit(see figure 1, steps a thru c with reversal of process b and c to return the
ancillary qubits); and implementing said
quantum fan-out operation by said fan-out gate using ancilla qubits(see figure highlights by
examiner) and feed-forward(“broadcast”)
operations.
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Re claims 16: fan-out gate is constructed from two ladders(neighboring one step ladders)
of CNOT gates(one step ladders shown).
The reference to Guo et al does not explicitly show
a processor connected to said memory, with processor configured to execute
program instructions of the computer program, however, this is conventional in the art, as will
be highlighted by Chen et al for a quantum circuit.
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As shown by Chen et al, the processor and memory allow for the quantum circuit algorithm
components such as the protocol, as noted by Guo et al, to be processed and to interact with
memory as the various data qubits and ancilla qubits are manipulated and kept track of in the
sequence of gate operations.
In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the protocol/method steps of Guo et al, maybe part of a complete quantum circuit system with processor and memory, as shown by Chen et al, to allow for the algorithm to proceed and allow for the appropriate measurements to be carried out.
Allowable Subject Matter
Claims 3-7, 10-14 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ARNOLD M. KINKEAD
Primary Examiner
Art Unit 2849
/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2849