Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Interpretation
The following interpretations are applied in the rejections below.
The term “viewing angle control line” is interpreted as a line that carries a control signal to a transistor of the pixel circuit that switches a light emitting element on and off [e.g., Instant Specification Paragraph 64: a gate of the first viewing angle control transistor Tvc1 can be connected to a first viewing angle control line VCL1; Instant Specification Paragraph 287: a first viewing angle control signal VCS1 having a high level, as illustrated in FIG. 13, can be supplied to gates of the first viewing angle control transistors Tvc1 of the subpixels SP provided in the first light emitting area EAI; Fig. 2: Tvc1, Tvc2, VCL1, VCL2; Fig. 13: VCS1, VCS2]. An emission control line that switches the light emitting element of a pixel on and off is such a line; so is a selection control line that switches on and off one of two light emitting elements of a pixel that differ in viewing angle.
The recitation “a gate driver provided between the viewing angle control line unit and the gate control line unit” is interpreted as a gate driver whose transistors are provided in the viewing angle control line unit and in the gate control line unit [e.g., Instant Specification Paragraph 340: The gate control lines GCL can be connected to the gate driver 200 provided in the viewing angle control line unit VCLU and the gate control line unit GCLU; Instant Specification Paragraph 341: transistors and capacitors configuring the gate driver 200 can be distributed and provided in the viewing angle control line unit VCLU and the gate control line unit GCLU; Fig. 18: BC, SBCn in the VCLU and the GCLUs].
The recitation of claim 7, “successive unit pixel driving circuits along the at least one viewing angle control line,” is interpreted as including the first unit pixel driving circuit on one side of the line and the second unit pixel driving circuit on the other side of the line [e.g., Instant Specification Paragraph 367: at least one viewing angle control line VCL can be connected to adjacent unit pixel driving circuits UPDC along at least one viewing angle control line VCL; Instant Specification Paragraph 368: only the first unit pixel driving circuit UPDC provided on the left side of the viewing angle control line VCL and the second unit pixel driving circuit UPDC provided on the right side of the viewing angle control line VCL are connected to the viewing angle control line VCL; Fig. 14: UPDC1, VCLU, UPDC2].
The term “scan line,” as used in claims 14-16 and 19, is interpreted as a line that supplies a gate signal to a transistor of a pixel circuit.
The terms “reference driver” and “reference transistors” of claim 18 are interpreted as a driver that supplies a control signal to transistors that apply a reference (initialization) voltage within the pixel circuit [e.g., Instant Specification Paragraph 59: The first reference transistor Tsw2a and the second reference transistor Tsw2b can be provided for measuring a threshold voltage of the driving transistor Tdr or mobility, or supplying a reference voltage VREF to the subpixel driving circuit SPDC; Fig. 2: Tsw2a, Tsw2b, RCL, VREF].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, due to the claimed subject matter: “the scan signal applied to a switching transistor of the first unit pixel driving circuit and the second unit pixel driving circuit.”
It is unclear whether the claim requires a single switching transistor that belongs to both the first unit pixel driving circuit and the second unit pixel driving circuit, or a switching transistor in each of the first unit pixel driving circuit and the second unit pixel driving circuit.
The limitation is amenable to both constructions: the clause recites one switching transistor and then two unit pixel driving circuits of which it is a transistor, and nothing in the claim selects between a transistor shared by the two circuits and a transistor in each of them.
The Board of Patent Appeals and Interferences has held that “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. § 112, second paragraph, as indefinite.” Ex parte Miyazaki, 89 USPQ2d 1207 (Bd. Pat. App. & Inter. 2008) (precedential); see MPEP 2173.02, subsection I, and MPEP 2173.05(b), subsection II.
It would be unclear to one having ordinary skill in the art what the metes, bounds, scope, and meaning of the above limitation are intended to be.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, due to the claimed subject matter: “an nth scan stage connected to the nth scan line” (claim 14) and “a scan stage generating a scan signal transmitted along the nth scan line” (claim 1).
Claim 1 recites “a scan stage generating a scan signal transmitted along the nth scan line.” Claim 14 then recites “an nth scan stage connected to the nth scan line.”
It is unclear whether the nth scan stage of claim 14 is the scan stage of claim 1 or a different scan stage.
Likewise, claim 14 recites a scan driver connected to switching transistors provided in unit pixel driving circuits, and it is unclear whether those switching transistors include the switching transistor recited in claim 1.
Each recitation is amenable to two plausible constructions, the same element as recited in claim 1 or a further element, and the claim does not select between them. Miyazaki, 89 USPQ2d 1207; MPEP 2173.02, subsection I.
It would be unclear to one having ordinary skill in the art what the metes, bounds, scope,
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and meaning of the above limitations are intended to be.
Claims 2-13 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being dependent upon rejected base claim 1, and claims 15-20 are further rejected as being dependent upon rejected base claim 14.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 and 14-20
Claims 1-10 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US 2017/0345373 A1) in view of Kim Tae-Jin (US 2017/0053597 A1) and Shikina et al (US 2011/0284881 A1).
Claim 1
Regarding claim 1, Kang discloses a light emitting display apparatus comprising:
a viewing angle control line unit [e.g., Paragraph 55: the gate driver 110A is split and disposed between the pixel circuits PX; Paragraph 51: The sub-blocks may receive a clock signal from at least one vertical clock line extending in the second direction and may receive a gate voltage from at least one voltage line extending in the second direction; Fig. 4: the strip of sub-block SB1-1, with vertical voltage lines VL1 and VL2, between the pixel circuit PX to its left and the pixel circuit PX to its right; Fig. 3: SB1-1 between two PX in the row of stage 110-1]
the viewing angle control line unit between
a first unit pixel driving circuit [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third subblock SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Fig. 3: the PX to the left of SB1-1 in the row of stage 110-1] and
a second unit pixel driving circuit [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third subblock SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Fig. 4: the PX between SB1-1 and SB1-2] provided along a nth (n is a non-zero natural number) scan line, [e.g., Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through… to the gate lines GL1 through GLn extending in the first direction D1; Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Fig. 2: 110-1, G1; Fig. 13: GW1]
the viewing angle control line unit comprising at least a first transistor of a scan stage, [e.g., Paragraph 60: The first sub-block SB1-1 may maintain the voltage of the second node N2 as the first logic level in response to the first clock signal. In one example embodiment, the first sub-block SB1-1 may include a holding transistor TR5 and a first capacitor C1. The holding transistor TR5 may include a gate electrode receiving the first clock signal, a first electrode receiving a first gate voltage VGL from a first vertical voltage line VL1, and a second electrode connected to the second node N2; Paragraph 49: each of stages 110-1 through 110-n in the gate driver 110A may be divided into a plurality of subblocks. At least one pixel circuit PX may be located between two adjacent sub-blocks. Therefore, split stages 110-1 through 110-n of the gate driver 110A may be inserted in a portion of the display region DR; Fig. 4: TR5 in SB1-1]
the scan stage generating a scan signal transmitted along the nth scan line, [e.g., Paragraph 59: the fifth sub-block SB1-5 may include a first output transistor TR8, a second capacitor C2, and a second output transistor TR7. The first output transistor TR8 may include a gate electrode connected to the third node N3, a first electrode receiving a second clock signal, and a second electrode connected to a first output terminal to which the gate signal G1 is outputted; Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through to the gate lines GL1 through GLn extending in the first direction D1; Fig. 2: 110-1, G1; Fig. 4: G1 at SB1-5]
the scan signal applied to a switching transistor of the first unit pixel driving circuit and the second unit pixel driving circuit; and [e.g., Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 41: The pixel circuit PX may receive a data signal from the data driver 150 via data lines and may receive a gate signal from the gate driver 110 via gate lines; Fig. 13: M2, GW1]
a gate control line unit including gate control lines [e.g., Paragraph 52: each of the stages 110-1 through 110-n may receive a first gate clock signal GCK1 from a first vertical clock line CL1 and a third vertical clock line CL3 that extend in the second direction; Paragraph 56: odd-number stages may receive the first gate clock signal GCK1 as the first clock signal via the first and third clock lines CL1 and CL3 and may receive the second gate clock signal GCK2 as the second clock signal via the second and fourth clock lines CL2 and CL4; Paragraph 51: The sub-blocks may receive a clock signal from at least one vertical clock line extending in the second direction and may receive a gate voltage from at least one voltage line extending in the second direction; Fig. 4: the strip of sub-block SB1-2, with vertical clock lines CL1 and CL2, between the pixel circuit PX to its left and the pixel circuit PX to its right] provided between a kth (k is a non-zero natural number) unit pixel driving circuit and a k+1th unit pixel driving circuit provided along the nth scan line, [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Fig. 4: the PX on either side of SB1-2]
wherein at least one unit pixel driving circuit is between the viewing angle control line unit and the gate control line unit, [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth subblock SB1-5, respectively; Fig. 4: the PX between SB1-1 and SB1-2; Fig. 3]
the gate control lines are connected to a gate driver [e.g., Paragraph 61: The second stabilizing transistor TR3 may include a gate electrode receiving the second clock signal, a first electrode connected to the second electrode of the first stabilizing transistor TR2, and a second electrode connected to the first node N1; Paragraph 61: The second sub-block SB1-2 may stabilize the gate signal G1 in response to the voltage of the second node N2 and a second clock signal. In one example embodiment, the second sub-block SB1-2 may include a first stabilizing transistor TR2 and a second stabilizing transistor TR3. The first stabilizing transistor TR2 may include a gate electrode connected to the second node N2, a first electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Paragraph 57: the third sub-block SB1-3 may include a first input transistor TRI and a second input transistor TR4. The first input transistor TRI may include a gate electrode receiving the first clock signal, a first electrode receiving the input signal, and a second electrode connected to the first node N1; Paragraph 43: The gate driver 110 may include a plurality of stages outputting the gate signal to the plurality of gate lines, respectively, to provide the gate signal to the pixel circuits PX; Fig. 4: CL1, CL2, VL2 into TR2, TR3 and TRI of stage 110-1]
provided between the viewing angle control line unit and the gate control line unit. [e.g., Paragraph 49: each of stages 110-1 through 110-n in the gate driver 110A may be divided into a plurality of sub-blocks. At least one pixel circuit PX may be located between two adjacent sub-blocks. Therefore, split stages 110-1 through 110-n of the gate driver 110A may be inserted in a portion of the display region DR; Paragraph 55: the gate driver 110A is split and disposed between the pixel circuits PX; Paragraph 60: The first sub-block SB1-1 may maintain the voltage of the second node N2 as the first logic level in response to the first clock signal. In one example embodiment, the first sub-block SB1-1 may include a holding transistor TR5 and a first capacitor C1. The holding transistor TR5 may include a gate electrode receiving the first clock signal, a first electrode receiving a first gate voltage VGL from a first vertical voltage line VL1, and a second electrode connected to the second node N2; Paragraph 61: The second sub-block SB1-2 may stabilize the gate signal G1 in response to the voltage of the second node N2 and a second clock signal. In one example embodiment, the second sub-block SB1-2 may include a first stabilizing transistor TR2 and a second stabilizing transistor TR3. The first stabilizing transistor TR2 may include a gate electrode connected to the second node N2, a first electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Fig. 4: stage 110-1, with TR5 in SB1-1 and TR2 and TR3 in SB1-2] (e.g., see Paragraphs 40-63)
Kang does not expressly disclose the at least one viewing angle control line included in the viewing angle control line unit, or that the at least one viewing angle control line is connected to the first unit pixel driving circuit and the second unit pixel driving circuit.
Kang’s strips between the pixel circuits carry the vertical clock lines and voltage lines of the split stages [e.g., Paragraph 51: The sub-blocks may receive a clock signal from at least one vertical clock line extending in the second direction and may receive a gate voltage from at least one voltage line extending in the second direction; Paragraph 55: each sub-block may include a number of transistors not exceeding 2 and a number of vertical lines (e.g., vertical voltage line, vertical clock line, etc) not exceeding 2; Fig. 4: VL1, VL2, CL1, CL2, VL3, CL3, CL4, VL4];
the emission control line of Kang’s pixel circuits runs along the pixel row [e.g., Paragraph 100: the first pixel circuit PX1 in the first pixel row and the second pixel circuit PX2 in the second pixel row may share an emission control line and a second initialization control line as the gate line; Paragraph 108: The fifth transistor M5 in the first pixel circuit PX1 may include a gate electrode connected to the emission control line EM2 corresponding to the second pixel row; Fig. 13: EM2].
However, Kim Tae-Jin discloses a display panel in which the row-direction emission control lines are fed through vertical emission control lines that run between the pixel columns [e.g., Paragraph 26: The display panel 110 includes data lines D1 through Dm, horizontal lines, vertical lines, pixels P11 through Pnm, and contact holes CNT1 through CNTn. The horizontal lines may include horizontal scan lines SH1 through SHn and horizontal emission control lines EH1 through EHn. The vertical lines may include vertical scan lines SV1 through SVm and vertical emission control lines E1 through Em; Paragraph 27: The vertical scan lines SV1 through SVm may extend in the first direction. The horizontal scan lines SH1 through SHn may extend in a second direction; Fig. 1: E1 through Em, EH1 through EHn],
each vertical emission control line being connected through a contact hole to one horizontal emission control line [e.g., Paragraph 30: The emission control line contact holes may electrically connect the horizontal emission control lines EH1 through EHn with the vertical emission control lines E1 through Em, respectively. For example, a first emission control line contact hole may electrically connect a first horizontal emission control line EH1 with a first vertical emission control line E1; Paragraph 29: The contact holes CNT1 through CNTn may electrically connect the horizontal lines to the vertical lines, respectively; Paragraph 46: The configuration of the vertical emission control lines may be substantially the same as or similar to a configuration of the vertical scan lines SV1 through SVn],
so that the vertical line between two pixels of a row is connected, through the horizontal line, to the pixel on each side of it [e.g., Paragraph 28: The pixels P11 through Pnm may be located at intersections of the data lines D1 through Dm and the horizontal lines; Paragraph 25: it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween; Fig. 1: P21 and P22 on either side of E2, each connected to EH2];
the emission control signals are supplied on the vertical emission control lines by an emission control driver 122 in the display driving integrated circuit 120 [e.g., Paragraph 35: The emission control driver 122 generates the emission control signals based on an emission driving control signal. The emission control signals are input into the display panel 110 through the vertical emission control lines E1 through Em; Paragraph 33: The display driving integrated circuit 120 may generate scan signals, emission control signals, and data signals for input into the display panel 110. The display driving integrated circuit 120 may include a scan driver 121, an emission control driver 122, and a data driver 123; Fig. 1: 120, 122],
the integrated circuit being arranged at one side of the display panel [e.g., Paragraph 45: The display driving integrated circuit 120 may be arranged in a first direction side of the display panel 210].
Under the interpretation stated above, Kim Tae-Jin’s vertical emission control line is a viewing angle control line, and the strip in which it runs between two pixels of the row is a viewing angle control line unit including that line.
Kang and Kim Tae-Jin are analogous art, because they are from the shared inventive field of light emitting displays, and each is directed to where the lines and driving circuits of an organic light emitting display panel are placed relative to its pixels.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to feed the emission control lines of Kang’s pixel circuits through vertical emission control lines of the kind Kim Tae-Jin discloses,
each running in one of the strips between the pixel circuits in which Kang already runs vertical lines and each contacting the emission control line of a pixel row.
Kang’s pixel circuits require an emission control line for each pair of pixel rows [e.g., Kang, Paragraph 100: the first pixel circuit PX1 in the first pixel row and the second pixel circuit PX2 in the second pixel row may share an emission control line and a second initialization control line as the gate line; Paragraph 108: The fifth transistor M5 in the first pixel circuit PX1 may include a gate electrode connected to the emission control line EM2 corresponding to the second pixel row], and the embodiment of Figs. 2 through 5 does not state how those lines are fed;
Kim Tae-Jin shows a known way of feeding each row’s emission control line, from a driver arranged at one side of the panel, through a vertical line between the pixel columns and a contact hole [e.g., Kim Tae-Jin, Paragraph 30: The emission control line contact holes may electrically connect the horizontal emission control lines EH1 through EHn with the vertical emission control lines E1 through Em, respectively. For example, a first emission control line contact hole may electrically connect a first horizontal emission control line EH1 with a first vertical emission control line E1; Paragraph 35: The emission control driver 122 generates the emission control signals based on an emission driving control signal. The emission control signals are input into the display panel 110 through the vertical emission control lines E1 through Em; Paragraph 33: The display driving integrated circuit 120 may generate scan signals, emission control signals, and data signals for input into the display panel 110. The display driving integrated circuit 120 may include a scan driver 121, an emission control driver 122, and a data driver 123; Paragraph 45: The display driving integrated circuit 120 may be arranged in a first direction side of the display panel 210].
Applying that known technique to Kang’s display supplies the emission control signals from the side of the panel on which Kang already places its data driver [e.g., Kang, Paragraph 40: A plurality of pixels PX and a gate driver 110 may be located in the display region DR], without an emission control driver in the display region or in the left and right non-display regions, with predictable results.
Kim Tae-Jin adopts the arrangement and compensates its side effect [e.g., Kim Tae-Jin, Paragraph 74: a display device in a smart watch includes a scan driver at a lower side of a display panel and auxiliary lines (vertical scan lines) for connecting scan lines that extend in a horizontal direction with the scan driver. In this case, a stain phenomenon may occur near connection points that electrically connect the scan line to the auxiliary lines; Paragraph 42: the display device 100 may store the location information of the contact holes CNT1 through CNTn that electrically connect the horizontal lines to the vertical lines. The input data may be compensated based on the location information of the contact holes CNT1 through CNTn. Therefore, the display device 100 may prevent a stain phenomenon from occurring due to the contact holes CNT1 through CNTn]; a side effect the reference itself corrects does not discourage the arrangement.
Kang states the number of vertical lines as an example of the small size of its sub-blocks [e.g., Kang, Paragraph 55: each sub-block may include a number of transistors not exceeding 2 and a number of vertical lines (e.g., vertical voltage line, vertical clock line, etc) not exceeding 2]: the count is of the vertical lines a subblock itself includes, it is given in example form, and a vertical line that runs in the strip
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alongside a sub-block is not a line the sub-block includes. Where the vertical lines of the combination run is a matter of layout within the ordinary skill.
That gate-driver stages split into transistor groups between adjacent pixels of a horizontal line, with gate control lines extending in the column direction between the pixels, was itself known in the art is evidenced by Kim Yong-Il et al (US 2021/0202906 A1) [e.g., Kim Yong-Il, Paragraph 103: The first substrate 100 may further include a gate driving circuit 150 which is disposed in the display area AA; Paragraph 106: The plurality of branch circuits 151l to 151n may include at least one TFT (or a branch TFT) and may be disposed between two adjacent pixels P (or pixel areas PA) within one horizontal line along the first direction X;
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Paragraph 182: The lines of the gate control line group GCL may extend long in the second direction Y and may be disposed apart from one another by a predetermined interval in the display area AA of the first substrate 100 in the first direction X; Paragraph 108: The gate control line group GCL according to an embodiment may include a start signal line, a plurality of shift clock lines, at least one gate driving power line, and at least one gate common power line; Fig. 6: 150, 1511 to 151n, GCL], cited as evidence of the state of the art (MPEP 2144.03);
Kang alone supplies that arrangement in this rejection.
Moreover, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because all the claimed elements were known in the prior art and one skilled in the art could have combined Kim Tae-Jin’s vertical emission control lines with Kang’s display device as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. See KSR International co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
To the extent the term viewing angle control line is read as requiring a line whose control signal selects the viewing angle of the light output from the pixel, Kang and Kim Tae-Jin do not expressly disclose such a line:
Kang’s pixel circuit drives one organic light emitting diode [e.g., Kang, Paragraph 101: the first pixel circuit PX1 may include an organic light emitting diode (OLED), a plurality of transistors, and a capacitor CST], and
Kim Tae-Jin describes its pixel circuits only by transistor count [e.g., Kim Tae-Jin, Paragraph 28: Each of the pixels P11 through Pnm includes a pixel circuit which has, for example, a 6TIC structure, a 7TIC structure, or another structure]; neither discloses two light emitting units of different viewing angle in a pixel, or a line that selects between them.
However, Shikina discloses a display apparatus in which each pixel has two organic EL elements of the same color with different viewing angle characteristics, an element A (26) with a wide viewing angle characteristic and an element B (27) with a narrow viewing angle characteristic and high front luminance [e.g., Paragraph 35: Each pixel of this display apparatus has two regions that are the same in color but have different viewing angle characteristics (a viewing angle characteristic A and a viewing angle characteristic B); Paragraph 56: the R-1 region 311 has a wide viewing angle characteristic as its optical characteristic; Paragraph 57: although the R-2 region 312 has a narrow viewing angle characteristic, it has an optical characteristic which provides high front luminance, i.e., high light extraction efficiency; Paragraph 76: the organic EL panel 11 of the present embodiment includes the organic EL elements A (26) each being flat on the light emitting side (i.e., on the side opposite the substrate with respect to the organic EL layer), and the organic EL elements B (27) each having a microlens on the light emitting side; Paragraph 74; Fig. 6: 26, 27],
each element having its own switch element, M3 for element A and M4 for element B, and its own selection control line, P2 for element A and P3 for element B [e.g., Paragraph 73: PI denotes a scanning signal line, P2 denotes a selection control line for the organic EL element A (26), and P3 denotes a selection control line for the
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organic EL element B (27); Paragraph 73: The anode electrode of the organic EL element A (26) is connected to the drain electrode of a TFT (M3) which is a first switch element on the substrate; Paragraph 73: the anode electrode of the organic EL element B (27) is connected to the drain electrode of a TFT (M4) which is a second switch element on the substrate; Paragraph 73: M3 and M4 constitute a switching circuit 60 for switching on and off the organic EL element A (26) and the organic EL element B (27) independently; Fig. 6: P2, M3, 26; P3, M4, 27];
the panel has a selection-control-line driving circuit 54 and selection control lines 57 and 58 connected to the two light emitting regions of each pixel, the two lines of a row running along the row through each of its pixel circuits 53 [e.g., Paragraph 69: a selection-control-line driving circuit 54 for selecting two light emitting regions within each pixel, and selection control lines 57 and 58 connected to respective two light emitting regions within each pixel; Paragraph 70: Each of the pixel circuits 53 includes organic EL elements of any one of the colors R, G, and B; Fig. 5: 54, 57, 58, 53];
by switching the levels of P2 and P3 the two elements are controlled independently [e.g., Paragraph 99: By switching between High and Low levels of P2 and P3, the organic EL element A (26) and the organic EL element B (27) can be controlled independently],
so that the panel provides a wide viewing angle characteristic when the first regions alone are turned on and a narrow viewing angle characteristic with high front light extraction efficiency when the second regions alone are turned on [e.g., Paragraph 63: if the R-1 region 311, the G-1 region 321, and the B-l region 331 only are turned on, the organic EL panel 11 can provide a wide viewing angle characteristic; Paragraph 64: If the R-2 region 312, the G-2 region 322, and the B-2 region 332 only are turned on, the organic EL panel 11 exhibits a narrow viewing angle characteristic, but can achieve high efficiency in extracting light to the front; Paragraph 172: capable of switching between a mode having high front luminance (light extraction efficiency) and a mode having a wide viewing angle characteristic].
Shikina’s selection control lines P2 and P3 are lines whose control signals select the viewing angle of the light output from the pixel; each is a viewing angle control line under the interpretation stated above and under the narrower reading alike, and each is connected to every pixel circuit of its row.
Kang, Kim Tae-Jin and Shikina are analogous art, because they are from the shared inventive field of light emitting displays, and Shikina is directed to the pixel circuit and control lines of an organic light emitting display whose viewing angle is switched.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide each pixel circuit of the
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combination of Kang and Kim Tae-Jin with Shikina’s two organic EL elements and two switch elements M3 and M4, and to route Shikina’s two selection control lines in the same manner as Kim Tae-Jin routes the emission control line as vertical lines in the strip between the pixel circuits in which Kang runs the vertical lines of its sub-block, each
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vertical line contacting the row’s selection control line –
so that the display can be
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switched between a wide viewing angle mode and a high front luminance, narrow viewing angle mode [e.g., Shikina, Paragraph 172: capable of switching between a mode having high front luminance (light extraction efficiency) and a mode having a wide viewing angle characteristic; Paragraph 7: the technique does not allow the user to select a front luminance (light extraction efficiency) priority mode or a wide viewing angle priority mode, depending on the situation; Paragraph 63: if the R-1 region 311, the G-1 region 321, and the B-l region 331 only are turned on, the organic EL panel 11 can provide a wide viewing angle characteristic; Paragraph 64: If the R-2 region 312, the G-2 region 322, and the B-2 region 332 only are turned on, the organic EL panel 11 exhibits a narrow viewing angle characteristic, but can achieve high efficiency in extracting light to the front],
with each pixel’s two elements selected independently through their own switch elements and lines [e.g., Shikina, Paragraph 73: M3 and M4 constitute a switching circuit 60 for switching on and off the organic EL element A (26) and the organic EL element B (27) independently; Paragraph 99: By switching between High and Low levels of P2 and P3, the organic EL element A (26) and the organic EL element B (27) can be controlled independently], and
with the selection control lines reaching the pixels of a row from the one side of the panel on which Kim Tae-Jin places its drivers [e.g., Kim Tae-Jin, Paragraph 45: The display driving integrated circuit 120 may be arranged in a first direction side of the display panel 210; Paragraph 33: The display driving integrated circuit 120 may generate scan signals, emission control signals, and data signals for input into the display panel 110. The display driving integrated circuit 120 may include a scan driver 121, an emission control driver 122, and a data driver 123];
the two selection control lines are fed by two further vertical lines and, as stated above, where the vertical lines of the combination run is a matter of layout within the ordinary skill. In the combination, the vertical selection control line running in the strip of sub-block SB1-1 is a viewing angle control line included in the viewing angle control line unit, and it is connected, through the row’s selection control line, to the pixel circuit on each side of the strip, the first unit pixel driving circuit and the second unit pixel driving circuit.
Moreover, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because all the claimed elements were known in the prior art and one skilled in the art could have combined Shikina’s two-element pixel circuit and selection control lines with the display device of Kang and Kim Tae-Jin as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. See KSR International co. v. Teleflex Inc., 550 U.S. 398 (2007);
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Graham v. John Deere Co., 383 U.S. 1 (1966).
Claim 2
Regarding claim 2, Kang discloses wherein the gate control lines are connected to a control driver that generates a gate control signal supplied to the gate control lines, [e.g., Kang, Paragraph 45: the display device 100 may further include a timing controller providing driving control signals to the data driver 150 and the gate driver 110; Paragraph 52: each of the stages 110-1 through 110-n may receive a first gate clock signal GCK1 from a first vertical clock line CL1 and a third vertical clock line CL3 that extend in the second direction; Fig. 4: GCK1 and GCK2 on CL1 and CL2]
The gate clock signals GCK1 and GCK2 carried on Kang’s vertical clock lines are driving control signals of the gate driver, which Kang’s timing controller provides [e.g., Kang, Paragraph 45: the display device 100 may further include a timing controller providing driving control signals to the data driver 150 and the gate driver 110; Paragraph 52: each of the stages 110-1 through 110-n may receive a first gate clock signal GCK1 from a first vertical clock line CL1 and a third vertical clock line CL3 that extend in the second direction].
Kim Tae-Jin further discloses the at least one viewing angle control line is connected to the control driver. [e.g., Kim Tae-Jin, Paragraph 38: The timing controller 140 may generate the scan driving control signal, the emission driving control signal, and the data driving control signal; Paragraph 34: The scan driving control signal may include, for example, a start pulse and clock signals; Paragraph 40: the timing controller 140 may be in, for example, display driving integrated circuit 120; Paragraph 33: The display driving integrated circuit 120 may generate scan signals, emission control signals, and data signals for input into the display panel 110. The display driving integrated circuit 120 may include a scan driver 121, an emission control driver 122, and a data driver 123; Paragraph 35: The emission control driver 122 generates the emission control signals based on an emission driving control signal. The emission control signals are input into the display panel 110 through the vertical emission control lines E1 through Em; Fig. 1: 120, 122, 140, E1 through Em]:
the display driving integrated circuit 120, with the timing controller 140 within it [e.g., Kim Tae-Jin, Paragraph 40: the timing controller 140 may be in, for example, display driving integrated circuit 120],
generates the scan driving control signal comprising the start pulse and clock signals [e.g., Kim Tae-Jin, Paragraph 34: The scan driving control signal may include, for example, a start pulse and clock signals; Paragraph 38: The timing controller 140 may generate the scan driving control signal, the emission driving control signal, and the data driving control signal] and
supplies the emission control signals to the vertical emission control lines from its emission control driver 122 [e.g., Kim Tae-Jin, Paragraph 35: The emission control driver 122 generates the emission control signals based on an emission driving control signal. The emission control signals are input into the display panel 110 through the vertical emission control lines E1 through Em].
In the combination the control driver is that integrated circuit: it generates the clock signals supplied on Kang’s vertical clock lines and it drives the vertical emission control lines, a connection being direct or through intervening elements under Kim Tae-Jin’s own usage [e.g., Kim Tae-Jin, Paragraph 25: it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween].
Where the viewing angle control line is the vertical selection control line of Shikina, that line is driven by Shikina’s selection-control-line driving circuit 54 [e.g., Shikina, Paragraph 69: a selection-control-line driving circuit 54 for selecting two light emitting regions within each pixel, and selection control lines 57 and 58 connected to respective two light emitting regions within each pixel; Fig. 5: 54];
Kim Tae-Jin places the scan driver, the emission control driver and the data driver in one display driving integrated circuit at the side of the panel, in which the timing controller may also be placed [e.g., Kim Tae-Jin, Paragraph 33: The display driving integrated circuit 120 may generate scan signals, emission control signals, and data signals for input into the display panel 110. The display driving integrated circuit 120 may include a scan driver 121, an emission control driver 122, and a data driver 123; Paragraph 45: The display driving integrated circuit 120 may be arranged in a first direction side of the display panel 210; Paragraph 40: the timing controller 140 may be in, for example, display driving integrated circuit 120], and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to place the selection-control-line driving circuit in that integrated circuit as well, so that every control signal of the panel, the clock signals of the gate driver and the selection signals included, is generated by the one integrated circuit at the one side of the panel from which the vertical lines are fed, with predictable results; the integrated circuit is then the control driver to which both the gate control lines and the viewing angle control line are connected. The same reasons to combine apply.
Claim 3
Regarding claim 3, Kang discloses wherein while one unit pixel driving circuit is between the viewing angle control line unit and the gate control line unit, [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth subblock SB1-5, respectively; Fig. 4: the single PX between SB1-1 and SB1-2]
the kth unit pixel driving circuit is the second unit pixel driving circuit [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third subblock SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Fig. 4: the PX between SB1-1 and SB1-2 is the second unit pixel driving circuit and the kth unit pixel driving circuit] and
the k+1th unit pixel driving circuit is a third unit pixel driving circuit. [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third subblock SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Fig. 4: the PX between SB1-2 and SB1-3] (e.g., see Paragraphs 49-61)
Claim 4
Kang and Kim Tae-Jin do not expressly disclose that each of the first unit pixel driving circuit and the second unit pixel driving circuit includes at least three subpixel driving circuits each including a first viewing angle control transistor connected to a first viewing angle control line and a second viewing angle control transistor connected to a second viewing angle control line provided in the viewing angle control line unit:
Kang’s pixel circuit drives one organic light emitting diode [e.g., Kang, Paragraph 101: the first pixel circuit PX1 may include an organic light emitting diode (OLED), a plurality of transistors, and a capacitor CST], and
Kim Tae-Jin describes its pixel circuits only by transistor count [e.g., Kim Tae-Jin, Paragraph 28: Each of the pixels P11 through Pnm includes a pixel circuit which has, for example, a 6TIC structure, a 7TIC structure, or another structure];
neither discloses two light emitting units per subpixel, or two control lines selecting between them.
However, Shikina discloses wherein each of the first unit pixel driving circuit and the second unit pixel driving circuit includes at least three subpixel driving circuits, [e.g., Paragraph 46: The organic EL panel 11 of the present embodiment has pixels of three different colors, R, G, and B; Paragraph 70: Each of the pixel circuits 53 includes organic EL elements of any one of the colors R, G, and B; Fig. 7: 71, 72, 73; Fig. 5: 53]
each of the at least three subpixel driving circuits including: [e.g., Paragraph 73: M3 and M4 constitute a switching circuit 60 for switching on and off the organic EL element A (26) and the organic EL element B (27) independently; Paragraph 36: An organic EL element A (26) and an organic EL element B (27) in the respective regions can be independently turned on or off]
a first viewing angle control transistor connected to a first viewing angle control line [e.g., Paragraph 73: PI denotes a scanning signal line, P2 denotes a selection control line for the organic EL element A (26), and P3 denotes a selection control line for the organic EL element B (27); Paragraph 73: The anode electrode of the organic EL element A (26) is connected to the drain electrode of a TFT (M3) which is a first switch element on the substrate; Paragraph 69: a selection-control-line driving circuit 54 for selecting two light emitting regions within each pixel, and selection control lines 57 and 58 connected to respective two light emitting regions within each pixel; Fig. 6: M3, P2; Fig. 5: 57, 54]
a second viewing angle control transistor connected to a second viewing angle control line [e.g., Paragraph 73: PI denotes a scanning signal line, P2 denotes a selection control line for the organic EL element A (26), and P3 denotes a selection control line for the organic EL element B (27); Paragraph 73: the anode electrode of the organic EL element B (27) is connected to the drain electrode of a TFT (M4) which is a second switch element on the substrate; Paragraph 99: By switching between High and Low levels of P2 and P3, the organic EL element A (26) and the organic EL element B (27) can be controlled independently; Fig. 6: M4, 1)3; Fig. 5: 58]
Shikina’s red, green and blue pixel circuits are separate circuits [e.g., Shikina, Paragraph 70: Each of the pixel circuits 53 includes organic EL elements of any one of the colors R, G, and B]; under the broadest reasonable interpretation three such circuits placed side by side between two of Kang’s strips,
where Kang places at least one pixel circuit [e.g., Kang, Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively], are a unit pixel driving circuit including at least three subpixel driving circuits, the claim reciting no further relation among them.
Shikina’s selection control lines 57 and 58 run along the pixel row from a selection-control-line driving circuit 54 [e.g., Paragraph 69: a selection-control-line driving circuit 54 for selecting two light emitting regions within each pixel, and selection control lines 57 and 58 connected to respective two light emitting regions within each pixel; Fig. 5: 54, 57, 58]
Shikina does not expressly disclose the two selection control lines provided in the viewing angle control line unit, i.e. running in the strip between two pixel circuits of the row. In the combination stated for claim 1, the two selection control lines of each row are fed through vertical lines in the strip between the pixel circuits, so that each is provided in the viewing angle control line unit, and each subpixel circuit of the combination carries Shikina’s two switch elements and two selection control lines. The same reasons to combine apply.
Claim 5
Regarding claim 5, Shikina discloses wherein a first viewing angle of light output from a first light emitting unit [e.g., Paragraph 35: Each pixel of this display apparatus has two regions that are the same in color but have different viewing angle characteristics (a viewing angle characteristic A and a viewing angle characteristic B); Paragraph 56: the R-1 region 311 has a wide viewing angle characteristic as its optical characteristic; Fig. 6: 26; Fig. 4: (a)]
that is driven by the first viewing angle control transistor [e.g., Paragraph 95: Since M3 is in a conductive state, a voltage generated in C1 causes current corresponding to the current driving capability of M2 to be supplied to the organic EL element A (26)]
is different from a second viewing angle of light output from a second light emitting unit [e.g., Paragraph 57: although the R-2 region 312 has a narrow viewing angle characteristic, it has an optical characteristic which provides high front luminance, i.e., high light extraction efficiency; Paragraph 76: the organic EL panel 11 of the present embodiment includes the organic EL elements A (26) each being flat on the light emitting side (i.e., on the side opposite the substrate with respect to the organic EL layer), and the organic EL elements B (27) each having a microlens on the light emitting side; Paragraph 86: In the configuration with the microlens 81, as compared to that without the microlens 81, the emission angle is closer to a direction perpendicular to the substrate; Fig. 6: 27; Fig. 8: 81; Fig. 4: (b)]
that is driven by the second viewing angle control transistor. [e.g., Paragraph 96: Since M4 is in a conductive state, a voltage generated in C1 causes current corresponding to the current driving capability of M2 to be supplied only to the organic EL element B (27); Paragraph 99: By switching between High and Low levels of P2 and P3, the organic EL element A (26) and the organic EL element B (27) can be controlled independently] (e.g., see Paragraphs 35-64, 68-100) The same reasons to combine apply.
Claim 6
Regarding claim 6, Shikina discloses wherein the first viewing angle control transistor is connected between the first light emitting unit and a driving transistor [e.g., Paragraph 73: The anode electrode of the organic EL element A (26) is connected to the drain electrode of a TFT (M3) which is a first switch element on the substrate; Paragraph 93: current is output to M3 and M4, through a second electrode of M2 electrically connected to M3 and M4; Fig. 6: M3 between M2 and 26]
that controls a level of a current supplied to the first light emitting unit or the second light emitting unit, [e.g., Paragraph 98: current is controlled by M2 which is controlled in accordance with the information signal corresponding to the a-th row and the b-th column, and current based on the same information signal is supplied to the organic EL element A (26) and the organic EL element B (27) of the pixel in the a-th row and the b-th column; Paragraph 93: a voltage corresponding to the current driving capability of M1 is held by C1 (capacitor) placed between the gate electrode of M2 (current output transistor) and a power supply potential V1; Paragraph 94: A section constituted by M1 (switching element), C1 (capacitor), and M2 (current output transistor) is referred to as a driving unit 59] and
the second viewing angle control transistor is connected between the driving transistor and the second light emitting unit. [e.g., Paragraph 73: the anode electrode of the organic EL element B (27) is connected to the drain electrode of a TFT (M4) which is a second switch element on the substrate; Paragraph 96: Since M4 is in a conductive state, a voltage generated in C1 causes current corresponding to the current driving capability of M2 to be supplied only to the organic EL element B (27); Fig. 6: M4 between M2 and 27]
The same reasons to combine apply.
Claim 7
Regarding claim 7, Kim Tae-Jin discloses wherein the at least one viewing angle control line is connected to successive unit pixel driving circuits along the at least one viewing angle control line. [e.g., Paragraph 30: The emission control line contact holes may electrically connect the horizontal emission control lines EH1 through EHn with the vertical emission control lines E1 through Em, respectively. For example, a first emission control line contact hole may electrically connect a first horizontal emission control line EH1 with a first vertical emission control line E1; Paragraph 28: The pixels P11 through Pnm may be located at intersections of the data lines D1 through Dm and the horizontal lines; Paragraph 25: it can be directly connected or coupled to the another element or be indirectly connected or coupled to the another element with one or more intervening elements interposed therebetween; Fig. 1: the pixel circuits P21 and P22 on either side of the vertical emission control line E2, both connected through the horizontal emission control line EH2]
The same reasons to combine apply. Under the interpretation stated above, the pixels on either side of the vertical emission control line, each connected to it through the horizontal emission control line, are successive unit pixel driving circuits along the line; so are the pixel circuits on either side of the vertical selection control line of the combination, each connected to it through the row’s selection control line [e.g., Shikina, Paragraph 69: a selection-control-line driving circuit 54 for selecting two light emitting regions within each pixel, and selection control lines 57 and 58 connected to respective two light emitting regions within each pixel; Fig. 5: 57, 58, 53].
Claim 8
Regarding claim 8, Kang discloses wherein the viewing angle control line unit further includes at least one auxiliary gate control line connected to the gate driver. [e.g., Paragraph 60: The first sub-block SB1-1 may maintain the voltage of the second node N2 as the first logic level in response to the first clock signal. In one example embodiment, the first sub-block SB1-1 may include a holding transistor TR5 and a first capacitor C1. The holding transistor TR5 may include a gate electrode receiving the first clock signal, a first electrode receiving a first gate voltage VGL from a first vertical voltage line VL1, and a second electrode connected to the second node N2; Paragraph 60: a second electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Paragraph 51: The sub-blocks may receive a clock signal from at least one vertical clock line extending in the second direction and may receive a gate voltage from at least one voltage line extending in the second direction; Paragraph 63: at least one the voltage line may be connected to both of the gate driver 110A and the pixel circuit PX; Fig. 4: the strip of sub-block SB1-1, with vertical voltage lines VL1 and VL2, between the pixel circuit PX to its left and the pixel circuit PX to its right]
Claim 9
Regarding claim 9, Kang discloses wherein the viewing angle control line unit further includes branch circuits connected to the gate control lines. [e.g., Paragraph 60: The first sub-block SB1-1 may maintain the voltage of the second node N2 as the first logic level in response to the first clock signal. In one example embodiment, the first sub-block SB1-1 may include a holding transistor TR5 and a first capacitor C1. The holding transistor TR5 may include a gate electrode receiving the first clock signal, a first electrode receiving a first gate voltage VGL from a first vertical voltage line VL1, and a second electrode connected to the second node N2; Paragraph 56: odd-number stages may receive the first gate clock signal GCK1 as the first clock signal via the first and third clock lines CL1 and CL3 and may receive the second gate clock signal GCK2 as the second clock signal via the second and fourth clock lines CL2 and CL4; Paragraph 60: a second electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Fig. 4: TR5 and C1 in SB1-1; the gate of TR5 receives the first clock signal GCK1 carried by clock line CL1 of the SB1-2 strip]
Claim 10
Regarding claim 10, Kang discloses wherein the gate control line unit further includes branch circuits connected to the gate control lines. [e.g., Paragraph 61: The second sub-block SB1-2 may stabilize the gate signal G1 in response to the voltage of the second node N2 and a second clock signal. In one example embodiment, the second sub-block SB1-2 may include a first stabilizing transistor TR2 and a second stabilizing transistor TR3. The first stabilizing transistor TR2 may include a gate electrode connected to the second node N2, a first electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Paragraph 61: The second stabilizing transistor TR3 may include a gate electrode receiving the second clock signal, a first electrode connected to the second electrode of the first stabilizing transistor TR2, and a second electrode connected to the first node N1; Fig. 4: TR2 and TR3 in SB1-2, connected to VL2 and CL2]
Claim 14
Regarding claim 14, Kang discloses
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wherein the gate driver includes a scan driver connected to switching transistors provided in unit pixel driving circuits, [e.g., Paragraph 43: The gate driver 110 may include a plurality of stages outputting the gate signal to the plurality of gate lines, respectively, to provide the gate signal to the pixel circuits PX; Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA 1
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corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 114: The second transistor M2 in second pixel circuit PX2 may include a gate electrode connected to the gate line GW2 corresponding to the second pixel row; Fig. 13: M2, GW1, GW2; Fig. 2: 110A]
wherein the scan driver includes scan stages, [e.g., Paragraph 50: the gate driver 110A may include first through (n)th stages 110-1 through 110-n; Fig. 2: 110-1 through 110-n] and
among the scan stages, an nth scan stage connected to the nth scan line includes nth scan branch circuits, [e.g., Paragraph 50: the first stage 110-1 may include first through fifth sub-blocks SB1-1 through SB1-5 sequentially arranged in a first direction D1; Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through . . . to the gate lines GL1 through GLn extending in the first direction D1; Fig. 2: 110-1, G1; Fig. 3: SB1-1 through SB1-5]
wherein each of the nth scan branch circuits includes at least one transistor, [e.g., Paragraph 55: each sub-block may include a number of transistors not exceeding 2 and a number of vertical lines (e.g., vertical voltage line, vertical clock line, etc) not exceeding 2; Paragraph 60: The first sub-block SB1-1 may maintain the voltage of the second node N2 as the first logic level in response to the first clock signal. In one example embodiment, the first sub-block SB1-1 may include a holding transistor TR5 and a first capacitor C1. The holding transistor TR5 may include a gate electrode receiving the first clock signal, a first electrode receiving a first gate voltage VGL from a first vertical voltage line VL1, and a second electrode connected to the second node N2; Paragraph 61: The second sub-block SB1-2 may stabilize the gate signal G1 in response to the voltage of the second node N2 and a second clock signal. In one example embodiment, the second subblock SB1-2 may include a first stabilizing transistor TR2 and a second stabilizing transistor TR3. The first stabilizing transistor TR2 may include a gate electrode connected to the second node N2, a first electrode receiving a second gate voltage VGH from a second vertical voltage line VL2; Paragraph 57: the third sub-block SB1-3 may include a first input transistor TRI and a second input transistor TR4. The first input transistor TRI may include a gate electrode receiving the first clock signal, a first electrode receiving the input signal, and a second electrode connected to the first node N1; Paragraph 58: the fourth sub-block SB1-4 may include a reducing transistor TR6 including a gate electrode receiving a first gate voltage VGL from a third voltage line VL3, a first electrode connected to the first node N1, and a second electrode connected to the third node N3; Paragraph 59: the fifth sub-block SB1-5 may include a first output transistor TR8, a second capacitor C2, and a second output transistor TR7. The first output transistor TR8 may include a gate electrode connected to the third node N3, a first electrode receiving a second clock signal, and a second electrode connected to a first output terminal to which the gate signal G1 is outputted; Fig. 4: TR5; TR2, TR3; TRI, TR4; TR6; TR7, TR8]
and each of the nth scan branch circuits is in one of viewing angle control line units and gate control line units along the nth scan line. [e.g., Paragraph 55: the gate driver 110A is split and disposed between the pixel circuits PX; Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively; Paragraph 49: each of stages 110-1 through 110-n in the gate driver 110A may be divided into a plurality of sub-blocks. At least one pixel circuit PX may be located between two adjacent sub-blocks. Therefore, split stages 110-1 through 110-n of the gate driver 110A may be inserted in a portion of the display region DR; Fig. 3: SB1-1 through SB1-5 each between two PX along the row of stage 110-1; Fig. 4]
As to claim 14, the gate signals G1 through Gn that Kang’s stages output to the gate lines [e.g., Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through . . . to the gate lines GL1 through GLn extending in the first direction D1]
are the gate signals of the first and second gate drivers [e.g., Paragraph 79: The first gate driver may include stages GW1-1, GW1-2, etc., that provide the gate signal to odd-number pixel rows. The stages GW1-1, GW1-2, etc., in the first gate driver may be located between the first pixel column and the second pixel column. In addition, each of the stages GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows; Paragraph 84: The second gate driver may include stages that provide the gate signal to even-number pixel rows],
which Kang’s pixel circuits receive on the gate lines GW1 and GW2 at the gates of the switching transistors M2 [e.g., Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 114: The second transistor M2 in second pixel circuit PX2 may include a gate electrode connected to the gate line GW2 corresponding to the second pixel row; Fig. 13: M2, GW1, GW2]; those gate lines are the scan lines of the claims.
In the combination every strip between the pixel circuits carries either the vertical lines that feed the row’s selection control lines and emission control line, routed as stated for claim 1, or the vertical clock and voltage lines of Kang, or both, so that each sub-block of a stage is in one of viewing angle control line units and gate control line units along the gate line of that stage.
Claims 15-20 are addressed on Kang’s further embodiment of Figs. 10 through 13, in which the same split-stage rule applies to each stage of the gate drivers [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each subblock may be interposed between adjacent pixel circuits],
each stage is placed between two pixel columns and corresponds to at least two pixel rows [e.g., Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region], and
the stage circuit of Fig. 12 receives its clock signals and gate voltages from vertical lines in the strip [e.g., Paragraph 88: stages in the first gate driver may receive a clock signal from at least one vertical clock line extending in the second direction D2 and receive a gate voltage from at least one voltage line extending in the second direction D2; Paragraph 90: The first stage GW1-1 in the first gate driver may include an input circuit 131, a load reducing circuit 132, an output circuit 133, a holding circuit 134, and a stabilizing circuit 135].
Claim 15
Regarding claim 15, Kang discloses wherein the nth scan line and at least two scan lines overlap each of the nth scan branch circuits configuring the nth scan stage. [e.g., Paragraph 83: the first sub-blocks GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows. For example, a first stage GW1-1, GWB1-1 in the first gate driver may correspond to a first pixel row including pixel circuits PX11, PX12, and PX13 and a second pixel row including pixel circuits PX21, PX22, and PX23; Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region; Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through . . . to the gate lines GL1 through GLn extending in the first direction D1; Paragraph 100: the first pixel circuit PX1 in the first pixel row and the second pixel circuit PX2 in the second pixel row may share an emission control line and a second initialization control line as the gate line; Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 114: The second transistor M2 in second pixel circuit PX2 may include a gate electrode connected to the gate line GW2 corresponding to the second pixel row; Paragraph 107: The (4-2)th transistor M4-2 in the first pixel circuit PX1 may include a gate electrode connected to the first initialization control line GI1 corresponding to the first pixel row, a first electrode connected to the second electrode of the (4-1)th transistor M4-1, and a second electrode connected to the first node N1; Paragraph 108: The fifth transistor M5 in the first pixel circuit PX1 may include a gate electrode connected to the emission control line EM2 corresponding to the second pixel row; Fig. 11: GW1-1 and GWB1-1 spanning pixel rows 1 and 2; Fig. 13: GW1, GI1, GW2, G12, EM2, GB2]
Kang’s gate lines extend in the first direction across the display region [e.g., Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through . . . to the gate lines GL1 through GLn extending in the first direction D1] and
the sub-blocks of a stage occupy the strip between two pixel columns over two pixel rows [e.g., Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region; Paragraph 83: the first sub-blocks GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows. For example, a first stage GW1-1, GWB1-1 in the first gate driver may correspond to a first pixel row including pixel circuits PX11, PX12, and PX13 and a second pixel row including pixel circuits PX21, PX22, and PX23],
so the gate lines GW1 and GI1 of the first pixel row, GW2 and G12 of the second pixel row and the shared lines EM2 and GB2 [e.g., Paragraph 100: the first pixel circuit PX 1 in the first pixel row and the second pixel circuit PX2 in the second pixel row may share an emission control line and a second initialization control line as the gate line; Paragraph 107: The (4-2)th transistor M4-2 in the first pixel circuit PX1 may include a gate electrode connected to the first initialization control line GI1 corresponding to the first pixel row, a first electrode connected to the second electrode of the (4-1)th transistor M4-1, and a second electrode connected to the first node N1; Paragraph 108: The fifth transistor M5 in the first pixel circuit PX1 may include a gate electrode connected to the emission control line EM2 corresponding to the second pixel row; Fig. 13] cross each sub-block of the first stage.
Under the interpretation stated above each of them is a scan line.
Further, Kang states that a stage corresponds to at least two pixel rows [e.g., Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region];
a stage whose subblocks correspond to three pixel rows, which is within that teaching, is crossed by the gate lines GW1, GW2 and GW3 of those rows, and it would have been obvious to size the subblocks over three rows where the space between the pixel columns so requires, Kang’s stated purpose for the multi-row stage being to secure space for the gate driver in the display region [e.g., Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region].
Claim 16
Regarding claim 16, Kang discloses wherein among the scan stages, a n+1th scan stage connected to a n+1th scan line includes n+1th scan branch circuits, [e.g., Paragraph 84: The second gate driver may include stages that provide the gate signal to even-number pixel rows; Paragraph 84: a first stage GW2-1, GWB2-1 in the second gate driver may correspond to a second pixel row including pixel circuits PX23, PX24, and PX25 and a third pixel row including pixel circuits PX33, PX34, and PX35; Paragraph 114: The second transistor M2 in second pixel circuit PX2 may include a gate electrode connected to the gate line GW2 corresponding to the second pixel row; Fig. 11: GW2-1 and GWB2-1 of the second gate driver; Fig. 13: GW2]
wherein each of the n+1th scan branch circuits includes at least one transistor [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each sub-block may be interposed between adjacent pixel circuits; Paragraph 83: Each stage in the first gate driver may be divided into a plurality of
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sub-blocks, and at least one pixel circuit may be located between two adjacent sub-blocks. For example, the first stage of the first gate driver may include a first sub-block GW1-1 and a second sub-block GWB1-1. Here, the second sub-block GWB1-1 may function as an output buffer to stably output the gate signal] and
each of the n+1th scan branch circuits is in one of viewing angle control line units and gate control line units along the n+1th scan line, and [e.g., Paragraph 84: The first sub-blocks GW2-1, GW2-2, etc., in the second gate driver may be located between the third pixel column and the fourth pixel column; Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each subblock may be interposed between adjacent pixel circuits; Fig. 11: GW2-1 between the third and fourth pixel columns, GWB2-1 between the fourth and fifth]
at least one of at least three scan lines overlapping the nth scan branch circuits is nonoverlapping with the n+1th scan branch circuits. [e.g., Paragraph 83: the first subblocks GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows. For example, a first stage GW1-1, GWB1-1 in the first gate driver may correspond to a first pixel row including pixel circuits PX11, PX12, and PX13 and a second pixel row including pixel circuits PX21, PX22, and PX23; Paragraph 84: a first stage GW2-1, GWB2-1 in the second gate driver may correspond to a second pixel row including pixel circuits PX23, PX24, and PX25 and a third pixel row including pixel circuits PX33, PX34, and PX35; Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 107: The (4-2)th transistor M4-2 in the first pixel circuit PX1 may include a gate electrode connected to the first initialization control line GI1 corresponding to the first pixel row, a first electrode connected to the second electrode of the (4-1)th transistor M4-1, and a second electrode connected to the first node N1; Fig. 11: GW1-1 spans rows 1 and 2, GW2-1 spans rows 2 and 3; Fig. 13: GW1 and GI1 of the first pixel row]
Claim 16 depends from claim 14. The at least three scan lines that overlap the nth scan branch circuits are the gate lines identified for claim 15 above, which cross the sub-blocks of the nth stage; of those, the gate lines of the first pixel row do not overlap the n+1th scan branch circuits, because the first stage of the second gate driver corresponds to the second and third pixel rows [e.g., Paragraph 84: a first stage GW2-1, GWB2-1 in the second gate driver may correspond to a second pixel row including pixel circuits PX23, PX24, and PX25 and a third pixel row including pixel circuits PX33, PX34, and PX35; Fig. 11: GW2-1 and GWB2-1] and lies in a strip between a different pair of pixel columns [e.g., Paragraph 84: The first sub-blocks GW2-1, GW2-2, etc., in the second gate driver may be located between the third pixel column and the fourth pixel column].
Claim 17
Regarding claim 17, Kang discloses wherein another scan stage configuring the scan driver is on a left side or a right side of the nth scan stage along a first direction parallel to the nth scan line, [e.g., Paragraph 83: Each stage in the first gate driver may be divided into a plurality of sub-blocks, and at least one pixel circuit may be located between two adjacent sub-blocks. For example, the first stage of the first gate driver may include a first sub-block GW1-1 and a second subblock GWB1-1. Here, the second sub-block GWB1-1 may function as an output buffer to stably output the gate signal; Paragraph 84: The first sub-blocks GW2-1, GW2-2, etc., in the second gate driver may be located between the third pixel column and the fourth pixel column; Paragraph 22: At least one of the pixel columns may be located between the first gate driver and the second driver; Fig. 11: GW2-1 of the second gate driver to the right of GW1-1 of the first gate driver, and GW1-1 to the left of GW2-1, along the row direction; Fig. 10: GW1-1, GW2-1] and
another scan stage configuring the scan driver is on an upper end or a lower end of the nth scan stage along a second direction that is different from the first direction. [e.g., Paragraph 83: the first sub-blocks GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows. For example, a first stage GW1-1, GWB1-1 in the first gate driver may correspond to a first pixel row including pixel circuits PX11, PX12, and PX13 and a second pixel row including pixel circuits PX21, PX22, and PX23; Fig. 11: GW1-2 at the lower end of GW1-1, and GW1-1 at the upper end of GW1-2; Fig. 10: GW1-1, GW1-2] (e.g., see Paragraphs 76-86)
Claim 18
Regarding claim 18, Kang discloses wherein the gate driver includes a reference driver connected to reference transistors in the unit pixel driving circuits, [e.g., Paragraph 86: the gate driver may further include a third gate driver providing an initialization control signal as a gate signal to the pixel circuits; Paragraph 107: The (4-2)th transistor M4-2 in the first pixel circuit PX1 may include a gate electrode connected to the first initialization control line GI1 corresponding to the first pixel row, a first electrode connected to the second electrode of the (4-1)th transistor M4-1, and a second electrode connected to the first node N1; Paragraph 106: a first electrode connected to the initialization voltage line VINT1 corresponding to the first pixel row; Fig. 13: M4-1, M4-2, GI1, VINT1]
the reference driver including reference stages and among the reference stages, an nth reference stage connected to subpixels connected to the nth scan line includes nth reference branch circuits, [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each sub-block may be interposed between adjacent pixel circuits; Paragraph 43: Each of the stages may be divided
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into a plurality of sub-blocks. At least one pixel circuit PX may be located between two adjacent sub-blocks; Paragraph 86: the gate driver may further include a third gate driver providing an initialization control signal as a gate signal to the pixel circuits; Fig. 11: EM1 and EMB1, the split stage of the emission control driver, as the pattern for each of the gate drivers]
wherein each of the nth reference branch circuits includes at least one transistor, [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each sub-block may be interposed between adjacent pixel circuits; Paragraph 55: each sub-block may include a number of transistors not exceeding 2 and a number of vertical lines (e.g., vertical voltage line, vertical clock line, etc) not exceeding 2] and
each of the nth reference branch circuits is in one of viewing angle control line units and gate control line units along the nth scan line. [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of subblocks, and each sub-block may be interposed between adjacent pixel circuits; Paragraph 85: The first sub-blocks EM1, EM2, etc., in the emission control driver may be located between the fifth pixel column and the sixth pixel column; Paragraph 85: the first subblocks EM1, EM2, etc., in the emission control driver may be disposed corresponding to two pixel rows; Fig. 11: EM1 between the fifth and sixth pixel columns, EMB1 between the sixth and seventh] (e.g., see Paragraphs 76-86, 98-127)
Kang does not expressly disclose the arrangement of the stages of its third gate driver: Kang states the third gate driver, which provides the initialization control signal to the pixel circuits [e.g., Paragraph 86: the gate driver may further include a third gate driver providing an initialization control signal as a gate signal to the pixel circuits], and
states in the alternative that the first gate driver and/or the second gate driver provide that signal [e.g., Paragraph 86: In another example, the first gate driver and/or the second gate driver provide the initialization control signal to the pixel circuits], but illustrates neither.
However, Kang discloses that each stage in the gate drivers is divided into sub-blocks interposed between adjacent pixel circuits [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each sub-block may be interposed between adjacent pixel circuits] and
illustrates that arrangement for the first gate driver, the second gate driver and the emission control driver [e.g., Paragraph 83: Each stage in the first gate driver may be divided into a plurality of sub-blocks, and at least one pixel circuit may be located between two adjacent sub-blocks. For example, the first stage of the first gate driver may include a first sub-block GW1-1 and a second sub-block GWB1-1. Here, the second subblock GWB1-1 may function as an output buffer to stably output the gate signal; Paragraph 84: The first sub-blocks GW2-1, GW2-2, etc., in the second gate driver may be located between the third pixel column and the fourth pixel column; Paragraph 85: The first subblocks EM1, EM2, etc., in the emission control driver may be located between the fifth pixel column and the sixth pixel column; Fig. 11]; and
in Kang’s second alternative the initialization control signal is provided by the first or second gate driver itself, whose stages are so divided [e.g., Paragraph 86: In another example, the first gate driver and/or the second gate driver provide the initialization control signal to the pixel circuits; Paragraph 83: Each stage in the first gate driver may be divided into a plurality of subblocks, and at least one pixel circuit may be located between two adjacent sub-blocks. For example, the first stage of the first gate driver may include a first sub-block GW1-1 and a second sub-block GWB1-1. Here, the second sub-block GWB1-1 may function as an output buffer to stably output the gate signal; Paragraph 84: The first sub-blocks GW2-1, GW2-2, etc., in the second gate driver may be located between the third pixel column and the fourth pixel column],
each stage serving the pixel rows it drives [e.g., Paragraph 83: the first sub-blocks GW1-1, GW1-2, etc., in the first gate driver may be disposed corresponding to two pixel rows. For example, a first stage GW1-1, GWB1-1 in the first gate driver may correspond to a first pixel row including pixel circuits PX11, PX12, and PX13 and a second pixel row including pixel circuits PX21, PX22, and PX23; Paragraph 84: a first stage GW2-1, GWB2-1 in the second gate driver may correspond to a second pixel row including pixel circuits PX23, PX24, and PX25 and a third pixel row including pixel circuits PX33, PX34, and PX35].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the stages of the driver that supplies the initialization control signal to the initialization transistors M4-1 and M4-2 of the pixel circuits [e.g., Paragraph 107: The (4-2)th transistor M4-2 in the first pixel circuit PX1 may include a gate electrode connected to the first initialization control line GI1 corresponding to the first pixel row, a first electrode connected to the second electrode of the (4-1)th transistor M4-1, and a second electrode connected to the first node N1] in the same way as the other gate drivers of the same display, i.e. as sub-blocks in strips between the pixel circuits of the rows they drive,
because Kang states that arrangement as the rule for each stage in the gate drivers [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of sub-blocks, and each subblock may be interposed between adjacent pixel circuits] and applies it to every driver it illustrates, with the predictable result of a driver that occupies no non-display region [e.g., Paragraph 26: the gate driver of the display device is located in an active region or a display region in which pixel circuits are arranged, thereby minimizing the size of the non-display region and decreasing an overall size of the display device]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 19
Regarding claim 19, Kang discloses wherein the nth scan line and at least two scan lines overlap each of the nth reference branch circuits configuring the nth reference stage. [e.g., Paragraph 82: Each stage in the gate drivers or the emission control driver may be divided into a plurality of subblocks, and each sub-block may be interposed between adjacent pixel circuits; Paragraph 85: the first sub-blocks EM1, EM2, etc., in the emission control driver may be disposed corresponding to two pixel rows; Paragraph 77: stages of the gate driver may be located between two adjacent pixel columns, which corresponding to at least two pixel rows, to secure a space in which the gate driver is interposed in the display region; Paragraph 54: The stages 110-1 through 110-n may respectively output the gate signal G1 through… to the gate lines GL1 through GLn extending in the first direction D1; Paragraph 100: the first pixel circuit PX1 in the first pixel row and the second pixel circuit PX2 in the second pixel row may share an emission control line and a second initialization control line as the gate line; Paragraph 103: The second transistor M2 in the first pixel circuit PX1 may include a gate electrode connected to the gate line GW1 corresponding to the first pixel row, a first electrode connected to the data line DATA1 corresponding to the first pixel column, and a second electrode connected to the second node N2; Paragraph 114: The second transistor M2 in second pixel circuit PX2 may include a gate electrode connected to the gate line GW2 corresponding to the second pixel row; Fig. 11: EM1 and EMB1 spanning two pixel rows; Fig. 13: GW1, GI1, GW2, G12, EM2, GB2]
For the reasons given for claims 15 and 18, the sub-blocks of the driver supplying the initialization control signal, arranged like those of the other drivers over two or more pixel rows, are crossed by the gate lines of those rows.
Claim 20
Regarding claim 20, Kang discloses wherein the reference driver is on a left side or a right side of the scan driver along a first direction parallel to the nth scan line. [e.g., Paragraph 78: the display device may include gate drivers (i.e., a first gate driver, a second gate driver) and an emission control driver in the circuit region IRC of the display region. At least one pixel column may be located between the first gate driver and the second gate driver. In addition, at least one pixel column may be located between the second gate driver and the emission control driver; Paragraph 85: The first sub-blocks EM1, EM2, etc., in the emission control driver may be located between the fifth pixel column and the sixth pixel column; Paragraph 86: the gate driver may further include a third gate driver providing an initialization control signal as a gate signal to the pixel circuits; Fig. 10: EM1 to the right of GW1-1 and GW2-1 along the row direction; Fig. 11: EM1, EMB1]
Kang does not expressly disclose where its third gate driver sits.
However, Kang discloses that each of its drivers occupies its own strip between two pixel columns, the emission control driver lying in a strip to the right of the strips of the first and second gate drivers with at least one pixel column between them [e.g., Paragraph 78: the display device may include gate drivers (i.e., a first gate driver, a second gate driver) and an emission control driver in the circuit region IRC of the display region. At least one pixel column may be located between the first gate driver and the second gate driver. In addition, at least one pixel column may be located between the second gate driver and the emission control driver; Paragraph 85: The first sub-blocks EM1, EM2, etc., in the emission control driver may be located between the fifth pixel column and the sixth pixel column; Fig. 10: GW1-1, GW2-1, EM1; Fig. 11: GW1-1, GW2-1, EM1].
For the reasons given for claim 18, it would have been obvious to locate the third gate driver in the same manner, in a further strip beside the strips of the scan driver along the row direction, Kang’s pattern for every driver it places being one strip per driver with pixel columns between [e.g., Paragraph 78: the display device may include gate drivers (i.e., a first gate driver, a second gate driver) and an emission control driver in the circuit region IRC of the display region. At least one pixel column may be located between the first gate driver and the second gate driver. In addition, at least one pixel column may be located between the second gate driver and the emission control driver; Paragraph 22: At least one of the pixel columns may be located between the first gate driver and the second driver].
Claims 11-13
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US 2017/0345373 A1) in view of Kim Tae-Jin (US 2017/0053597 A1) and Shikina et al (US 2011/0284881 A1) as applied to claim 1 above, and further in view of Son et al (US 2022/0246086 A1).
Claim 11
Kang, Kim Tae-Jin and Shikina do not expressly disclose that the viewing angle control line unit overlaps any one of the subpixel driving circuits:
Kang locates at least one pixel circuit between two adjacent sub-blocks [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth subblock SB1-5, respectively], and
none of Kang, Kim Tae-Jin and Shikina describes any part of the inter-column strip lying over a pixel circuit.
Nor does any of them expressly describe a unit pixel driving circuit including at least three subpixel driving circuits:
Kang does not state how many pixel circuits lie between two sub-blocks [e.g., Paragraph 50: At least one pixel circuit PX may be located between the first sub-block SB1-1 and the second sub-block SB1-2, between the second sub-block SB1-2 and the third sub-block SB1-3, between the third sub-block SB1-3 and the fourth sub-block SB1-4, and between the fourth sub-block SB1-4 and the fifth sub-block SB1-5, respectively], and
Shikina’s three single-color pixel circuits placed side by side are such a unit only under the broadest reasonable interpretation stated for claim 4.
However, Son discloses
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wherein each of the first unit pixel driving circuit and the second unit pixel driving circuit includes at least three subpixel driving circuits, [e.g., Paragraph 141: each pixel group PXG may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 positioned in each unit pixel area UPA; Paragraph 154: The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 formed in each unit pixel area UPA may be sub-pixels that emit light of different colors. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively; Paragraph 143: a first pixel circuit PXC1, a second pixel circuit PXC2, and a third pixel circuit PXC3 of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 of the first pixel group PXG1 may be connected in common to the first scan line SL1 and the first power source line PL1 to be driven at the same time; Paragraph 159: the first circuit element CRE1 may be disposed between the first unit pixel area UPA1 in which the first pixel group PXG1 may be positioned and the second unit pixel area UPA2 in which the second pixel group PXG2 may be positioned; Fig. 7: PXG1 (PXC1, PXC2, PXC3) in UPA1 and PXG2 in UPA2 on either side of CRE1] and
the viewing angle control line unit overlaps any one of subpixel driving circuits included in the first unit pixel driving circuit and the second unit pixel driving circuit. [e.g., Paragraph 206: the conductive pattern CDP may be connected to the second electrode ELT2 provided in an adjacent pixel PXL, for example, the second pixel PXL2 of the second pixel group PXG2, and may be integrally formed with the second electrode ELT2; Paragraph 175: the conductive pattern CDP may extend to an area in which the emission unit EMU of the at least one adjacent pixel PXL may be formed, and may be formed integrally with the second electrode ELT2 of the emission unit EMU; Paragraph 147: Each emission unit EMU may overlap a plurality of pixel circuits PXC including the pixel circuit PXC of a corresponding pixel PXL, and may be electrically connected to the pixel circuit PXC in an area overlapping the pixel circuit PXC of the corresponding pixel PXL; Paragraph 147: the first emission unit EMU1 of the first pixel group PXG1 may overlap the first, second, and third pixel circuits PXC1, PXC2, and PXC3 of the first pixel group PXG1; Fig. 12: CDP integral with ELT2 of PXG2; Fig. 7: CDP, CRE1]
Son places the first transistor T1 of the i-th scan stage, which outputs the i-th scan signal to the i-th scan line, in the non-pixel area between the first unit pixel area UPA1 and the second unit pixel area UPA2 of the i-th pixel row [e.g., Paragraph 158: the first circuit element CRE1 may be the first transistor T1 of the i-th stage STi that outputs the i-th scan signal SSi to the i-th scan line SLi using the first clock signal CLK1; Paragraph 159: the first circuit element CRE1 may be disposed between the first unit pixel area UPA1 in which the first pixel group PXG1 may be positioned and the second unit pixel area UPA2 in which the second pixel group PXG2 may be positioned; Paragraph 52: stages included in the gate driver and circuit elements (for example, transistors and capacitors of each stage) constituting the stages may be formed inside the display area DA together with the pixels PXL. For example, the circuit elements of the gate driver may be distributed and disposed in non-pixel areas between the pixels PXL; Fig. 7: CRE1 (T1), UPA1, UPA2],
each unit pixel area holding the pixel circuits of a red, a green and a blue sub-pixel [e.g., Paragraph 141: each pixel group PXG may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 positioned in each unit pixel area UPA; Paragraph 154: The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 formed in each unit pixel area UPA may be sub-pixels that emit light of different colors. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively];
a conductive pattern CDP of the same metal layer as the emission-unit electrodes covers T1 and its clock line [e.g., Paragraph 166: The conductive pattern CDP may be disposed in the display area DA to overlap the first circuit element CRE1; Paragraph 171: the conductive pattern CDP may be formed on the same layer as the first electrodes ELT1 and the second electrodes ELT2 in a process of forming the first electrodes ELT1 and the second electrodes ELT2 of the emission units EMU, and may be formed to cover at least the first circuit element CRE1], and
in the embodiment of Fig. 12 the pattern extends into the adjacent pixel and is formed integrally with the second electrode of that pixel’s emission unit [e.g., Paragraph 175: the conductive pattern CDP may extend to an area in which the emission unit EMU of the at least one adjacent
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pixel PXL may be formed, and may be formed integrally with the second electrode ELT2 of the emission unit EMU; Paragraph 206: the conductive pattern CDP may be connected to the second electrode ELT2 provided in an adjacent pixel PXL, for example, the second pixel PXL2 of the second pixel group PXG2, and may be integrally formed with the second electrode ELT2],
the emission unit overlapping the pixel circuits of its group [e.g., Paragraph 147: Each emission unit EMU may overlap a plurality of pixel circuits PXC including the pixel circuit PXC of a corresponding pixel PXL, and may be electrically connected to the pixel circuit PXC in an area overlapping the pixel circuit PXC of the corresponding pixel PXL].
Kang, Kim Tae-Jin, Shikina and Son are analogous art, because they are from the shared inventive field of light emitting displays, and Son, like Kang, is directed to a gate driver whose stage transistors are placed between the pixels inside the display area.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to place three sub-pixel circuits of a red, a green and a blue sub-pixel between the sub-block strips of Kang, as Son places them on each side of its in-area stage transistor, and to cover the transistors and lines of each strip with Son’s conductive pattern, tied to the low power source and formed integrally with the electrode of the adjacent emission unit, so as to reduce or prevent the deviation in parasitic capacitance between the in-area driver elements and their lines and the surrounding pixels, which otherwise degrades image quality [e.g., Son, Paragraph 169: the conductive pattern CDP may be connected to an adjacent second power source line PL2 to receive the second power source VSS having a constant potential. In this case, the first circuit element CRE1 and a portion of the first clock line CL1 connected thereto may be capped by the conductive pattern CDP connected to the second power source VSS. Therefore, the size of parasitic capacitance formed between the first circuit element CRE1 and the first clock line CL1 and the pixels PXL around them and/or deviation in the parasitic capacitance may be reduced or prevented; Paragraph 243: the deviation in characteristics of the pixels due to the deviation in parasitic capacitance formed between the circuit element of the driving circuit and the signal lines connected thereto and the pixels can be reduced or prevented, thereby improving the image quality of the display device; Paragraph 237: a parasitic capacitance may be generated between second nodes N2 (shown in FIG. 3) of the pixels PXL to which the source electrodes M1_SE of the first transistors M1 and the one electrodes CE of the capacitors Cst may be connected, and the first circuit element CRE1 (in particular, the source and drain electrodes T1_SE and T1_DE of the first transistor T1) and the first clock line CL1],
the pattern being formed in the process of forming the emission-unit electrodes without a further step [e.g., Son, Paragraph 171: the conductive pattern CDP may be formed on the same layer as the first electrodes ELT1 and the second electrodes ELT2 in a process of forming the first electrodes ELT1 and the second electrodes ELT2 of the emission units EMU, and may be formed to cover at least the first circuit element CRE1] and,
when formed integrally with the adjacent second electrode, without a further contact hole [e.g., Son, Paragraph 175: the conductive pattern CDP may extend to an area in which the emission unit EMU of the at least one adjacent pixel PXL may be formed, and may be formed integrally with the second electrode ELT2 of the emission unit EMU].
Kang’s sub-blocks and vertical lines sit between the pixel circuits [e.g., Kang, Paragraph 55: the gate driver 110A is split and disposed between the pixel circuits PX] as Son’s stage element sits between the unit pixel areas, and in the combination the strip carrying the vertical selection control lines and the vertical emission control line is shielded in the same way;
Son states the aim it shares with Kang [e.g., Son, Paragraph 4: An aspect of the disclosure is to provide a display device capable of reducing a non-display area and improving image quality; Paragraph 53: In case that the gate driver is formed inside the display area DA, a non-display area NDA of the display panel PNL can be reduced].
Moreover, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because all the claimed elements were known in the prior art and one skilled in the art could have combined Son’s unit pixel areas and conductive pattern with the display device of Kang, Kim Tae-Jin and Shikina as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. See KSR International co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Claim 12
Regarding claim 12, Son discloses wherein the viewing angle control line unit further includes a metal blocking layer [e.g., Paragraph 166: The conductive pattern CDP may be disposed in the display area DA to overlap the first circuit element CRE1; Paragraph 167: The conductive pattern CDP may also overlap a portion of the first clock line CL1 connected to the first circuit element CRE1; Paragraph 171: the conductive pattern CDP may be formed on the same layer as the first electrodes ELT1 and the second electrodes ELT2 in a process of forming the first electrodes ELT1 and the second electrodes ELT2 of the emission units EMU, and may be formed to cover at least the first circuit element CRE1; Paragraph 203: the conductive pattern CDP may be disposed on the same layer as the first and second electrodes ELT1 and ELT2 of the pixels PXL, and may include the same conductive material as the first and second electrodes ELT1 and ELT2; Paragraph 208: the first and second electrodes ELT1 and
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ELT2 may include at least one metal of various metal materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), Neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (MO), and copper (Cu), or alloys thereof; Fig. 11: CDP; Fig. 7: CDP]
between the at least one viewing angle control line and a light emitting device. [e.g., Paragraph 169: the conductive pattern CDP may be connected to an adjacent second power source line PL2 to receive the second power source VSS having a constant potential. In this case, the first circuit element CRE1 and a portion of the first clock line CL1 connected thereto may be capped by the conductive pattern CDP connected to the second power source VSS. Therefore, the size of parasitic capacitance formed between the first circuit element CRE1 and the first clock line CL1 and the pixels PXL around them and/or deviation in the parasitic capacitance may be reduced or prevented; Paragraph 240: the conductive pattern CDP may be formed on the first circuit element CRE1 and/or the first clock line CL1, and the conductive pattern CDP may be connected to an adjacent power source line (for example, the second power source line PL2). Accordingly, the size of the parasitic capacitance formed between the source and drain electrodes T1_SE and T1_DE of the first circuit element CRE1 and the first clock line CL1, and the second nodes N2 of the
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pixels PXL and/or the deviation in the parasitic capacitance may be reduced; Paragraph 68: the second node N2 may be a node (also referred to as a source node of the first transistor M1 or an anode node of the pixel PXL) to which a first electrode (for example, a source electrode) of the first transistor M1 and the first electrode ELT1 of the emission unit EMU may be connected; Paragraph 204: The conductive pattern CDP may have a larger area than the first circuit element CRE1 so as to cover at least the first circuit element CRE1. For example, the conductive pattern CDP may cover the upper portion of the first circuit element CRE1, and may further cover the upper portion of the first clock line CL1 and/or at least one scan line SL around the first circuit element CRE1; Paragraph 241: the conductive pattern CDP may be simultaneously formed with the electrodes provided on the emission units EMU of the display layer DPL, and may be formed to shield the first circuit element CRE1 and/or the first clock line CL1 of the circuit layer PCL; Fig. 11: CDP over CRE1, between the circuit layer PCL and the display layer DPL, beside the light emitting elements LD of PXG1 and PXG2; Fig. 12: CDP integral with ELT2]
The same reasons to combine apply.
Claim 13
Regarding claim 13, Son discloses wherein each of the kth unit pixel driving circuit and the k+1th unit pixel driving circuit includes at least three subpixel driving circuits, [e.g., Paragraph 141: each pixel group PXG may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 positioned in each unit pixel area UPA; Paragraph 154: The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 formed in each unit pixel area UPA may be sub-pixels that emit light of different colors. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively; Paragraph 159: the first circuit element CRE1 may be disposed between the first unit pixel area UPA1 in which the first pixel group PXG1 may be positioned and the second unit pixel area UPA2 in which the second pixel group PXG2 may be positioned; Fig. 7: PXG1 and PXG2 in UPA1 and UPA2] and
the gate control line unit overlaps a light emitting device connected to any one of subpixel driving circuits provided in the kth unit pixel driving circuit and the k+1th unit pixel driving circuit. [e.g., Paragraph 175: the conductive pattern CDP may extend to an area in which the emission unit EMU of the at least one adjacent pixel PXL may be formed, and may be formed integrally with the second electrode ELT2 of the emission unit EMU; Paragraph 206: the conductive pattern CDP may be connected to the second electrode ELT2 provided in an adjacent pixel PXL, for example, the second pixel PXL2 of the second pixel group PXG2, and may be integrally formed with the second electrode ELT2; Paragraph 76: The emission unit EMU may include the first electrode ELT1, a second electrode ELT2, and at least one light emitting element LD connected between the first power source line PL1 and the second power source line PL2; Fig. 12: CDP formed integrally with ELT2 of the emission unit of PXG2; Fig. 4: EMU, ELT1, ELT2, LD]
The same reasons to combine apply.
Response to Arguments
The rejections of claims 1-20 under 35 U.S.C. 112(b) set forth in the Office action mailed 17 June 2026 (paragraphs 4-10) are withdrawn in view of the amendments to claims 1, 3, 7, 14-16, 18 and 19 filed 9 September 2026.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
14 September 2026
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