DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 07/29/2026 is acknowledged. As a result, claims 1-18 are pending for examination.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Please below detailed rejections with new references.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak)
Regarding Claim 1, Lübbers teaches A power detector comprising: a forward power detector circuit configured to receive a forward signal from a coupler associated with a transmission path conductor;
(Lübbers[0022] The at least one coupler 106 couples a portion of the power incident at its input port (“forward power”) to a forward coupled port.
[0023] The forward coupling port and the reverse coupling port of the at least one coupler 106 are coupled to inputs of the power detector circuitry 108.)
a reverse power detector circuit configured to receive a reverse signal from the coupler associated with the transmission path conductor, wherein the reverse signal is based on a signal reflected from an antenna;
(Lübbers [0022, line 6] The at least one coupler 106 couples a portion of the power incident upon the output port (“reverse power” or “reflected power”), e.g. reflected from the load, to a reverse coupled port.
[0018, line 4] The load may be an antenna.
[0023] The forward coupling port and the reverse coupling port of the at least one coupler 106 are coupled to inputs of the power detector circuitry 108.)
But Lübbers does not teach a summing node configured to: receive a first current from the forward power detector circuit based on the forward signal from the coupler;
receive a second current from the reverse power detector circuit based on the reverse signal from the coupler ;
and sum the first current and the second current into a combined power-detected signal.
However, El-Damak teaches a summing node configured to: receive a first current from the forward power detector circuit based on the forward signal from the coupler
(El-Damak [0022] The apparatus 200 also includes a first current sum sense resistor RS1 245 coupled between the first switched voltage input terminal 205 and the summing node 238.)
(Note: The “first current” in the claim limitation is received from switched voltage input terminal 205 in the reference.)
receive a second current from the reverse power detector circuit based on the reverse signal from the coupler;
[0022, line 3] The apparatus 200 further includes a second current sum sense resistor RS2 250 coupled between the second switched voltage input terminal 208 and the summing node 238.
(Note: The “second current” in the claim limitation is received from switched voltage input terminal 208 in the reference.)
and sum the first current and the second current into a combined power-detected signal.
(El-Damak [0024] FIG. 3 is a schematic diagram of a coupled inductor current sensing apparatus 300 according to various example embodiments. The apparatus 300 includes the two switched voltage input terminals 205 and 208, the switched drive phases 210 and 212, the output terminal 218, the inductors L1 215 and L2 222, the inductor currents I1 225 and I2 228, the current sum sense capacitor 235, the summing node 238.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and by incorporating El-Damak for the power detector at the output of an amplifier to be able to combine the measurements of both the forward signal and reverse signal from an antenna and create one output signal.
The motivation of doing so would have enabled the power detector to control or calibrate the output signal.
Claims 2, 5-8, 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak) and in further view of NAKAMOTO (US 20120235733 A1, hereinafter Nakamoto)
Regarding Claim 2, Lubbers and El-Damak disclose the power detector of claim 1, but fail to teach a boost circuit configured to receive the forward signal and generate a boosted signal when the forward signal is below a threshold.
In a similar endeavor, Nakamoto teaches a boost circuit configured to receive the forward signal and generate a boosted signal when the forward signal is below a threshold
(Nakamoto [0029] by coupling the output of a power amplifier, the power of which is to be detected, to the anode of the diode D1, the output power of the power amplifier can be detected.
(Note: Power amplifier in the reference acts as a boost circuit in the claim limitation.)
[0028] FIG. 1 illustrates operation of a power detector circuit using a diode. In this power detector circuit, the high-frequency signal, which is the AC signal for power detection, is supplied to the input terminal RFIN, and when the high-frequency signal voltage exceeds the threshold voltage of the diode D1, the diode D1 becomes conducting and a current occurs.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto for the power detector to have a boost circuit to receive a forward signal when it is measured against a threshold.
The motivation of doing so would have enabled the power detector to be able to amplify the signal as long as it meets the criteria of “a threshold”.
Regarding Claim 5, Lubbers and El-Damak disclose the power detector of claim 1, but fail to teach wherein the forward power detector circuit comprises a plurality of stacked diodes configured to rectify the forward signal to a direct current (DC) signal.
In a similar endeavor, Nakamoto teaches wherein the forward power detector circuit comprises a plurality of stacked diodes configured to rectify the forward signal to a direct current (DC) signal.
(Nakamoto [0034, line 9] the AC component of the high-frequency signal is applied to node n1. The first diode D1 is a diode which rectifies the AC component applied to node n1, and the second diode D2 is a compensating diode which compensates fluctuation of the diode threshold voltage. Both diodes D1 and D2 are unidirectional elements having PN junctions or similar.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to have a detector circuit comprised of plurality of stacked diodes to rectify the forward signal into a DC signal.
The motivation of doing so would have enabled the detector circuit for a efficient control and calibration.
Regarding Claim 6, Lubbers and El-Damak disclose the power detector of claim 1, but fail to teach wherein the reverse power detector circuit comprises a plurality of stacked diodes configured to rectify the reverse signal to a direct current (DC) signal.
In a similar endeavor, Nakamoto teaches wherein the reverse power detector circuit comprises a plurality of stacked diodes configured to rectify the reverse signal to a direct current (DC) signal.
(Nakamoto [0034, line 9] the AC component of the high-frequency signal is applied to node n1. The first diode D1 is a diode which rectifies the AC component applied to node n1, and the second diode D2 is a compensating diode which compensates fluctuation of the diode threshold voltage. Both diodes D1 and D2 are unidirectional elements having PN junctions or similar.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to have a detector circuit comprised of plurality of stacked diodes to rectify the reverse signal into a DC signal.
The motivation of doing so would have enabled the detector circuit for an efficient control and calibration.
Regarding Claim 7, Lubbers and El-Damak disclose the power detector of claim 5, but fail to teach a bias circuit connected to the forward power detector circuit and configured to bias a transistor serially positioned with the plurality of stacked diodes;
In a similar endeavor, Nakamoto teaches a bias circuit connected to the forward power detector circuit and configured to bias a transistor serially positioned with the plurality of stacked diodes;
(Nakamoto [0040, line 7] The first current mirror circuit CM1 has an N-channel MOS (NMOS) transistor N10, and, NMOS transistors N11, N12, N13 refer to [Fig 3])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to create a bias circuit.
The motivation of doing so would have enabled the detector circuit for an improved accuracy and stability.
Regarding Claim 8, Lubbers and El-Damak disclose the power detector of claim 7, but fail to teach wherein the bias circuit comprises a second plurality of stacked diodes, a current source, and a programmable resistor.
In a similar endeavor, Nakamoto teaches wherein the bias circuit comprises a second plurality of stacked diodes, a current source, and a programmable resistor.
(Nakamoto [0035] A DC voltage VB, which is a power supply voltage and constant bias voltage, is applied, via first and second resistors RP and RR, to the anode terminals n1 and n2 of the first and second diodes D1 and D2. The first resistor RP is a resistor to supply the DC voltage VB to the terminal n1 to which the above-described AC component is applied. The second resistor RR is provided in the reference circuit 22 as well, corresponding to the first resistor RP.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to be able to define the formation of the bias circuit.
The motivation of doing so would have enabled the detector circuit for an improved accuracy and stability.
Regarding Claim 10, Lubbers and El-Damak disclose the power detector of claim 8, but fail to teach wherein the current source is temperature compensated.
In a similar endeavor, Nakamoto teaches wherein the current source is temperature compensated.
(Nakamoto [0050] When the threshold voltages of the first and second diodes D1 and D2 change due to process and temperature fluctuations, the absolute values of the currents flowing therewithin change, and the current flowing in the resistor R1 changes to I.sub.AC-I.sub.DC+.DELTA.I, while the current flowing in the resistor R2 similarly changes to I.sub.DC-.DELTA.I.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to have the temperature compensated current source.
The motivation of doing so would have enabled the detector circuit to be more stable, efficient and accurate.
Regarding Claim 11 and as applied to Claim 1, El-Damak further teaches
wherein the reverse power detector circuit further comprises: an input node;
(El-Damak [0018] The apparatus 200 receives a switched drive voltage (“drive phase”) 210 at the input terminal 205 and a drive phase 212 at the input terminal 208.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and by incorporating El-Damak to have an input node at the reverse power detector circuit.
The motivation of doing so would have enabled the overall detector circuit to be stable and efficient in control and calibration.
But Lubbers and El-Damak do not disclose the following limitations
a first current mirror coupled to the input node through a diode;
However, Nakamoto discloses a first current mirror coupled to the input node through a diode;
(Nakamoto [0040] The difference current generation circuit 24 has a first current mirror circuit CM1 which copies the current I.sub.AC-I.sub.DC of the input circuit 20 to the node n4.)
and a second current mirror coupled to the first current mirror and the summing node.
(Nakamoto [0040, line 3] a second current mirror circuit CM2 which copies the current I.sub.DC of the reference circuit 22 to the node n3.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to have a reverse power detector circuit signal measurement process.
The motivation of doing so would have enabled the overall detector circuit to be stable and efficient in control and calibration.
Regarding Claim 13 and as applied to Claim 11, Nakamoto further teaches wherein the second current mirror comprises a binary array of transistors configured to allow selection of a gain provided by the second current mirror.
(Nakamoto [0041] The second current mirror circuit CM2 has an NMOS transistor N20 coupled to the reference circuit 22, and a transistor N21 the gate of which is coupled to the drain and gate of this NMOS transistor N20. In this current mirror circuit CM2 also, current is copied at a current mirror ratio according to the transistor channel widths of the transistors N20 and N21.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Nakamoto to allow the selection of a gain.
The motivation of doing so would have enabled the detector circuit to function with improved efficiency.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak) and in further view of Voor et al. (US 20230421194 A1, hereinafter Voor)
Regarding Claim 3, Lubbers and El-Damak teach the power detector of claim 1, but fail to teach wherein the reverse power detector circuit does not generate the second current when the reverse signal is below a threshold.
However, in a similar endeavor, Voor teaches wherein the reverse power detector circuit does not generate the second current when the reverse signal is below a threshold.
(Voor [0082, line 15] When the value measured by the second peak detector drops below a second threshold (e.g., the out of band blocker finished its transmission), a determination may be made to cause a mode switch back to the rural mode.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers and El-Damak and by incorporating Voor to enable the detector circuit not to have the second current when the reverse signal is below “a threshold”.
The motivation of doing so would have enabled the detector circuit to have an efficient operation.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak), Voor et al. (US 20230421194 A1, hereinafter Voor) and in further view of NAKAMOTO (US 20120235733 A1, hereinafter Nakamoto)
Regarding Claim 4, Lubbers and El-Damak and Voor teach the power detector of claim 3, but fail to teach a transistor in the reverse power detector circuit configured to program the threshold.
However, in a similar endeavor, Nakamoto teaches a transistor in the reverse power detector circuit configured to program the threshold.
(Nakamoto [0041] The second current mirror circuit CM2 has an NMOS transistor N20 coupled to the reference circuit 22, and a transistor N21 the gate of which is coupled to the drain and gate of this NMOS transistor N20.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers, El-Damak and Voor and by incorporating Nakamoto to enable the detector circuit to have a transistor to program threshold.
The motivation of doing so would have enabled the detector circuit to have efficient operation in control and calibration.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak), NAKAMOTO (US 20120235733 A1, hereinafter Nakamoto) and in further view of Venkateswaran (US 9973204 B1, hereinafter Venkateswaran)
Regarding Claim 9, Lubbers and El-Damak and Nakamoto teach the power detector of claim 8, but fail to teach wherein the programmable resistor comprises a digital to analog converter (DAC) connected to a plurality of transistors such that different resistors are activated depending on which of the plurality of transistors are activated by the DAC.
However, in a similar endeavor, Venkateswaran teaches wherein the programmable resistor comprises a digital to analog converter (DAC) connected to a plurality of transistors such that different resistors are activated depending on which of the plurality of transistors are activated by the DAC.
(Venkateswaran [Col. 4, line 45] In some embodiments, the resistor string DAC 100 includes 2.sup.N resistors 105, where N is a number of bits received by the resistor string DAC as input for controlling a value of an output of the resistor string DAC 100. The resistors 105 may be arranged into a plurality of columns 110A, 110B, 110C, 110D, 110E, and 110F (110A-110F), where each column has a corresponding column output 112A, 112B, 112C, 112D, 112E, and 112F (112A-112F). Each of the column outputs 112A-112F may couple to an output 115 of the resistor string DAC via a respective column switch 120A, 120B, 120C, 120D, 120E, and 120F (120A-120F). Each of the resistors may couple to a column output 112A-112F via a respective row switch 125. [Col.6, line 1] Each of the column switches 120A-120F and the row switches 125 may comprise mechanical switches (e.g., relays) or electrical switches (e.g., transistors or other electrical components, which may sometimes be referred to as solid-state switches). For example, the column switches 120A-120F and the row switches 125 may each comprise bipolar junction transistors (BJTs))
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers, El-Damak and Nakamoto and by incorporating Venkateswaran to have programmable resistors connected with the digital to analog converter.
The motivation of doing so would have enabled the converter to function efficiently.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, hereinafter El-Damak), NAKAMOTO (US 20120235733 A1, hereinafter Nakamoto) and in further view of Voor et al. (US 20230421194 A1, hereinafter Voor)
Regarding Claim 12, Lubbers and El-Damak and Nakamoto teach the power detector of claim 11, but fail to teach wherein the first current mirror is configured to remain off until the reverse signal rises above a threshold.
However, in a similar endeavor, Voor teaches wherein the first current mirror is configured to remain off until the reverse signal rises above a threshold.
(Voor [0058] When the signal level of a receive RF signal exceeds a given threshold, the signal could potentially harm LNA performance by overloading its input. When such an overload condition is detected, the controller may reconfigure the FEM to a more protected mode (e.g., one of urban or bypass modes) to protect the LNA.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Lubbers, El-Damak and Nakamoto and by incorporating Voor to enable the detector circuit to have the first current mirror to remain off until “a threshold” kicks in.
The motivation of doing so would have enabled the detector circuit to be stable with improved accuracy.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Voor (US 20230421194 A1, hereinafter Voor) in view of Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1)
Regarding Claim 14, Voor teaches
a transmission chain comprising: a baseband processor (BBP);
(Voor [0033, line 20] a baseband processor and/or application processor may be present.)
a power amplifier coupled to the BBP;
(Voor [0004, line 3] the receive path comprising at least one low noise amplifier (LNA).)
But Voor does not teach
a coupler
and a power detector coupled to an output of the power amplifier, the power detector comprising: a forward power detector circuit configured to receive a forward signal from a coupler associated with a transmission path conductor;
a reverse power detector circuit configured to receive a reverse signal from the coupler associated with the transmission path conductor, wherein the reverse signal is based on a signal reflected from an antenna;
However, Lubbers teaches
a coupler
(Lubbers [0019, line 5] In one embodiment, the at least one coupler 106 is a bi-directional coupler.)
and a power detector coupled to an output of the power amplifier, the power detector comprising: a forward power detector circuit configured to receive a forward signal from [[a]] the coupler associated with a transmission path conductor;
(Lübbers[0022] The at least one coupler 106 couples a portion of the power incident at its input port (“forward power”) to a forward coupled port.
[0023] The forward coupling port and the reverse coupling port of the at least one coupler 106 are coupled to inputs of the power detector circuitry 108.)
a reverse power detector circuit configured to receive a reverse signal from the coupler associated with the transmission path conductor, wherein the reverse signal is based on a signal reflected from an antenna;
(Lübbers [0022, line 6] The at least one coupler 106 couples a portion of the power incident upon the output port (“reverse power” or “reflected power”), e.g. reflected from the load, to a reverse coupled port.
[0018, line 4] The load may be an antenna.
[0023] The forward coupling port and the reverse coupling port of the at least one coupler 106 are coupled to inputs of the power detector circuitry 108.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Voor by incorporating Lubbers to have a Baseband processor in the transmission line to for the forward and reveres power detector circuits to be able to receive forward and reverse signals from the coupler associated with the transmission path.
The motivation of doing so would have enabled the power detector to control or calibrate the output signal.
However, Voor and Lubbers do not teach a summing node configured to: receive a first current from the forward power detector circuit;
receive a second current from the reverse power detector circuit;
and sum the first current and the second current into a combined power-detected signal.
However, El-Damak teaches a summing node configured to: receive a first current from the forward power detector circuit;
(El-Damak [0022] The apparatus 200 also includes a first current sum sense resistor RS1 245 coupled between the first switched voltage input terminal 205 and the summing node 238.)
(Note: The “first current” in the claim limitation is received from switched voltage input terminal 205 in the reference.)
receive a second current from the reverse power detector circuit;
[0022, line 3] The apparatus 200 further includes a second current sum sense resistor RS2 250 coupled between the second switched voltage input terminal 208 and the summing node 238.
(Note: The “second current” in the claim limitation is received from switched voltage input terminal 208 in the reference.)
and sum the first current and the second current into a combined power-detected signal.
(El-Damak [0024] FIG. 3 is a schematic diagram of a coupled inductor current sensing apparatus 300 according to various example embodiments. The apparatus 300 includes the two switched voltage input terminals 205 and 208, the switched drive phases 210 and 212, the output terminal 218, the inductors L1 215 and L2 222, the inductor currents I1 225 and I2 228, the current sum sense capacitor 235, the summing node 238.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Voor and Lubbers and by incorporating El-Damak for the power detector at the output of an amplifier to be able to combine the measurements of both the forward signal and reverse signal from an antenna and create one output signal.
The motivation of doing so would have enabled the power detector to control or calibrate the output signal.
Regarding Claim 16, Voor further teaches wherein the reverse power detector circuit does not generate the second current when the reverse signal is below a threshold.
(Voor [0082, line 15] When the value measured by the second peak detector drops below a second threshold (e.g., the out of band blocker finished its transmission), a determination may be made to cause a mode switch back to the rural mode.)
Claims 15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Voor (US 20230421194 A1, hereinafter Voor), Lübbers et al. (US 20200099457 A1, hereinafter Lubbers) in view of El-Damak et al. (US 20160187386 A1, and in further view of NAKAMOTO (US 20120235733 A1, hereinafter Nakamoto)
Regarding Claim 15, Voor, Lubbers and El-Damak teach the mobile communication device of claim 14, but fail to teach wherein the power detector further comprises a boost circuit configured to receive the forward signal and generate a boosted signal when the forward signal is below a threshold.
However, in a similar endeavor, Nakamoto teaches wherein the power detector further comprises a boost circuit configured to receive the forward signal and generate a boosted signal when the forward signal is below a threshold.
(Nakamoto [0029] by coupling the output of a power amplifier, the power of which is to be detected, to the anode of the diode D1, the output power of the power amplifier can be detected. (Note: Power amplifer in the reference acts as a boost circuit in the claim limitation.) [0028] FIG. 1 illustrates operation of a power detector circuit using a diode. In this power detector circuit, the high-frequency signal, which is the AC signal for power detection, is supplied to the input terminal RFIN, and when the high-frequency signal voltage exceeds the threshold voltage of the diode D1, the diode D1 becomes conducting and a current occurs.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Voor, Lubbers and El-Damak and by incorporating Nakamoto for the power detector to have a boost circuit to receive a forward signal when it is measured against a threshold.
The motivation of doing so would have enabled the power detector to be able to amplify the signal as long as it meets the criteria of “a threshold”.
Regarding Claim 17, Voor, Lubbers and El-Damak teach the mobile communication device of claim 16, but fail to teach further comprising a transistor in the reverse power detector circuit configured to program the threshold.
However, in a similar endeavor, Nakamoto teaches
(Nakamoto [0041] The second current mirror circuit CM2 has an NMOS transistor N20 coupled to the reference circuit 22, and a transistor N21 the gate of which is coupled to the drain and gate of this NMOS transistor N20.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Voor, Lubbers and El-Damak and by incorporating Nakamoto to enable the detector circuit to have a transistor to program threshold.
The motivation of doing so would have enabled the detector circuit to have efficient operation in control and calibration.
Regarding Claim 18, Voor, Lubbers and El-Damak teach the mobile communication device of claim 14, but fail to teach an autocalibration circuit coupled to the power detector.
However, in a similar endeavor, Nakamoto teaches
an autocalibration circuit coupled to the power detector.
(Nakamoto [0031, line 7 and Fig 2] a calibration circuit 14 which performs calibration thereof. The calibration circuit 14 performs an operation to calibrate the power detector circuit by means of an incorporated calibration control circuit 16.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the examined application to have modified Voor, Lubbers and El-Damak and by incorporating Nakamoto to have a autocalibration circuit with the power detector.
The motivation of doing so would have enabled the power detector with improved calibration.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANA HASSAN MAHMUD whose telephone number is (571)272-8939. The examiner can normally be reached Mon-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kathy Wang-Hurst can be reached at 5712705371. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RANA H MAHMUD/Examiner, Art Unit 2644
/KATHY W WANG-HURST/Supervisory Patent Examiner, Art Unit 2644
