DETAILED ACTION
This action is responsive to the following: the application and information disclosure statement filed on June 21, 2024 and the information disclosure statement filed on October 17, 2025.
Claims 1-20 are pending. Claims 1 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Benefit Status
Instant application (“Memory Device and Operation Method Thereof”) was filed 6/12/2024 as a continuation-in-part of application 17558673 (“Ternary Content Addressable Memory and Operation Method Thereof”), which became abandoned effective June 27, 2024 for failure to timely file a proper reply the Final Rejection mailed March 26, 2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 21, 2024 and October 17, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
the use of the term “wildcard” in claim 7.
The term “wildcard” in claim 7 is confusing since a search input with a “wildcard” bit is said to correspond to a in-memory “don’t care” bit. These terms in reference to the data held by a bit are understood to be interchangeable in the art. For instance, Li et al (US 20200258587 A1) states in paragraph 22 ‘A ternary CAM (“TCAM”) operates on an input pattern (and stores data) containing not only binary bits of “0” and “1”, but also an “X” value. An “X” is sometimes referred to as a “don't care” or a “wildcard”.’ There is not definition of wildcard in applicant’s specification to alter this understanding of the term. Thus, the terms “X,” “wildcard,” and “don’t care” are understood to be interchangeable and have the same meaning in the context of data operation in a TCAM type memory.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-12, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over de Sandre (US 6944038 B2) in view of Goda et al (US 20120230116 ).
Regarding Independent Claim 1, de Sandra teaches a memory device, comprising:
a memory array (Fig. 2: 350), comprising:
M*N memory cells (Fig. 2: 210), wherein a memory cell (Fig. 2: 210) among the M*N memory cells is located at an m-th column (Fig. 2: 241, 242) and n-th row (Fig. 2: 220), and the memory cell comprises a first transistor (Fig. 2: 211) and a second transistor (Fig. 2: 212);
M first bit-lines (Fig. 2: 241), wherein an m-th first bit-line among the M first bit-lines (Fig. 2: 241) is electrically connected to a first terminal of the first transistor (Fig. 2: 211), and a first search voltage is applied to the m-th first bit-line;
M second bit-lines (Fig. 2: 242), wherein an m-th second bit-line among the M second bit-lines (Fig. 2: 242) is electrically connected to a first terminal of the second transistor (Fig. 2: 212), and a second search voltage is applied to them-th second bit-line;
M first source lines (Fig. 2: 230), wherein an m-th first source line (Fig. 2: 230) among the M first source lines is electrically connected to a second terminal of the first transistor (Fig. 2: 211), and an m-th first sensing current is selectively generated in response to the first search voltage and a threshold voltage of the first transistor;
N word lines (Fig. 2: 220), wherein control terminals of the first transistor (Fig. 2: 211) and the second transistor (Fig. 2: 211) are electrically connected to an n-th word line among the N word lines,
a control circuit (Fig. 2: 370, 360, 380,385, 371, 372), electrically connected to the memory array (Fig. 2: 350) through the M first bit-lines (Fig. 2: 211), the M second bit-lines (Fig. 2: 212), the M first source lines (Fig. 2: 230), and the N word lines, wherein the control circuit comprises:
a sensing circuit (Fig. 2: 380), configured to receive the m-th first sensing current through the m-th first source line (Fig. 2: 230), and generate a sensing circuit output representing whether the m-th first sensing current and the m-th second sensing current are generated (col 2 lines 20-23),
De Sandre fails to teach M second source lines, wherein an m-th second source line among the M second source lines is electrically connected to a second terminal of the second transistor, and an m-th second sensing current is selectively generated in response to the second search voltage and a threshold voltage of the second transistor;
And fails to teach a select voltage is applied to the n-th word line, and a pass-through voltage is applied to other (N-1) word lines among the N word lines; and
Goda teaches M second source lines (Fig. 7: src1-3; Goda teaches a separate source line for each column of stacked cells), wherein an m-th second source line among the M second source lines is electrically connected to a second terminal of the second transistor, and an m-th second sensing current is selectively generated in response to the second search voltage and a threshold voltage of the second transistor;
And a select voltage (Fig. 8: Vr) is applied to the n-th word line (Fig. 8: WLn), and a pass-through voltage (Fig. 8: Vpass) is applied to other (N-1) word lines (Fig. 8: 810, 811) among the N word lines; and
Goda teaches that the individual source lines provide the ability to individually bias columns to compensate for issues like program disturb that can impact sensing. Thus, this would represent an obvious improvement for a structure like a TCAM where current from two transistors are compared to determine what is stored in the cell.
It would the therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Goda to the teachings of de Sandre to produce a memory array of TCAM cells with separate source lines for each column of transistors in a block of transistors, wherein pairs of parallel transistors in teach column combine to form the TCAM cells of the array.
Regarding Claim 2, de Sandre and Goda teach the limitations of claim 1. Goda further teaches the memory device according to claim 1, wherein the control circuit further comprises:
a memory controller (Fig. 13: 1370), electrically connected to the memory array (fig. 13: 1330), the sensing circuit (Fig. 13: 1350), and a host device (Fig. 13: 1310),
de Sandre teaches performing a search operation on the memory array (Col 3 lines 5-23).
Regarding Claim 3, de Sandre and Goda teach the limitations of claim 2. De Sandre further teaches the memory device according to claim 2, wherein
M memory cells among the M*N memory cells located at the n-th row are programmed to store an in-memory data, and the in-memory data comprises M in-memory bits (Col 3 lines 5-23), wherein
the threshold voltage of the first transistor and the threshold voltage of the second transistor are programmed according to an m-th in-memory bit among the M in-memory bits (Col 3 lines 5-23).
Regarding Claim 4, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches the memory controller determines whether the in-memory data is equivalent to the search input based on the sensing circuit output. (col 3 lines 24-35)
Regarding Claim 5, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches determines that the m-th in-memory bit is inequivalent to the m-th search bit if the sensing circuit output represents that one of the m-th first sensing current and the m-th second sensing current is generated, and
the memory controller determines that the m-th in-memory bit is equivalent to the m-th search bit if the sensing circuit output represents that none of the m-th first sensing current and the m-th second sensing current is generated (col 3 lines 3-35).
Regarding Claim 6, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches the threshold voltage of the first transistor is programmed to a high threshold voltage, and the threshold voltage of the second transistor is programmed to a low threshold voltage if them-th in-memory bit represents a binary "0” (Col 3 lines 15-20);
the threshold voltage of the first transistor is programmed to the low threshold voltage, and the threshold voltage of the second transistor is programmed to the high threshold voltage if them-th in-memory bit represents a binary "1" (Col 3 lines 8-15);
the threshold voltage of the first transistor is programmed to the high threshold voltage, and the threshold voltage of the second transistor is programmed to the high threshold voltage if the m-th in-memory bit represents a "don't care" bit (col 3 lines 20-23); and
the threshold voltage of the first transistor is programmed to the low threshold voltage, and the threshold voltage of the second transistor is programmed to the low threshold voltage if them-th in-memory bit represents an "invalid" bit (from the description in de Sandra although not explicitly state this is implied form the description of the valid bit values).
Regarding Claim 7, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches the search input corresponds to a range of search values if a least significant bit (LSB) of the search input is a "wildcard" bit, and
the in-memory data corresponds to a range of in-memory values if a least significant bit (LSB) of the in-memory data is a "don't care" bit. (col 3 lines 20-35)
This claim is understood to mean that “if search input data looking for an X is input then it corresponds to searching for an X in the memory array.” This is understood to be implicit in de Sandre’s description of Searching for an X and how the memory indicates that an X has been found.
Regarding Claim 9, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches the first search voltage and the second search voltage are set according to an m-th search bit among the M search bits (col 3 lines 5-23).
Regarding Claim 10, de Sandre and Goda teach the limitations of claim 9. the first search voltage is a high search voltage, and the second search voltage is a low search voltage if the m-th search bit represents a binary "0" (Col 3 lines 15-20);
the first search voltage is the low search voltage, and the second search voltage is the high search voltage if the m-th search bit represents a binary "1" (Col 3 lines 8-15);
the first search voltage is the low search voltage, and the second search voltage is the low search voltage if the m-th search bit represents a "wildcard" bit (Col 3 lines 20-23); and
the first search voltage is the high search voltage, and the second search voltage is the high search voltage if the m-th search bit represents an "invalid" bit. (from the description in de Sandra although not explicitly state this is implied form the description of the valid bit values)
Regarding Claim 11, de Sandre and Goda teach the limitations of claim 10. De Sandre further teaches a high threshold voltage is greater than the high search voltage, the high search voltage is greater than a low threshold voltage, and the low threshold voltage is greater than the low search voltage, wherein
the threshold voltage of the first transistor is programmed to one of the high threshold voltage and the low threshold voltage according to the m-th in-memory bit and
the threshold voltage of the second transistor is programmed to one of the high threshold voltage and the low threshold voltage according to the m-th in-memory bit.
(Col 3 lines 5-23 state that transistors in the memory cell do not conduct when the high voltage is on a bit line of a with high threshold voltages and thus therefore the threshold voltage is higher than the high supply voltage as only transistors at or above the threshold voltage conduct. The same is said to be true for a threshold voltage transistor with a low voltage on the bit line. However, de Sandre states that a low threshold voltage with the high bit line voltage applied will conduct. Thus, implicitly the high voltage is greater than low threshold voltage but less than the high threshold voltage.)
Regarding Claim 12, de Sandre and Goda teach the limitations of claim 3. De Sandre further teaches sensing units (Fig. 2: 380) on each source line (Fig. 2: 230). Since Goda teaches a separate source line (Fig. 7: src0-3) for each column of transistors. It would be reasonable to combine the two references such that each source line for each column of transistors would have a sensing unit.
Regarding Claim 19, de Sandre and Goda teach the limitations of claim 1. De Sandre further teaches a third search voltage is applied to a k-th first bit-line among the M first bit-lines
and a fourth search voltage is applied to a k-th second bit-line among the M second bit-lines, wherein
the first search voltage is equivalent to one of a first high search voltage and a low search voltage,
the second search voltage is equivalent to one of the first high search voltage and the low search voltage,
the third search voltage is equivalent to one of a second high search voltage and the low search voltage, and
the fourth search voltage is equivalent to one of the second high search voltage and the low search voltage, wherein k is a positive integer, k is different from m, and k is smaller than or equivalent to M
(De Sandre in Col 3 lines 5-23 teaches applying a high and low voltage to bit lines during a search. Therefore, de Sandre also teaches applying equivalent voltages to some subset of bit lines.)
Regarding Independent Claim 20, de Sandra teaches 20. An operation method applied to a memory device comprising a memory array (Fig. 2: 350) and a control circuit (Fig. 2: 370, 360, 380,385, 371, 372), wherein the memory array (Fig. 2: 350)comprises M*N memory cells (Fig. 2: 210), wherein the memory array (Fig. 2: 350) is electrically connected to the control circuit (Fig. 2: 370, 360, 380,385, 371, 372) through M first bit-lines (Fig. 2: 241), M second bit-lines (Fig. 2: 242), M first source lines (Fig. 2: 230), and N word lines row (Fig. 2: 220), and a memory cell (Fig. 2: 210) among the M*N memory cells (Fig. 2: 210) comprises a first transistor (Fig. 2: 211) and a second transistor (Fig. 2: 212), wherein the operation method comprises steps of:
applying a first search voltage to an m-th first bit-line (Fig. 2: 241), wherein an m-th first sensing current is selectively generated in response to the first search voltage and a threshold voltage of the first transistor (col 3 lines 5-23);
applying a second search voltage to an m-th second bit-line (Fig. 2: 242), wherein an m-th second sensing current is selectively generated in response to the second search voltage and a threshold voltage of the second transistor (col 3 lines 5-23);
receiving the m-th first sensing current through them-th first source line (Fig. 2: 230);
generating a sensing circuit (Fig. 2: 380) output based on the m-th first sensing current and the m-th second sensing current (col 2 lines 20-23).
wherein M, N, m, and n are positive integers, m is smaller than or equivalent to M, and n is smaller than or equivalent to N.
de Sandra fails to teach M second source lines and
applying a select voltage to an n-th word line among the N word lines, wherein
control terminals of the first transistor and a second transistor are electrically connected to the n-th word line;
applying a pass-through voltage to other (N-1) word lines among the N word lines;
Goda teaches M second source lines (Fig. 7: src1-3; Goda teaches a separate source line for each column of stacked cells), wherein an m-th second source line among the M second source lines is electrically connected to a second terminal of the second transistor, and an m-th second sensing current is selectively generated in response to the second search voltage and a threshold voltage of the second transistor;
And a select voltage (Fig. 8: Vr) is applied to the n-th word line (Fig. 8: WLn), and a pass-through voltage (Fig. 8: Vpass) is applied to other (N-1) word lines (Fig. 8: 810, 811) among the N word lines; and
Goda teaches that the individual source lines provide the ability to individually bias columns to compensate for issues like program disturb that can impact sensing. Thus, this would represent an obvious improvement for a structure like a TCAM where current from two transistors are compared to determine what is stored in the cell.
It would the therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Goda to the teachings of de Sandre to produce a method of operating a TCAM array with separate source lines for each column of transistors in a block of transistors, wherein pairs of parallel transistors in teach column combine to form the TCAM cells of the array.
Allowable Subject Matter
Claims 8 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8 and 14 would be allowable for teaching that the memory cells are divided into p partitions and q-bit positions. Neither de Sandre nor Goda teach dividing the cells in such a way. Therefore, they would be allowable if written in independent form.
Claim 13 would be allowable for teaching that the sensing units comprise total current counters where the output of the current counter is a number between 0 and M. Neither Goda nor de Sandre teach counting the total current and outputting a number based on the amount of current counted. Therefore, this claim would be allowable if written in independent form.
Claims 15 and 16 would be allowable for being dependent on Claim 14.
Claim 17 would be allowable for teaching that the sensing circuits comprise logic gates that generate an output based on the output of a sensing unit sensing the current first memory cells and a sensing unit sensing the current from second memory cells. De Sandra teachings sensing units on each source line but not that the output is logically combined with that of another source line after sensing. Goda fails to teach logically combining the outputs of sensing units in this way as well. Therefore, this claim would be allowable if written in independent form.
Claim 18 would be allowable for being dependent on Claim 17.
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825