Prosecution Insights
Last updated: April 19, 2026
Application No. 18/750,206

ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITRY FOR REDUCED INTERFERENCE FROM BULK CURRENT INJECTION (BCI) NOISE

Non-Final OA §102§103
Filed
Jun 21, 2024
Examiner
BARNIE, REXFORD N
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microchip Technology Inc.
OA Round
1 (Non-Final)
11%
Grant Probability
At Risk
1-2
OA Rounds
3y 5m
To Grant
52%
With Interview

Examiner Intelligence

Grants only 11% of cases
11%
Career Allow Rate
5 granted / 46 resolved
-57.1% vs TC avg
Strong +41% interview lift
Without
With
+40.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
62 currently pending
Career history
108
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
23.0%
-17.0% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Applicant is advised that should claim 3 be found allowable, claim 11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim 10 includes all of the limitations of claims 1 and 3 (without claim 2). Claim 11, by repeating the limitations of claim 2, makes it identical to claim 3. Claim 8 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 19. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim 18 repeats the limitations of claims 1, 3 and 8 (without claim 2). But claim 19 then recites the limitations of claim 2. Claim 8 recites the exact same limitations (it depends from and includes the limitations of claims 1-3). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (US 2020/0105740). With respect to claim 1, Hsu discloses an apparatus (fig 3; par 17) comprising: an ESD protection circuitry including: a first diode (lower diode of 121) having a cathode coupled to a first signal input (I/O #1) and an anode coupled to a signal ground input (GND); a second diode (lower diodes of (312) having a cathode coupled to a second signal input (I/O #2) and an anode coupled to the signal ground input (GND); and a third diode (124) having a cathode coupled to the signal ground input (GND) and an anode coupled to a substrate ground (SOI_SUB). The scope of the claim is limited to the ESD protection circuitry, which encompasses three diodes. The named inputs are not distinctly claimed and are not part of the ESD protection circuitry. Hsu discloses the three-diode Y configuration of diodes between two signal inputs, a ground and a SOI substrate. The SOI substrate layer (see fig 1) is interpreted as a substrate ground. With respect to claim 2, Hsu discloses a substrate (See fig 1, items 103-104, the substrate ground at least part of, or coupled to, the substrate. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-6, 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Singh (US 2023/0031363). With respect to claim 2, Hsu discloses the apparatus of claim 2 and discloses that the signal inputs are connected to functional circuitry (102) disposed on the substrate but does not expressly disclose an AFE. Singh discloses an apparatus (fig 2) with first and second signal inputs (Vinp, VinM) comprising an analog front-end (106), the analog front-end including: a first analog front-end circuitry (top half of 106) coupled to the first signal input (Vinp) and the signal ground input (obvious that circuitry has a connection to ground); and a second analog front-end circuitry (bottom half of 106) coupled to the second signal input (Vinm) and the signal ground input (obvious ground). In the combination, the Singh AFE is connected to the Hsu substrate. Hsu and Singh are analogous to the claimed invention because they are from the same field of endeavor, namely data circuits. At the time of the earliest priority date of the application, it would have been obvious to one skilled in the art to combine the signal inputs taught by Hsu (with their ESD) with those taught by Singh (with their AFE). The motivation for doing so would have been to utilize the benefits of both circuits (EDS protection, analog data conditioning). With respect to claim 4, Hsu discloses an IC (fig 1, item 100, fig 3, item 300; see first sentence of par 12 and 17) including the substrate and ESD protection circuitry. In the combination, the Singh AFE would be included in the Hsu substrate as well. With respect to claim 5, Hsu discloses the IC includes a power supply input (Vdd) and a ground input (GND), the ground input having a connection in the IC to the substrate ground (through 124). With respect to claim 6, Hsu discloses the third diode (124) between ground and substrate ground, but does not expressly disclose a fourth diode. At the time of the earliest priority date of the application, it would have been obvious to one skilled in the art to duplicate diode 124 to provide an exact copy in parallel (cathode to ground, anode to substrate ground SOI_SUB). The mere duplication of parts is an obvious modification. MPEP §2144.04(VI)(B). With respect to claims 10-13, Hsu and Singh combine to disclose the recited limitations, and the references are analogous, as discussed above in the art rejections of claims 1-3 and 5-6. Claim 10 corresponds to claims 1 and 3. Claims 11-13 correspond to claims 2 and 5-6, respectively. Allowable Subject Matter Claims 7-9 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 7 and 14, the prior art does not teach or suggest the apparatus of claims 6 and 13 further comprises a switch coupled between the ground input and the substrate ground, the switch to switchably break the connection at least partially responsive to a disconnection of a ground of the power source. Regarding claims 8 and 15, the prior art does not teach or suggest the apparatus further comprises a support structure and inductive position sensor coils on, or in, the support structure, with the sensor coils being connected to the inputs as claimed. Claim 9 depends from claim 8 and claims 16-17 depend from claim 15. Claims 18-25 are allowed. Claim 18 is allowable for the same reason as claim 8. Claims 19-25 depend from claim 18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADI AMRANY whose telephone number is (571)272-0415. The examiner can normally be reached Monday - Friday, 8am-7pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rex Barnie can be reached at 5712722800 x36. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADI AMRANY/Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Jan 27, 2026
Non-Final Rejection — §102, §103 (current)

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Granted
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
11%
Grant Probability
52%
With Interview (+40.9%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allow rate.

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