DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-11 and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JENG et al. (US Patent Appl. Pub. No. 2020/0098693 A1).
[Re claim 10] JENG discloses the semiconductor package comprising: a redistribution structure (610) comprising redistribution lines (612) and redistribution vias (612 located in through holes 611a); a first semiconductor chip (130F) on the redistribution structure (610); a conductive post (570) separated from the first semiconductor chip (130F) in a horizontal direction and on the redistribution structure (610); a first molding layer (560) surrounding the first semiconductor chip (130F) and the conductive post (570) in the horizontal direction and on the redistribution structure; conductive pillars (135) on a lower surface of the first semiconductor chip (130F), the conductive pillars (135) respectively metal-metal-bonded to uppermost portions of some of the redistribution vias (612 located in through holes 611a); and an insulating material layer (590) surrounding sidewalls of the conductive pillars (135) (see figure 5A-5F and paragraph [0102]-[0111]).
[Re claim 11] JENG discloses the semiconductor package wherein lower surfaces of the conductive pillars (135) are coplanar with a lower surface of the insulating material layer (590) (see figure 5E).
[Re claim 14] JENG discloses the semiconductor package wherein the redistribution vias (612 located in through holes 611a) each have a tapered shape in which a length in the horizontal direction increases as a distance from the first semiconductor chip (130F) increases (see figure 5F).
[Re claim 15] JENG discloses the semiconductor package further comprising: a connection terminal (640) on the conductive post (570); and a second semiconductor chip (630) on the first semiconductor chip (130F) and connected to the conductive post (570), wherein the first semiconductor chip (130F same as chip 130A) is a logic chip and the second semiconductor chip (630 same as 440) is a memory (see figure 6 and paragraph [0023], [0092], [0106], [0119]-[0121]).
[Re claim 16] JENG discloses the semiconductor package further comprising an underfill layer (650) between the first semiconductor chip (130F) and the second semiconductor chip (630) and surrounding the connection terminal (640) (see figure 6 and paragraph [0119]-[0120]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over JENG et al. (US Patent Appl. Pub. No. 2020/0098693 A1) in view of Yu et al. (US Patent Appl. Pub. No.2018/0323150 A1).
[Re claim 12] JENG discloses the device as claimed and rejected in claim 10, but JENG does not disclose the semiconductor package wherein the insulating material layer comprises at least one from among SiO2, SiC, SiON, SiOC, SiCN, SiN, and SiOCN. Yu discloses the semiconductor package wherein the insulating material layer (110) comprises at least one from among SiO2, SiC, SiON, SiOC, SiCN, SiN, and SiOCN (see figure 1 and paragraph [0016]). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating material layer comprises at least one from among SiO2, SiC, SiON, SiOC, SiCN, SiN, and SiOCN in the device of JENG in order to protect the die connectors.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over JENG et al. (US Patent Appl. Pub. No. 2020/0098693 A1) in view of SEO et al. (US Patent Appl. Pub. No.2021/0320077 A1).
[Re claim 17] JENG discloses the device as claimed and rejected in claim 10, but JENG does not disclose the semiconductor package further comprising a second molding layer on the first molding layer and surrounding the second semiconductor chip. SEO discloses the semiconductor package further comprising a second molding layer (730) on the first molding layer and surrounding the second semiconductor chip (720) (see figure 6A and paragraph [0108]). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second molding layer surrounding the second semiconductor chip in the device of JENG in order to protect the semiconductor chip.
[Re claim 18] SEO also discloses the semiconductor package wherein the conductive pillars (150) comprise a plurality of layers (151 and 155) (see figure 1D and paragraph [0033]-[0035]).
Allowable Subject Matter
Claim 13 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-9 and 20 are allowed.
The following is an examiner's statement of reasons for allowance: Claim 1 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of bonding the first semiconductor chip to the metal pad by using a connection terminal; forming a first molding layer surrounding the first semiconductor chip; removing the connection terminal and the metal pad; and forming a redistribution structure connected to the conductive pillar. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
The following is an examiner's statement of reasons for allowance: Claim 20 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of bonding the conductive pillar to the metal pad by performing a solder reflow process by using a connection terminal between the conductive pillar and the metal pad; forming a first molding layer surrounding the first semiconductor chip; planarizing an upper surface of the first molding layer; removing the connection terminal and the metal pad by performing a planarization process; and forming a redistribution structure that is metal-metal-bonded to the conductive pillar. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-9 depend from claim 1 so they are allowable for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817
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