Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. This office action is responsive to communication(s) filed on 4/3/2026.
2. Newly added claims 2-21 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
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4. Claims 2-21 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 7-8 and 14 of U.S. Patent No. 10998080. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 2, 5 and 9 of the examined application are anticipated and the same scope of invention by claim 14 of the reference such as a memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
The claims 3-4, 11-12 and 19-20 of examined application are obvious over the claims of reference 14 because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites modify one or more parameters of the set of one or more access operations while in the reference is silent. However, a claim 22 of the U.S. Patent No. 11217303 disclose this limitation.
Claims 6-8 are obvious to claims 6-8 of the reference.
Claims 10 and 13-17 of the examined application are anticipated and the same scope of invention by claim 1 and6-8 of the reference such as an method, comprising: determining to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and applying to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
The claims 18 and 21 of examined application are obvious over the claims of reference 14 because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites comprising instructions which, when executed by one or more processors of an electronic device while in the reference is silent. However, a claim 17 of the U.S. Patent No. 11557371 or a claim 19 the U.S. Patent No. 12040038 disclose this limitation.
5. Claims 2-21 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 8-9, 18, 22 and 25 of U.S. Patent No. 11217303. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 2-16 of the examined application are apparatus claims but they encompass the same scope of invention as to that of method claims 1, 8-9, 14, 18, 22 and 25 of the reference.
Claims 2-5, 9-13, and 17 of the examined application are anticipated and the same scope of invention by a claim 22 of the reference such as a memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
Claims 6-8 and 14-16 are obvious to claims 14, 18 and 25 of the reference.
The claims 18 and 21 of examined application are obvious over the claims of reference 14 because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites comprising instructions which, when executed by one or more processors of an electronic device while in the reference is silent. However, a claim 17 of the U.S. Patent No. 11557371 or a claim 19 the U.S. Patent No. 12040038 disclose this limitation.
Claims 19-20 are obvious to a claim 22 of the reference.
6. Claims 2-21 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-6 and 13-17 of U.S. Patent No. 11557371. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 2 and 5-9 of the examined application are anticipated and the same scope of invention by claims 13-16 of the reference such as a memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
The claims 3-4, 11-12 and 19-20 of examined application are obvious over the claims of reference 14 because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites modify one or more parameters of the set of one or more access operations while in the reference is silent. However, a claim 22 of the U.S. Patent No. 11217303 disclose this limitation.
claims as follows:
Claims 10 and 13-17 of the examined application are anticipated and the same scope of invention by claims 1 and 3-8 of the reference such as a method, comprising: determining to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and applying to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
Claims 18 and 21 of the examined application are anticipated and the same scope of invention by a claim 17 of the reference such as a non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure is to increase an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
7. Claims 2-21 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-6 and 13, 17-19 of U.S. Patent No. 12040038. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 2 and 5-9 of the examined application are anticipated and the same scope of invention by claims 13 and 17-18 of the reference such as a memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
The claims 3-4, 11-12 and 19-20 of examined application are obvious over the claims of reference 14 because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites modify one or more parameters of the set of one or more access operations while in the reference is silent. However, a claim 22 of the U.S. Patent No. 11217303 disclose this limitation.
claims as follows:
Claims 10 and 13-17 of the examined application are anticipated and the same scope of invention by claims 1 and 5-7 of the reference such as a method, comprising: determining to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure increases an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and applying to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
Claims 18 and 21 of the examined application are anticipated and the same scope of invention by a claim 19 of the reference such as a non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to: determine to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states, wherein the imprint recovery procedure is to increase an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; and apply to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more access operations to increase the ability of the memory cell to switch between storing the first logic state of the set of logic states and storing the second logic state of the set of logic states.
Response to Arguments
8. Applicant's arguments with respect to the newly added claims have been considered but are moot in view of the new ground(s) of rejections as set forth in the rejection above.
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). See MPEP 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
10. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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