DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 9/10/2026 have been fully considered but they are not persuasive.
As to Applicant’s argument that “Stecklina therefore describes delivery of each decrypted instruction directly to a processor core for execution, not storage of the decrypted instruction in an internal volatile memory (Remarks, p. 7), the Examiner respectfully disagrees. Stecklina does not send the decrypted instruction directly to the processor core for execution. Stecklina “uses an intermediate data storage, for example, such as a register” (Stecklina, [0072]). Registers are volatile memory by definition and Maximov, [0026]. The volatile storage/register is internal to the trusted execution environment (Maximov, [0026]). Therefore, the rejection is maintained.
As to Applicant’s argument that “Maximov does not describe storing decrypted program code, or even individual program instructions, in that volatile storage” (Remarks, p. 7), the Examiner respectfully disagrees. Stecklina stores individual decrypted instructions in a register (volatile memory and intermediate data storage) (Stecklina, [0072]). Therefore, the rejection is maintained.
As to Applicant’s argument that the “cited disclosures do not provide the two claimed operating states” (Remarks, p. 8), the Examiner respectfully disagrees. The Examiner uses the broadest reasonable interpretation of the claim language. The Specification defines the configuration state as “to receive the encrypted program code from the memory, to decrypt it by means of the crypto function unit and to verify the integrity and/or authenticity of the decrypted program code and to store is in the internal volatile memory” (Specification, [0004]). This is what Stecklina as modified teaches (Stecklina, [0072] and Maximov, [0026]). The cited references have two operating states: decryption of the encrypted instruction and execution of the decrypted instruction. The decryption state prepares the instruction for execution (configuration state) and executing the decrypted instruction (execution state). The decryption only happens after execution of the previous instruction (Stecklina, [0073-0074]). Therefore, the rejection is maintained.
As to Applicant’s argument that “put simply, there are not two distinct data paths in Stecklina, and Maximov does not suggest any such data paths either” (Remarks, p. 8), the Examiner respectfully disagrees. There are three distinct data paths described in prior art references: the path from the program memory to the decryption unit, the path from the decryption unit to intermediate storage (register) and the path from the intermediate storage (register) to the processor core (Stecklina, [0072]). While there is no explicit path selection circuit, the instruction by instruction processing closes (interrupts) the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]). Therefore, the rejection is maintained.
As to Applicant’s argument that “Stecklina still transfers decrypted instructions from the decryption unit to the processor core rather the storing them in the claimed internal volatile memory” (Remarks, p. 10), the Examiner respectfully disagrees. Stecklina “uses intermediate data storage” between the decryption of an instruction and subsequent execution of the decrypted instruction (Stecklina, [0073-0074]). Therefore, the rejection is maintained.
As to Applicant’s argument that “an absence of disclosed reverse communication does not affirmatively disclose the particular first path recited in claim 4 is unidirectional (Remarks, p. 10), the Examiner respectfully disagrees. The instructions themselves are not modified, other than being decrypted. There is no need of a bidirectional communication path. There is no re-encryption of the instructions. The path of Stecklina is one-way: sending encrypted instructions for decryption, decrypting the encrypted instructions, send decrypted instructions, storing decrypted instructions in a intermediate register, sending the decrypted instructions to the processor for execution (Stecklina, [0073-0074]). There is no reason to reverse the communication path. Therefore, the rejection is maintained.
As to Applicant’s argument that “the fact that a cryptoprocessor performs authentication or attestation does not disclose authenticated encryption or authenticated encryption with associated data (Remarks, p. 11), the Examiner respectfully disagrees. “Authentication (a process to prove the identity attribute of an entity, i.e. the secure cryptoprocessor acting as the integrity reporting entity) and attestation (a process that enables the software integrity state to be reported and verified in order to determine its trustworthiness) are some steps that might be performed to ensure trusted computing” (Maximov, [0029]). The secure crypto-processor protects against any malicious intent and provides a root of trust. Therefore, the rejection is maintained.
As to Applicant’s argument that “Rosenthal’s reference values therefore verify the encrypted and compressed protected program as stored, not the decrypted program code” (Remarks, p. 12), the Examiner respectfully disagrees. The Armor program is used to determine corruption or a virus is present in the code. “If code was compressed and encrypted, it is read from the disk and decompressed and decrypted in block 116 and loaded into the portion of memory previously occupied by Armor…Armor can then decrypt the code…Finally, Armor returns control to Run Armor, passing a return code indicating that no corruption was detected and no errors occurred” (Rosenthal, 14:1-34). It is clear that Armor looks at the decrypted, decompressed code to determine if any corruption is present in the decrypted, decompressed code. Therefore, the rejection is maintained.
As to Applicant’s argument that “those disclosures do not identify the particular two-area arrangement required by claim 12” (Remarks, p. 12), the Examiner respectfully disagrees. Powell’s tamper-resistant security module protects the whole device, not a portion of the device (Powell, [0033]). This is an improvement of only protecting a certain area. The claimed limitation leaves processing device less secure. Therefore, the rejection is maintained.
Newly added claim 14 is addressed below in the Response to Amendment section.
Response to Amendment
Claim 14 has been added.
Claims 1-14 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub. No. 2019/0384894 to Stecklina et al. (hereinafter Stecklina) in view of US PG Pub. No. 2021/0374262 Maximov et al. (hereinafter Maximov).
As to claim 1, Stecklina teaches an electronic data processing device comprising:
a. A memory configured to store encrypted program code for a cryptographic algorithm (memory with encrypted instructions) (Stecklina, [0008-0009]).
b. A cryptoprocessor unit having a security processor, an interface to the memory (cryptoprocessor setup with non-volatile memory) (Stecklina, [0006-0010]).
Stecklina does not expressly mention a volatile memory as part of the cryptoprocessor setup). However, in an analogous art, Maximov teaches an internal volatile memory and a crypto function circuit (cryptoprocessor has volatile memory) (Maximov, [0026]).
Therefore, one of ordinary skill in the art before the effective filing date of the instant invention would have been motivated to implement the cryptoprocessor of Stecklina with the use of internal volatile memory of Maximov in order to better protect the contents of the memory when the cryptoprocessor is rebooted or powered down as suggested by Maximov (Maximov, [0026]).
Stecklina as modified further teaches:
c. A data processing circuit having an interface to the cryptoprocessor unit (Stecklina, [0006-0010]), wherein the cryptoprocessor unit is configured:
i. In a configuration state, to receive the encrypted program code from the memory, to decrypt it by means of the crypto function circuit and to verify the integrity and/or authenticity of the decrypted program code and to store it in the internal volatile memory (each encrypted instruction is individually decrypted sent to the cryptoprocessor for execution using intrinsic code attestation (ICA) to protect the instructions from manipulation) (Stecklina, [0009 and 0073-0074]).
ii. In an execution state, to execute the decrypted program code by means of the security processor and at least partially by means of the crypto function circuit (cryptoprocessor executes decrypted instructions) (Stecklina, [0073-0074]).
d. A path selection circuit which is configured, in the configuration state, to provide a first data path from the memory, via the crypto function circuit, to the internal volatile memory of the cryptoprocessor unit and, in the execution state, to interrupt the first data path and to provide a second data path between the security processor and the internal volatile memory and the crypto function circuit (Instructions are processed instruction by instruction, the decryption unit decrypts a first instruction and then sends the plaintext instruction for execution. No encrypted instruction is decrypted until the previous instruction has been decrypted. While there is no explicit path selection circuit, the instruction by instruction processing closes the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]).
As to claim 2, Stecklina as modified teaches the path selection circuit is configured to interrupt the second data path in the configuration state (Nothing is sent to processor while the decryption of an instruction is performed. Instructions are processed instruction by instruction; the decryption unit decrypts a first instruction and then sends the plaintext instruction for execution. No encrypted instruction is decrypted until the previous instruction has been decrypted. While there is no explicit path selection circuit, the instruction by instruction processing closes the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]).
As to claim 3, Stecklina as modified teaches the security processor has no read access and no write access to the internal volatile memory in the configuration state (security processor only has access to the processor when a plaintext instruction is sent for execution) (Stecklina, [0073-0074]).
As to claim 4, Stecklina as modified teaches the first data path is unidirectional (there is no mention of sending any data from the security processor to memory with the encrypted instructions) (Stecklina, [0073-0074]). It is also noted that there are only 2 options for the direction of communications: unidirectional and bidirectional and is viewed as an obvious variation.
As to claim 5, Stecklina as modified teaches the security processor has no access to the crypto function circuit in the configuration state (only plaintext instructions are sent to the processor for execution) (Stecklina, [0073-0074]).
As to claim 6, Stecklina as modified teaches the data processing circuit has no access to the crypto function circuit and the internal volatile memory of the cryptoprocessor unit in the execution state (the data processing circuit only receives the data word (part of the decryption key) it does not have access to the cryptofunction unit) (Stecklina, [0073-0074]).
As to claim 7, Stecklina as modified teaches the path selection circuit has a first path selection circuit which is configured to establish a connection between the data processing circuit and the crypto function circuit in the configuration state and to block it in the execution state (Nothing is sent to processor while the decryption of an instruction is performed. Instructions are processed instruction by instruction; the decryption unit decrypts a first instruction and then sends the plaintext instruction for execution. No encrypted instruction is decrypted until the previous instruction has been decrypted. While there is no explicit path selection circuit, the instruction by instruction processing closes the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]).
As to claim 8, Stecklina as modified teaches the path selection circuit has a second path selection circuit which is configured to establish a connection between the security processor and the crypto function circuit in the execution state and to block it in the configuration state (Nothing is sent to processor while the decryption of an instruction is performed. Instructions are processed instruction by instruction; the decryption unit decrypts a first instruction and then sends the plaintext instruction for execution. No encrypted instruction is decrypted until the previous instruction has been decrypted. While there is no explicit path selection circuit, the instruction by instruction processing closes the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]).
As to claim 9, Stecklina as modified teaches the path selection circuity is configured to establish a connection between the crypto function circuit and the internal volatile memory in the execution state (Nothing is sent to processor while the decryption of an instruction is performed. Instructions are processed instruction by instruction; the decryption unit decrypts a first instruction and then sends the plaintext instruction for execution. No encrypted instruction is decrypted until the previous instruction has been decrypted. While there is no explicit path selection circuit, the instruction by instruction processing closes the path to the decryption circuit until the previous instruction is decrypted and then the plaintext instruction is executed by the processor and only takes the next instruction (closing the path) when the previous instruction has been executed.) (Stecklina, [0073-0074]).
As to claim 11, Stecklina as modified teaches the crypto function circuit is an authenticated encryption module or an authenticated encryption with associated data module (secure cryptographic module runs in a trusted execution environment and is authenticated) (Maximov, at least [0029]).
As to claim 13, Stecklina as modified teaches the cryptoprocessor unit is a secure enclave of the electronic data processing device (enclaves are used to protect circuits) (Maximov, [0027]).
As to claim 14, Stecklina as modified teaches the second data path extends from the security process, via the crypto function circuit, to the internal volatile memory (after decryption, the plaintext instruction is sent to the register (Stecklina, [0073-0074]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub. No. 2019/0384894 to Stecklina et al. (hereinafter Stecklina) in view of US PG Pub. No. 2021/0374262 Maximov et al. (hereinafter Maximov) as applied to claim 1 above, and further in view of US Patent No. 5,359,659 to Rosenthal.
As to claim 10, Stecklina as modified does not expressly mention a test value. However, in an analogous art, Rosenthal teaches the memory is configured to store a test value of the decrypted program code and the cryptoprocessor unit is configured to verify the integrity and/or authenticity of the decrypted program code based on the test value (a checksum is used to detect alterations in program code) (Rosenthal, 1:49-64).
Therefore, one of ordinary skill in the art before the effective filing date of the instant invention would have been motivated to implement the cryptoprocessor of Stecklina as modified with the use of checksum calculations in order to detect any alterations in the program code as suggested by Rosenthal (Rosenthal, 1:49-64).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over US PG Pub. No. 2019/0384894 to Stecklina et al. (hereinafter Stecklina) in view of US PG Pub. No. 2021/0374262 Maximov et al. (hereinafter Maximov) as applied to claim 1 above, and further in view of US PG Pub. No. 2013/0212026 to Powell et al. (hereinafter Powell).
As to claim 12, Stecklina as modified does not expressly mention protections against physical attacks. However, in an analogous art, Powell teaches the cryptoprocessor unit belongs to a first area of the data processing device which is more strongly protected against physical attacks than a second area, to which the data processing circuit and the memory belong (employing a tamper-resistant security module which may include hardened casing at varying levels of protection) (Powell, [0033]).
Therefore, one of ordinary skill in the art before the effective filing date of the instant invention would have been motivated to implement the cryptoprocessor of Stecklina as modified with the use of tamper-resistant security modules of Powell in order to protect against physical attacks as suggested by Powell (Powell, [0033]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM S POWERS whose telephone number is (571)272-8573. The examiner can normally be reached M-F 7:30-17:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jorge L Ortiz-Criado can be reached at (571) 272-7624. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM S POWERS/Primary Examiner, Art Unit 2496
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