Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
As to Applicant’s arguments regarding Chaiken and the independent claims, those arguments are moot because the Morgan reference has been added to teach those features. Applicant’s arguments that regarding support for the amendments to the independent claims is unpersuasive. The examiner asserts that the original disclosure does not convey to a person of ordinary skill in the art that, at the time the application was filed, the inventors had possession of the claimed invention as amended. Paragraph 0039 does not sufficiently describe the claimed process as amended such that a person of ordinary skill in the art would think the inventors, at the time the application was filed, had possession of the claimed invention as amended.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is insufficient support in the original disclosure for the central processing unit executing the advanced memory test routine to perform either a hard post package repair (PPR) or a soft PPR to substitute a spare memory module for a memory module failing the test of the advanced memory test routine. Paragraph 0039 does not sufficiently describe such a process such that a person of ordinary skill in the art would think, at the time the application was filed, the inventors had possession of the claimed invention as amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 7-10, 11, 13, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable Chaiken in view of Tian (US 20140129821 A1) and Morgan (US 20160307647 A1).
As to claim 1, Chaiken teaches a computer system comprising:
a basic input output system (BIOS) including an advanced memory test routine (see paragraph 0062);
a volatile memory having a plurality of memory modules (see fig. 1 and paragraphs 0040 and 0052);
a non-volatile memory (see fig. 1 and paragraph 0052, 0055); and
a central processing unit coupled to the memory and the BIOS (see Fig. 1), the central processing unit executing the advanced memory test routine stored in the BIOS (See paragraph 0093, disclosing that a boot firmware can perform the tests and paragraph 0062, disclosing that boot firmware can be implemented as a BIOS) to test the memory modules of the volatile memory (see Figs. 2, 3, paragraphs 0040 and 97-104), and wherein test result data from the advanced memory test routine is stored in the non-volatile memory (see Fig. 3, step 260 and corresponding text).
Chaiken does not explicitly teach a baseboard management controller (BMC) coupled to the non-volatile memory; or that the test result data from the advanced memory test routine is transmitted to the BMC and stored in the non-volatile memory by the BMC.
However, Tian teaches a BMC with a memory (see figs. 1 and 2, elements 40 and 404) and sending state signals that indicate normal or malfunctions to the BMC and the BMC storing information of those results in its memory (see paragraphs 0012-0015).
The references do not explicitly teach that the memory of the BMC is non-volatile, but Chaiken does teach the use of non-volatile memory.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the concept of using non-volatile memory in the BMC because it allows data to be stored across power cycles/loss.
Chaiken does not explicitly teach the central processing unit executing the advanced memory test routine to perform either a hard post package repair (PPR) or a soft PPR to substitute a spare memory module for a memory module failing the test of the advanced memory test routine.
However, Morgan teaches hard and soft PPR that remaps address from defective memory to non-defective memory (see paragraphs 0017-0019).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the methods of Morgan because it helps to improve overall yield and to reduce cost (see paragraph 0017). It also prevents a reduction in usable memory by replacing defective memory areas.
As to claim 3, the references teach claim 2 as detailed above. They further teach the non-volatile memory is a flash memory (see Chaiken paragraph 0060) and wherein the BMC stores the test result data to a system error log (see Tian paragraphs 0012 and 0015, disclosing a BMC storing test results; the examiner is intercepting the collection of status information in the BMC memory as corresponding to the claimed “system error log” which is not described in detail and therefore broad enough to correspond to the collection of status information).
As to claim 5, the references teach claim 1 as referenced above. Chaiken further teaches the volatile memory includes a plurality of memory modules, and wherein the advanced memory test routine includes an option to test a subset of the plurality of memory modules (see paragraph 0101 disclosing a bit that determines if a page of volatile memory will be tested or not).
As to claim 8, the references teach claim 5 as referenced above. The references further teaches the execution of the advanced memory test routine includes repairing any memory modules failing the advanced memory test (see Chaiken Fig. 2, step 290 and above cited portions of Morgan).
As to claim 9 the references teach claim 1 as referenced above. Chaiken further teaches the computer system is a server (See paragraph 0045).
As to claim 10, the references teach claim 1 as referenced above. Chaiken further teaches the test result data is stored prior to booting an operating system for the central processing unit (see Figs. 2 and 3 performed in pre-boot environment, paragraph 0093, disclosing that a boot firmware can perform the Figs. 2 and 3 and paragraph 0062, disclosing that boot firmware can be implemented as a BIOS).
As to claim 11, Chaiken teaches a method of testing volatile memory in a computer system, the method comprising:
configuring a basic input output system (BIOS) to execute an advanced memory test routine in the computer system (See paragraph fig. 2, 3, and paragraphs 0040, 0052, 0093, disclosing that a boot firmware can perform the tests of figs. 2 and 3 and paragraph 0062, disclosing that boot firmware can be implemented as a BIOS);
running a power on self-test routine of the BIOS to execute the advanced memory test routine to test a volatile memory (See paragraph fig. 2, 3, and paragraphs 0040, 0052, 0093, disclosing that a boot firmware can perform the tests of figs. 2 and 3 on volatile memory and paragraph 0062, disclosing that boot firmware can be implemented as a BIOS); and storing test result data from the advanced memory test routine in a non-volatile memory (see Figs. 2, 3, paragraphs 0040 and 97-104), and wherein test result data from the advanced memory test routine is stored in the non-volatile memory (see Fig. 3, step 260 and corresponding text).
Chaiken does not explicitly teach transmitting the test result data from the advanced memory test routine to a baseboard management controller (BMC) coupled to a non-volatile memory;and storing test result data from the advanced memory test routine in a non-volatile memory by the BMC.
However, Tian teaches a BMC with a memory (see figs. 1 and 2, elements 40 and 404) and sending state signals that indicate normal or malfunctions to the BMC and the BMC storing information of those results in its memory (see paragraphs 0012-0015).
The references do not explicitly teach that the memory of the BMC is non-volatile, but Chaiken does teach the use of non-volatile memory.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the concept of using non-volatile memory in the BMC because it allows data to be stored across power cycles/loss.
Chaiken does not explicitly teach executing the advanced memory test routine to perform either a hard post package repair (PPR) or a soft PPR to substitute a spare memory module for a memory module failing the test of the advanced memory test routine.
However, Morgan teaches hard and soft PPR that remaps address from defective memory to non-defective memory (see paragraphs 0017-0019).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the methods of Morgan because it helps to improve overall yield and to reduce cost (see paragraph 0017). It also prevents a reduction in usable memory by replacing defective memory areas. It also prevents a reduction in usable memory by replacing defective memory areas.
As to claim 13, the references teach claim 12 as detailed above. They further teach the non-volatile memory is a flash memory (see Chaiken paragraph 0060) and wherein the BMC stores the test result data to a system error log (see Tian paragraphs 0012 and 0015, disclosing a BMC storing test results; the examiner is intercepting the collection of status information in the BMC memory as corresponding to the claimed “system error log” which is not described in detail and therefore broad enough to correspond to the collection of status information).
As to claim 15, the references teach claim 11 as referenced above. Chaiken further teaches the volatile memory includes a plurality of memory modules, and wherein the advanced memory test routine includes an option to test a subset of the plurality of memory modules (see paragraph 0101 disclosing a bit that determines if a page of volatile memory will be tested or not).
As to claim 18, the references teach claim 15 as referenced above. Chaiken further repairing any memory modules of the plurality of memory modules that fail the advanced memory test via executing the advanced memory test (see Chaiken Fig. 2, step 290 and above cited portions of Morgan).
As to claim 19, the references teach claim 11 as referenced above. Chaiken further teaches the computer system is a server (See paragraph 0045).
As to claim 20, the references teach claim 11 as referenced above. Chaiken further teaches booting an operating system for the computer system, wherein the test result data is stored prior to booting the operating system (see Figs. 2 and 3 performed in pre-boot environment, paragraph 0093, disclosing that a boot firmware can perform the Figs. 2 and 3 and paragraph 0062, disclosing that boot firmware can be implemented as a BIOS).
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable Chaiken, Tian, and Morgan in view of Chen (US 20120011402 A1).
As to claim 4, the references teach claim 3 as detailed above. They do not explicitly teach test result data stored on the system error log is accessible via an Intelligent Platform Management Interface (IPMI) command.
However, Chen teaches supporting IPMI (see throughout) and transmitting test results (see paragraph 0034).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Chaiken with the methods of Chen because it enables full-life-cycle testing including before an OS is loaded (see Summary and paragraph 0015).
As to claim 14, the references teach claim 13 as detailed above. They do not explicitly teach that test result data stored on the system error log is accessible via an Intelligent Platform Management Interface (IPMI) command.
However, Chen teaches supporting IPMI (see throughout) and transmitting test results (see paragraph 0034).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine Chaiken with the methods of Chen because it enables full-life-cycle testing including before an OS is loaded (see Summary and paragraph 0015).
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable Chaiken, Tian, and Morgan in view of Park (US 11899959 B2).
As to claim 6, the references teach claim 5 as referenced above. They do not explicitly teach the advanced memory test routine is executed again after a replacement of at least one of the plurality of memory modules of the volatile memory, wherein the advanced memory test routine is only executed for the replaced at least one of the plurality of memory modules.
However, Park teaches repairing memory by replacing failed cells and then re-testing the failed cells (see column 4, lines 11-43, also see claim 13).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the methods of Park because it allows improved reliability and reduced test time (see abstract).
As to claim 16, the references teach claim 15 as referenced above. They do not explicitly teach executing the advanced memory test routine again after a replacement or at least one of the plurality of memory modules of the volatile memory, wherein the advanced memory test routine is only executed for the replaced at least one of the plurality of memory modules.
However, Park teaches repairing memory by replacing failed cells and then re-testing the failed cells (see column 4, lines 11-43, also see claim 13).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with the methods of Park because it allows improved reliability and reduced test time (see abstract).
Conclusion
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/JASON B BRYAN/ Primary Examiner, Art Unit 2114