DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/19/2026 has been entered.
Response to Amendment
The office action is responding to the amendments filed on 01/13/2026. Claims 1, 8 and 15 have been amended. Claims 1-15 are subject to examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bronson et al. [US 2015/0058569 A1] in view of CHACHAD et al. [US 2020/0371934 A1] and in further view of HIJAZ [US 2019/0087344 A1].
Claim 1 is rejected over Bronson, CHACHAD and HIJAZ.
Bronson teaches “A method for cache coherency management in a multi-level coherent system, comprising:” as “Embodiments include a method and computer program product for a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer.” [¶0005 and Fig. 2]
“for occurrence of a conflict eviction from a set of a cache at a first level from the multi-level coherent system: selecting a victim line from the set of the cache for eviction;” as “The NIC directory and highest-level cache act to capture and track data that is evicted from the lower-level caches to maintain an inclusive cache management policy” [¶0023]
“for the victim line being dirty and a second level from the multi-level coherent system having a copy of the victim line:” as “The highest-level cache that is used in conjunction with the NIC directory may track evictions from the lower-level cache, regardless of whether the data in the evicted line has been modified or not, and also commonly shared lines to enable fast intervention to other processor nodes in the SMP.” [¶0024]
Bronson does not explicitly teach writing dirty data of the victim line to a third level from the multi-level coherent system using a cache maintenance operation configured to write the dirty data of the victim line to the third level without execution of a snoop filter update;
silently dropping the victim line without notification to the third level.
However, CHACHAD teaches “writing dirty data of the victim line from the first level to a third level from the multi-level coherent system using a cache maintenance operation configured to write the dirty data of the victim line to the third level” as “When the L2 controller 320 receives a snoop transaction or a read or write transaction occurs from the L3 controller 310 to the L2 controller 320, the L2 controller 320 first checks the shadow L1 main and shadow L1 victim caches 326, 328. If a match is found (e.g., a hit), then the L2 controller 320 initiates a snoop transaction to the L1 controller 310.” [¶0089]
“without execution of a snoop filter update;” as “the opcode mapping logic 1106 also maps non-coherent non-allocating reads to a read command without snoop.” [¶0124]
Bronson and CHACHAD are analogous arts because they teach cache coherence and multi-level cache.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Bronson and CHACHAD before him/her, to modify the teachings of Bronson to include the teachings of CHACHAD with the motivation of writing that miss the main cache are sent to L2 cache subsystem without allocating space in the L1 main cache. [CHACHAD, ¶0055]
The combination of Bronson and CHACHAD does not explicitly teach silently dropping the victim line without notification to the third level.
However, HIJAZ teaches “silently dropping the victim line without notification to the third level.” as “Silently dropping the clean data may be accomplished by removal and/or invalidation of the date of the cache line 302 in the higher level cache memory 300 without sending the clean data to the lower level cache memory 320” [¶0071]
Bronson, CHACHAD and HIJAZ are analogous arts because they teach cache coherence and multi-level cache.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Bronson, CHACHAD and HIJAZ before him/her, to modify the teachings of combination of Bronson and CHACHAD to include the teachings of HIJAZ with the motivation of cache lines with clean data to reduce and/or avoid clean evictions of the cache line in a cache memory hierarchy by maintaining the cache line with clean data in an inclusive mode and maintaining the cache line with dirty data in an exclusive mode. [HIJAZ, ¶0039]
Claim 2 is rejected over Bronson, CHACHAD and HIJAZ.
Bronson teaches “wherein the second level is a level that is directly lower than the first level.” as [Fig. 2] (Fig. 2 shows the cache hierarchy of multi-level cache)
Claim 3 is rejected over Bronson, CHACHAD and HIJAZ.
Bronson teaches “wherein the third level is a level that is directly higher than the first level.” as [Fig. 2] (Fig. 2 shows the cache hierarchy of multi-level cache)
Claim 4 is rejected over Bronson, CHACHAD and HIJAZ.
Bronson teaches “wherein the selecting the victim line from the set of the cache for eviction comprises: searching for lines that are dirty and for which the second level has a copy; and” as “ In block 401, the following entry types are installed in the L4 cache: L3 fetches that miss in the L4 and NIC directories; L3 exclusive evictions or castouts (based on, for example, L3 least recently used, or LRU replacement policy) that hit in the NIC directory; and L3 read-only shared LRU castouts that hit in NIC directory and is a final copy of data” [¶0030]
The combination of Bronson and CHACHAD does not explicitly teach for the lines that are dirty and for which the second level has a copy being found from the searching, selecting the victim line from the found lines that are dirty and for which the second level has a copy.
However, HIJAZ teaches “for the lines that are dirty and for which the second level has a copy being found from the searching, selecting the victim line from the found lines that are dirty and for which the second level has a copy.” as “The cache memory controller may be configured to analyze the dirty indicator for the cache line 302 in response to an eviction of the cache line 302 from the higher level cache memory 300. The cache memory controller may determine that the eviction is a clean eviction in response to determining that the dirty indicator for the cache line 302 indicates that the data of the cache line 302 is not dirty, or is clean.” [¶0071]
Claim 5 is rejected over Bronson, CHACHAD and HIJAZ.
The combination of Bronson and CHACHAD does not explicitly teach wherein the selecting the victim line from the set of the cache for eviction comprises: searching for lines that are clean or for which the second level does not have a copy; and for the lines that are clean or for which the second level does not have a copy being found from the searching, selecting the victim line from the found lines that are clean or for which the second level does not have a copy.
However, HIJAZ teaches “wherein the selecting the victim line from the set of the cache for eviction comprises: searching for lines that are clean or for which the second level does not have a copy; and for the lines that are clean or for which the second level does not have a copy being found from the searching, selecting the victim line from the found lines that are clean or for which the second level does not have a copy.” as “Maintaining the victim cache line in the lower level cache memory may include keeping a copy of the victim cache line candidate of the higher level cache memory in the lower level cache memory. To keep the copy of the victim cache line candidate in the lower level cache memory, the processing device may not evict, remove, and/or invalidate the cache line from the lower level cache memory.” [¶0187]
Claim 6 is rejected over Bronson, CHACHAD and HIJAZ.
The combination of Bronson and CHACHAD does not explicitly teach wherein the selecting the victim line from the set of the cache for eviction comprises: searching for lines that are clean and for which the second level has a copy; and
for the lines that are clean and for which the second level has a copy being found from the searching, selecting the victim line from the lines that are clean and for which the second level has a copy.
However, HIJAZ teaches “wherein the selecting the victim line from the set of the cache for eviction comprises: searching for lines that are clean and for which the second level has a copy; and” as “the dirty indicator 904 may be a 1 bit binary indicator for which a “0” value may indicate a clean data for the cache line 902 and a “1” value may indicate a dirty data for the cache line 902.” [¶0125]
“for the lines that are clean and for which the second level has a copy being found from the searching, selecting the victim line from the lines that are clean and for which the second level has a copy.” as “In response to determining that the hit counter of the victim cache line in the lower level cache memory does not equal or exceed the inclusion mode threshold (i.e., determination block 710=“No”), the processing device may reset the victim cache line inclusion mode indicator in the lower level cache memory in block 714.” [¶0116]
Claim 7 is rejected over Bronson, CHACHAD and HIJAZ.
The combination of Bronson and CHACHAD does not explicitly teach for the victim line not being dirty or for the second level from the multi-level coherent system not having a copy of the victim line, executing another eviction process.
However, HIJAZ teaches “for the victim line not being dirty or for the second level from the multi-level coherent system not having a copy of the victim line, executing another eviction process.” as “FIG. 9B illustrates the example system configured to relax exclusivity requirements with a cache memory hierarchy in which a cache line (A) 902a from another memory may be written to the higher level cache memory 300 and to the lower level cache memory 320, and a cache line (B) 902b from the other memory may be written the higher level cache memory 300.” [¶0145]
Claim 8 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 1.
Claim 9 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 2.
Claim 10 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 3.
Claim 11 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 4.
Claim 12 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 5.
Claim 13 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 6.
Claim 14 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 7.
Claim 15 is rejected over Bronson, CHACHAD and HIJAZ under the same rationale of rejection of claim 1.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MASUD K KHAN/Primary Examiner, Art Unit 2132