Prosecution Insights
Last updated: April 19, 2026
Application No. 18/750,461

DIFFERENTIAL DIGITAL-TO-ANALOG CONVERTER

Non-Final OA §112
Filed
Jun 21, 2024
Examiner
LAUTURE, JOSEPH J
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
96%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
722 granted / 761 resolved
+26.9% vs TC avg
Minimal +1% lift
Without
With
+0.8%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
8 currently pending
Career history
769
Total Applications
across all art units

Statute-Specific Performance

§101
5.0%
-35.0% vs TC avg
§103
36.3%
-3.7% vs TC avg
§102
35.1%
-4.9% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 761 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The application has not been checked to the extent necessary to determine the presence of all possible typographical and grammatical errors. Applicant’s cooperation is requested in correcting any errors of which he/she may become aware in the application. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 on line 15 recites the limitation “the first subset of the set of digital circuits”. There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites on line 18 the limitation “the second subset of the set of digital circuits”. There is insufficient antecedent basis for this limitation in the claim. Claim 8 recites on line 22 the limitation “the third subset of the set of digital circuits”. There is insufficient antecedent basis for this limitation in the claim. Claims 9-15 are also rejected since they depend on independent claim 8 which has been rejected. Allowable Subject Matter Claims 1-7 and 16-20 are allowable. The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claims 1 and 16, patentability exists, at least in part, with the claimed features of a sixth switch coupled to the third transistor and coupled to the second output node; a fourth transistor coupled to the power supply node; a seventh switch coupled to the fourth transistor and to the first output node; and an eighth switch coupled to the fourth transistor and to a ground node; and a control circuit coupled to control the switches of the first DAC sub-circuit and the second DAC sub-circuit. Kim et al (US 2010/0156867) is cited as teaching some elements of the claimed invention including a digital-to-analog converter comprising: a first digital-to-analog converter (DAC) sub-circuit that comprises: a plurality of transistors including a first transistor coupled to a power supply node; a plurality of switches, including a first switch coupled to the first transistor and to a first output node; a second switch coupled to the first transistor and to a second output node; a second DAC sub-circuit coupled to the first DAC sub-circuit that comprises: a third transistor coupled to the power supply node; a fifth switch coupled to the third transistor and coupled to the first output node; and a control circuit coupled to control the switches of the first DAC sub-circuit and the second DAC sub-circuit. However, the prior art, when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH J LAUTURE whose telephone number is (571)272-1805. The examiner can normally be reached 9:30 AM-6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 5712722105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH J LAUTURE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Dec 23, 2025
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603660
MIXED-SIGNAL PROCESSING INTEGRATED IN HYBRID VOLTAGE-TIME ANALOG TO DIGITAL CONVERTER
2y 5m to grant Granted Apr 14, 2026
Patent 12592709
AD CONVERTER DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND DESIGNING METHOD OF AD CONVERTER DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12584802
METHOD AND APPARATUS FOR TEMPERATURE SENSING
2y 5m to grant Granted Mar 24, 2026
Patent 12587201
METHODS AND SYSTEMS FOR LOW NOISE OPERATION OF ANALOG IN MEMORY COMPUTE MAC ARRAYS
2y 5m to grant Granted Mar 24, 2026
Patent 12580579
VOLTAGE REGULATOR WITH PROGRAMMABLE TELEMETRY CONFIGURATION
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+0.8%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 761 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month