Prosecution Insights
Last updated: August 17, 2026
Application No. 18/750,513

LAYER STRUCTURE INCLUDING SILICIDE LAYER, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICES AND ELECTRONIC DEVICES INCLUDING LAYER STRUCTURE

Non-Final OA §102§103
Filed
Jun 21, 2024
Priority
Jan 11, 2024 — RE 10-2024-0004863
Examiner
CHIU, TSZ K
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
537 granted / 678 resolved
+19.2% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
30 currently pending
Career history
713
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 678 resolved cases

Office Action

§102 §103
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). Status of claim(s) to be treated in this office action: Independent: 1 and 13. Pending: 1-20. Information Disclosure Statement Applicant’s IDS(s) submitted on 2/10/2025, 7/25/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 6, 8-15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nishi et al., US PG pub. 20080230804 A1. Re: Independent Claim 1, Nishi discloses a first material layer (Si, fig. 11) including silicon (Si); a second material layer (Er, fig. 11; Er can be Er or Y, ¶0040) configured to face the first material layer (Si, fig. 11) and to form a Schottky barrier with the first material layer (Si, fig. 11); and a silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) between the first material layer (Si, fig. 11) and the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040), wherein the silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) comprises an order “n” silicide and order “n+1” ((Er, Ni)Si, fig. 11C; Er can be yttrium; ¶0040) or greater silicide. Re: Claim 2, Nishi disclose(s) all the limitations of claim 1 on which this claim depends. Nishi further discloses: wherein the silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) comprises: a first silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) between the first material layer (Si, fig. 11) and the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040), the first silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) including the order “n+1” or greater silicide; and a second silicide layer (NiSI layer, fig. 11) between the first silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) and the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040), the second silicide layer ((ER, Ni)SI layer, fig. 11) including the order n silicide (NiSi, fig. 11). Re: Claim 3, Nishi disclose(s) all the limitations of claim 2 on which this claim depends. Nishi further discloses: wherein the first silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) comprises a mixture of the order “n+1” ((Er, Ni)Si, fig. 11C; Er can be yttrium; ¶0040) or greater silicide and the order n silicide (NiSi, fig. 11). Re: Claim 4, Nishi disclose(s) all the limitations of claim 2 on which this claim depends. Nishi further discloses: wherein the order “n+1” ((Er, Ni)Si, fig. 11C; Er can be yttrium; ¶0040) or greater silicide has a composition formula of M1M2Si.sub.x, and the order n silicide (NiSi, fig. 11) has a composition formula M2Si.sub.x, wherein M1 (Er or Y, fig. 11; ¶0040) and M2 (Ni, fig. 11) include different elements. Re: Claim 6, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi further discloses: wherein M1 (Er or Y, fig. 11; ¶0040) includes at least one of Co, Cr, Fe, Hf, Mn, Mo, Nb, Ni, Ru, Sc, Ta, Ti, V, W, Y or Zr. Re: Claim 8, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi further discloses: wherein the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040) comprises one of M1 (Er or Y, fig. 11; ¶0040) and M2 (Ni, fig. 11) as a metal component (Er or Y is a type of metals). Re: Claim 9, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi further discloses: wherein the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040) comprises a metal component (Er or Y is a type of metals) different from M1 (Er or Y, fig. 11; ¶0040) and M2. Re: Claim 10, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi further discloses: wherein the order “n+1” ((Er, Ni)Si, fig. 11C; Er can be yttrium; ¶0040) or greater silicide further comprises an additional metal component (Er or Y is a type of metals) different from M1 (Er or Y, fig. 11; ¶0040) and M2. Re: Claim 11, Nishi disclose(s) all the limitations of claim 1 on which this claim depends. Nishi further discloses: wherein the silicide layer ((ER, Ni)SI layer, fig. 11; Er can be Y ¶0040) is provided between (100) plane of the first material layer (Si, fig. 11) and the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040). Re: Claim 12, Nishi disclose(s) all the limitations of claim 1 on which this claim depends. Nishi further discloses: wherein the first material layer (Si, fig. 11) comprises at least one of an undoped silicon layer, a silicon layer doped with a p-type dopant, or a silicon layer doped with an n-type dopant. Re: Independent Claim 13, Nishi discloses distributing a first element (Ni, fig. 11A) on a first material layer (Si, fig. 11A), the first material layer (Si, fig. 11) comprising silicon (Si); forming a second material layer (Er, fig. 11A; Er can be Er or Y, ¶0040) covering the first element (Ni, fig. 11A) on the first material layer (Si, fig. 11A), the second material layer (Er, fig. 11A; Er can be Er or Y, ¶0040) comprising a metal component (Er or Y is a type of metals); and heat treating (¶0062) the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040) such that a silicide including the first element (Ni, fig. 11A) is formed between the first and second material layer (Ni and Er, fig. 11; Er can be Er or Y, ¶0040)s, wherein the first element (Ni, fig. 11A) is a material different from the metal component (Er or Y is a type of metals). Re: Claim 14, Nishi disclose(s) all the limitations of claim 13 on which this claim depends. Nishi further discloses: distributing a second element ((Er or Y) and Ni, fig. 11B-11C) together with the first element (Ni, fig. 11A) on the first material layer (Si, fig. 11); and forming the second material layer (Er, fig. 11; Er can be Er or Y, ¶0040) to cover the first and second element ((Er or Y) and Ni, fig. 11B-11C)s, wherein the second element ((Er or Y) and Ni, fig. 11B-11C) is a different element from the first element (Ni, fig. 11A). Re: Claim 15, Nishi disclose(s) all the limitations of claim 13 on which this claim depends. Nishi further discloses: wherein the first element (Ni, fig. 11A) includes at least one of Co, Cr, Fe, Hf, Mn, Mo, Nb, Ni, Ru, Sc, Ta, Ti, V, W, Y or Zr. Re: Claim 17, Nishi disclose(s) all the limitations of claim 13 on which this claim depends. Nishi further discloses: wherein the metal component (Er or Y is a type of metals) includes at least one of Sc, Ti, V, Co, Zr, Hf, or Y. Re: Claim 18, Nishi disclose(s) all the limitations of claim 13 on which this claim depends. Nishi further discloses: wherein the heat treating (¶0062) is performed such that the silicide includes a ternary silicide including the first element (Ni, fig. 11A), the metal component (Er or Y is a type of metals), and the silicon and a binary silicide including the metal component (Er or Y is a type of metals) and the silicon. Re: Claim 19, Nishi disclose(s) all the limitations of claim 1 on which this claim depends. Nishi further discloses: A semiconductor device (a semiconductor device as shown in figure 17) comprising the layer structure of claim 1. Re: Claim 20, Nishi disclose(s) all the limitations of claim 1 on which this claim depends. Nishi further discloses: An electronic device (an electronic device as shown in figure 17) comprising the layer structure of claim 1. Claim Rejections - 35 USC § 102/103 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 and 16 is/are rejected under AIA 35 U.S.C. 102/103 as being unpatentable over Nishi et al., US PG pub. 20080230804 A1; in evidence by National Center for Biotechnology Information (NCBI). Nickel (Element) - Atomic Radius. PubChem. (https://pubchem.ncbi.nlm.nih.gov/element/Nickel#section=Atomic-Radius) and PubChem National Center for Biotechnology Information (NCBI). Yttrium (Element) - Atomic Radius. PubChem. (https://pubchem.ncbi.nlm.nih.gov/element/39#section=Atomic-Radius). Re: Claim 5, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi did not mention wherein M1 (Er or Y, fig. 11; ¶0040) has a first atomic radius R1, M2 (Ni, fig. 11) has a second atomic radius R2, and the first atomic radius R1 is equal to or less than (1.15×R2), and M1 (Er or Y, fig. 11; ¶0040) and M2 (Ni, fig. 11) have valence states that are compatible with each other, however, since Nishi teaches the material Yttrium and nickel that is use as the silicide layer, these material is inherently have an atomic radius of a chemical element is a measure of the size of its atom these atomic radius is a characteristic of the element, these characteristic, such as atomic radius of an element, is presumed to exist in the prior art material. Under MPEP § 2112, the "missing" characteristic is considered an inherent result of the identical structure or composition found in the reference Nishi. Re: Claim 16, Nishi disclose(s) all the limitations of claim 13 on which this claim depends. Nishi did not mention wherein the metal component (Er or Y is a type of metals) comprises a metal element, and the first element (Ni, fig. 11A) has a first atomic radius R1, and the metal element has a second atomic radius R2, wherein the first atomic radius R1 is equal to or less than (1.15×R2), and the first element (Ni, fig. 11A) and the metal element have valence electron states that are compatible with each other, however, since Nishi teaches the material Yttrium and nickel that is use as the silicide layer, these material is inherently have an atomic radius of a chemical element is a measure of the size of its atom these atomic radius is a characteristic of the element, these characteristic, such as atomic radius of an element, is presumed to exist in the prior art material. Under MPEP § 2112, the "missing" characteristic is considered an inherent result of the identical structure or composition found in the reference Nishi. Claim Rejections - 35 USC § 103 The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7 is/are rejected under AIA 35 U.S.C. 102/103 as being unpatentable over Nishi et al., US PG pub. 20080230804 A1; in view of Chu et al., US PG pub. 20210193816 A1. Re: Claim 7, Nishi disclose(s) all the limitations of claim 4 on which this claim depends. Nishi is silent regarding: wherein M2 (Ni, fig. 11) includes at least one of Sc, Ti, V, Co, Zr, Hf, or Y. Chu discloses the silicide layer can be made of material include Ti, Ta, Er, Y, Yb, Eu, Tb, Lu, Th, Sc, Hf, Zr, and/or other suitable low work function metal(s). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include these low working function metals when forming a silicide layer with low work function metal since low work function can lower Schottky barrier for electrons allow carriers to flow easily across metal-semiconductor interface, also reduce parasitic resistance which improves electrical contact. Prior art made of record and not relied upon are considered pertinent to current application disclosure. * (“Wu US PG pub. 20070290234 A1”) Discloses a power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer. * (“Okuno et al., US PG pub. 20060138562 A1”) discloses a semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide. Allowable Subject Matter Claim(s) 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Re: Claim 7, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the silicide layer comprises: a first silicide layer between the first material layer and the second material layer, the first silicide layer including the order n+1 or greater silicide; and a second silicide layer between the first silicide layer and the second material layer, the second silicide layer including the order n silicide wherein the order (n+1) or greater silicide has a composition formula of M1M2Six, and the order n silicide has a composition formula M2Six, wherein M1 and M2 include different elements wherein M2 includes at least one of Sc, Ti, V, Co, Zr, Hf, or Y. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jun 21, 2024
Application Filed
Jul 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+10.6%)
3y 4m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 678 resolved cases by this examiner. Grant probability derived from career allowance rate.

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