DETAILED ACTION
This office action is in response to the application filed on 06/21/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/21/2024 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claim 2. Therefore, the “by the inverter comparison signal” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner’s Note: The drawings as filed on 06/21/2024 does not have any inverter shown to create said inverted signal.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al US 2020/0100339 in view of Yu et al. US 2018/0351460 and further in view of Zhao et al. US 2018/0034450.
Regarding Claim 1, Huang teaches (Figures 1-3 and 11 ) a DC voltage converter system (Fig. 1), comprising at least two dividing modules positioned in parallel (11 and 12) and an error module (at 132) configured to generate an error signal indicative of an error between an output voltage and a reference voltage (fig. 3), and a synchronization module (133, 134 and 139) configured to produce, for each dividing period (Fig. 11), one synchronization signal for each respective one of the driving modules , allowing the respective driving of the respective driving modules in an interleaved manner (signal Cot1 and Cot2). (For example: 20-25, 35, 37, 41 and 47-56)
Huang does not teach a storage module configured, for each dividing period, to store the error signal and to transmit the identical stored error signal to all the dividing modules instead of the error signal.
Yu teaches (Figure 2) a storage module (at 301) configured , for each dividing period (each switching period), to store the error signal (at the capacitor and diode circuitry) and to transmit the identical stored error signal to all the dividing modules (sent to 302 and 303) instead of the error signal (output from Gm1). (For example: 125-22 and 26-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include a storage module configured, for each dividing period, to store the error signal and to transmit the identical stored error signal to all the dividing modules instead of the error signal, as taught by Yu to decrease the ripple of the output voltage of the switching power supply in order to maintain a higher quality of output voltage.
Huang as modified does not teach the synchronization module being configured to produce a storage signal controlling the storage module to store the error signal, for each dividing period.
Zhao teaches (Figures 2-5) wherein the synchronization module (producing sync clock and Comp synch) is configured to produce, in each dividing period, a storage signal ordering the storage of the storage module (Cs&h). (For example: Par. 28-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the synchronization module is configured to produce, in each dividing period, a storage signal ordering the storage of the storage module, as taught by Zhao to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.
Regarding Claim 6, Huang teaches (Figures 1-3 and 11 ) a synchronization module.
Huang does not teach wherein the synchronization signal is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period, the pulses of the various synchronization signals being interleaved.
Zhao teaches (Figures 2-5) wherein the synchronization signal (Sync clock or phase clock) is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period (See fig. 5), the pulses of the various synchronization signals being interleaved (Fig. 5). (For example: Par. 28-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein a synchronization signal is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period, the pulses of the various synchronization signals being interleaved, as taught by Zhao to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.
Regarding Claim 7-8, Huang teaches (Figures 1-3 and 11 ) a synchronization module.
Huang does not teach wherein the storage signal comprises one pulse per dividing period.
Zhao teaches (Figures 2-5) wherein the storage signal comprises one pulse per dividing period (fig. 5, sample signal). (For example: Par. 28-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the storage signal comprises one pulse per dividing period, as taught by Zhao to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.
Regarding Claim 9, Huang teaches (Figures 1-3 and 11 ) a DC voltage converter system. (For example: 20-25, 35, 37, 41 and 47-56)
Huang does not teach wherein the storage module is common to all the dividing modules.
Yu teaches (Figure 2) wherein the storage module (with the capacitor at301) is common to all the dividing modules(from 301 to the different modules) . (For example: 125-22 and 26-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the storage module is common to all the dividing modules, as taught by Yu to decrease the ripple of the output voltage of the switching power supply in order to maintain a higher
quality of output voltage.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al US 2020/0100339 in view of Yu et al. US 2018/0351460 and Zhao et al. US 2018/0034450 and further in view of Hariman et al. US 7705579.
Regarding Claim 2, Huang teaches (Figures 1-3 and 11 ) wherein a control module (at 13) configured to produce a control signal (sent to 136 and 137), the control module comprising a logical AND function (138) between the synchronization signal (e.g. Cot) and a comparison signal (ext), and an RS flip-flop function (136-137) deactivated by the comparison signal that is inverted (set and inverter, fig. 2). (For example: 20-25, 35, 37, 41 and 47-56)
Huang does not teach an RS flip-flop function activated by the output of the logical AND function.
Hariman teaches (Figure 5) an RS flip-flop function (sr1) activated by the output of the logical AND function (LG1). (For example: Col. 7 lines 40-67)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include an RS flip-flop function activated by the output of the logical AND function, as taught by Hariman to increasing the speed of responses of the system.
Regarding Claim 3, Huang teaches (Figures 1-3 and 11 ) a synchronization module.
Huang does not teach wherein the synchronization signal is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period, the pulses of the various synchronization signals being interleaved.
Hariman teaches (Figures 2-5) wherein the synchronization signal (Sync clock or phase clock) is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period (See fig. 5), the pulses of the various synchronization signals being interleaved (Fig. 5). (For example: Par. 28-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the synchronization signal is substantially permanently in the high state and exhibits a pulse in the low state once per dividing period, the pulses of the various synchronization signals being interleaved, as taught by Hariman to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.
Regarding Claims 4, Huang teaches (Figures 1-3 and 11 ) a synchronization module.
Huang does not teach wherein the storage signal comprises one pulse per dividing period.
Hariman teaches (Figures 2-5) wherein the storage signal comprises one pulse per dividing period (fig. 5, sample signal). (For example: Par. 28-32)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Huang to include wherein the storage signal comprises one pulse per dividing period, as taught by Hariman to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.
Regarding Claim 5, Huang teaches (Figures 1-3 and 11 ) comprising a drive module (136)configured to control a first transistors (one of Q1-Q4) of a half-bridge in an exclusive manner (par. 35) when the control signal (sent to 136-137) is in one state and to control a second transistors (other of A1-Q4) of the half-bridge in an exclusive manner (par. 35) when the control signal is in the other state. (For example: 20-25, 35, 37, 41 and 47-56)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838