DETAILED ACTION
This action is responsive to the following: the application filed on June 21, 2024 and information disclosure statement filed on October 28, 2024.
Claims 1-20 are pending. Claims 1, 16, and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 28, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “twelfth end connecting the second voltage source” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 14 recites that “a fourth transistor” has “a twelfth end connecting the second voltage source” in reference to the drain of the fourth transistor. This is best understood to correspond to the drain of the transistor M2 in Figure 9. However. Figure 9 shows that the drain of M2 is not connected to the “second voltage source,” which corresponds to “VGSW_ANA” in Figure 9, but rather figure 9 shows that the drain of M2 is connected to the source of M4. The specification in paragraph 88 states “As shown in FIG. 9, the pull-down subcircuit 906 includes a fourth transistor M2 comprising a tenth end connecting the third end of the first transistor M1, an eleventh end connecting the ground reference voltage source VSS, and a twelfth end connecting the second voltage source VGSW_ANA.” Since both the claims and specification require this transistor to be connected to a supply voltage its requested that the drawing sheets reflect the invention as disclosed.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In paragraph 80 line 1 the amplifier amplifier circuit 802 is said to be a “folded cascade amplifier,” this likely should read “folded cascode amplifier”. (emphasis added)
The term “end” is used throughout the specification to refer to various parts of the circuit structure, however this term is not common in the art and is confusing in its ubiquity. For instance, terminals of a transistor, signals that are input/output from one circuit to another, and internal nodes of the circuit are all referred to as “end.” It is suggested that applicant use terms more common in the art in place of “end” or provide a definition of the term to clear up any confusion.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b) indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “end” in claims 1, 10, 13-14, 16, and 20 is used by the claim to mean “node,” “source, “drain,” “gate,” “connection,” “terminal,” while the accepted meaning is “the furthest or most extreme part of something.” The term is indefinite because the specification does not clearly redefine the term.
Additionally, the term “end” is overly broad and renders the claims indefinite by referring to structures by what they are connected to rather than what they are. For instances the first, second, and third end of the first transistor claimed in claim 10 are said to respectively be connected to the driving signal, ground, and the fourth and fifth ends of the second transistor. From Fig. 9 its understood these ends refer to the gate, source and drain of the first transistor respectively, however that is not clear from the claimed language or written description. Thus, a transistor could have gate connected to ground, source connected to the driving signal and be said to have “ends” connected the same as the disclosed invention. However, such an invention with a transistor connected this way would operate materially differently than the invention disclosed. Thus, the terms are overly broad and may lead to confusion when interpreting the claims.
Further many structures are renamed several times and then later explained to represent the same structure later on the claims. For instance, in claim 1 states that the third, fourth, and fifth input ends are all connected to each other and thus represent a single node within the circuit. It is not clear what structure is meant by “input end” beyond a node where wire would connect multiple terminals of a transistors together.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wenske (US 20230091219 A1).
Regarding Independent Claim 1, Wenske teaches the limitations of Claim 1.
A driving circuit (Fig. 1: 100), comprising:
a first-stage amplifier circuit (Fig. 1: 129) comprising a first input end (Fig. 1: 106, VIN) receiving an input signal (Fig. 1: VIN), a second input end (Fig. 1: 108, VFB) receiving a feedback signal (Fig. 1: VFB), and a first output end (Fig. 1: VNdrive, 112, 126) providing a driving signal (Fig. 1: VNdrive), wherein the first-stage amplifier circuit (Fig. 1: 129) comprises a first voltage (Fig. 1: VDD) source having a first voltage level; and
a second-stage amplifier circuit (Fig. 1: 130, 148, 134, 136, 162, 138, 144) comprising a third input end (Fig. 1: VNdrive, 130) connecting the first output (Fig. 1: VNdrive, 112, 126) end to receive the driving signal (Fig. 1: VNdrive), a second output end providing an output signal (Fig. 1: VOUT), and a third output end providing the feedback signal (Fig. 1: VFB), wherein the second-stage amplifier circuit comprises:
a pull-up subcircuit (Fig. 1: 136. 148) comprising a fourth input end (Fig. 1: VNdrive) and a fourth output end (Fig. 1: VOUT); and
a pull-down subcircuit (Fig. 1: 130, 134) comprising a fifth input (Fig. 1: VNdrive) end and a fifth output end (Fig. 1: VOUT), wherein the fourth input end (Fig. 1: VNdrive) and the fifth input end (Fig. 1: VNdrive) connect to the third input end (Fig. 1: VNdrive), and the fourth output end (Fig. 1: VOUT) and the fifth output end (Fig. 1: VOUT) connect to the second output end (Fig. 1: VOUT).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wenske (US 20230091219 A1) in view of Sim et al (US 20010052784 A1) and Lee et al (US 20200076426 A1).
Regarding Claim 2, Wenske teaches the limitations of Claim 1. However, Wenske fails to teach wherein the second-stage amplifier circuit further comprises:
a second voltage source having a second voltage level different from the first voltage level; and
a third voltage source having a third voltage level different from the first voltage level and the second voltage level.
Sim teaches a differential amplifier (Fig. 2: 300) coupled to two generators (Fig. 2: 100, 200) that use three different power supply voltages (Fig. 2: 1, 3, VPP).
Sim states in paragraph 36 “ it is desirable to use a separate power supply voltage for the cell array to reduce the amount of noise created in the circuit by the power supply voltage.” Thus using a separate power domain for an op amp from its inputs its desirable in reducing noise in a circuit.
Lee teaches a driver circuit (Fig. 2B: 250) wherein the current mirror has a first supply voltage (Fig. 2B: VddH) for the pre-driver stage (Fig. 2B: 220) and the output stage (Fig. 2B: 280) has a different second supply voltage (Fig. 2B: Vdd).
Lee teaches in paragraph 10, “The higher supply voltage allows the voltage on node 230 to be greater than Vdd+VTh, which allows the voltage on output node 295 to increase to approximately Vdd” This would allow the output of the amplifier to be better provide a greater range of outputs in the power domain used.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Sim and Lee to the teachings of Wenske to produce a two stage amplifier where the first stage uses single supply voltage and the second stage used two supply voltages, which are different from the first.
Regarding Claim 3, Wenske, Sim, and Lee teach the limitations of Claim 2. 3. Wenske further teaches, wherein the pull-up subcircuit pulls up an output voltage level of the output signal when a first input voltage level of the input signal is higher than a feedback voltage level of the feedback signal (para 11 “The amplifier uses a feedback voltage V.sub.FB dependent on V.sub.OUT to self-regulate, and uses an output control MOSFET (MPout 136) to control V.sub.OUT.”), and the pull-down subcircuit pulls down the output voltage level of the output signal when the first input voltage level of the input signal is lower than the feedback voltage level of the feedback signal. (para 15 “The amplifier stage 129 generates a voltage to adjust an n-channel transistor gate bias, V.sub.Nshift, responsive to a difference between V.sub.IN and V.sub.FB.”)
Regarding Claim 4, Wenske, Sim, and Lee teach the limitations of Claim 3. Wenske further teaches wherein the first-stage amplifier circuit (Fig. 1: 129) and the second-stage amplifier circuit (Fig. 1: 130, 148, 134, 136, 162, 138, 144) further comprise a ground reference voltage source (Fig. 1: 114).
Regarding Claim 5, Wenske, Sim, and Lee teach the limitations of Claim 4. Wenske further teaches wherein the first-stage amplifier circuit (Fig. 1: 129) comprises a differential amplifier comparing the input signal and the feedback signal and generating the driving signal according to a comparison result of the differential amplifier. (para 15 “The amplifier stage 129 generates a voltage to adjust an n-channel transistor gate bias, V.sub.Nshift, responsive to a difference between V.sub.IN and V.sub.FB.”; para 22 “The amplifier stage 129 generates a voltage to adjust a p-channel transistor gate bias, V.sub.Pshift, responsive to a difference between V.sub.IN and V.sub.FB.”)
Regarding Claim 6, Wenske, Sim, and Lee teach the limitations of Claim 5. Wenske further teaches wherein the second-stage amplifier circuit (Fig. 1: 130, 148, 134, 136, 162, 138, 144) pulls up or pulls down the output voltage level of the output signal according to the comparison result of the differential amplifier. (para 15 “The amplifier stage 129 generates a voltage to adjust an n-channel transistor gate bias, V.sub.Nshift, responsive to a difference between V.sub.IN and V.sub.FB.”; para 22 “The amplifier stage 129 generates a voltage to adjust a p-channel transistor gate bias, V.sub.Pshift, responsive to a difference between V.sub.IN and V.sub.FB.”)
Regarding Claim 7, Wenske, Sim, and Lee teach the limitations of Claim 5. Lee further teaches wherein the second voltage level (Fig. 2B: VddH) of the second voltage source (Fig. 2B: 205B) is greater than the third voltage level (Fig. 2: VDD) of the third voltage source (Fig. 2B: 205A). (para 10 “”a second supply voltage source 205B, which provides a supply voltage V.sub.ddH that is greater than V.sub.dd from supply voltage source 205A.)
Regarding Claim 10, Wenske, Sim, and Lee teach the limitations of Claim 5. Lee further teaches a first transistor (Fig. 2B: 225) comprising a first end receiving the driving signal (Fig. 2B: CTL215), a second end connecting the ground reference voltage source (Fig. 2B: 210), and a third end (Fig. 2B: 230);
a second transistor (Fig. 2B: 235) comprising a fourth end connecting the third end of the first transistor (Fig. 2B: 230), a fifth end connecting the third end of the first transistor (Fig. 2B: 230), and a sixth end connecting the second voltage source (Fig. 2B: 205B); and
a third transistor (Fig. 2B: 290) comprising a seventh end connecting the fourth end of the second transistor (Fig. 2B: 230), an eighth end connecting the second output end (Fig. 2B: 295), and a ninth end connecting the third voltage source (Fig. 2B: 205A).
Regarding Claim 13, Wenske, Sim, and Lee teach the limitations of Claim 10. Lee further teaches wherein the third transistor (Fig. 2B: 290) is disposed between the third voltage source (Fig. 2B: 205A) and the second output end (Fig. 2B: 295).
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wenske (US 20230091219 A1) in view of Rana et al (US 20220180944 A1).
Regarding Independent Claim 16, Wenske teaches a driving circuit (Fig. 1: 100) comprising:
a first-stage amplifier circuit (Fig. 1: 129) comprising a first input end (Fig. 1: 106, VIN) receiving an input signal (Fig. 1: VIN), a second input end (Fig. 1: 108, VFB) receiving a feedback signal (Fig. 1: VFB), and a first output end (Fig. 1: VNdrive, 112, 126) providing a driving signal (Fig. 1: VNdrive), wherein the first-stage amplifier circuit (Fig. 1: 129)comprises a first voltage (Fig. 1: VDD) source having a first voltage level; and
a second-stage amplifier circuit (Fig. 1: 130, 148, 134, 136, 162, 138, 144) comprising a third input end (Fig. 1: VNdrive, 130) connecting the first output (Fig. 1: VNdrive, 112, 126) end to receive the driving signal (Fig. 1: VNdrive), a second output end providing an output signal (Fig. 1: VOUT), and a third output end providing the feedback signal (Fig. 1: VFB), wherein the second-stage amplifier circuit comprises:
a pull-up subcircuit (Fig. 1: 136. 148) comprising a fourth input end (Fig. 1: VNdrive) and a fourth output end (Fig. 1: VOUT); and
a pull-down subcircuit (Fig. 1: 130, 134) comprising a fifth input (Fig. 1: VNdrive) end and a fifth output end (Fig. 1: VOUT), wherein the fourth input end (Fig. 1: VNdrive) and the fifth input end (Fig. 1: VNdrive) connect to the third input end (Fig. 1: VNdrive), and the fourth output end (Fig. 1: VOUT) and the fifth output end (Fig. 1: VOUT) connect to the second output end (Fig. 1: VOUT).
Wenske fails to teach a memory device, comprising:
a memory cell array comprising a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and
a peripheral circuit, coupled to the memory cell array, configured to control the memory cell array;
Rana teaches a memory device (Fig. 1: 100), comprising:
a memory cell array (Fig. 1: 106) comprising a plurality of memory cells (Fig. 1: 102) and a plurality of word lines (Fig. 1: 124) coupled to the plurality of memory cells; and
a peripheral circuit (Fig. 1: 108, 112,116, 119, 121), coupled to the memory cell array (Fig. 1: 106), configured to control the memory cell array (Fig. 1: 106);
Rana teaches that a driving circuit with pull up and pull down capability can be used to provide voltages to word lines in memory arrays can be employed to overcome variations due to process and temperature and provide a more exact voltage to memory cells during a read operation. Overvoltaging cells is also an issue that can lead to VTH shift over time. Thus, implementing the driving circuit proposed by Wenske to drive word lines could prevent excessive voltage being placed on the cell in extreme use cases.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Rana to the teachings of Wenske to produce a memory devices with a two stage driver coupled to the memory array as part of the peripheral control circuits.
Regarding Independent Claim 20, Wenske teaches a driving circuit (Fig. 1: 100) comprising:
a first-stage amplifier circuit (Fig. 1: 129) comprising a first input end (Fig. 1: 106, VIN) receiving an input signal (Fig. 1: VIN), a second input end (Fig. 1: 108, VFB) receiving a feedback signal (Fig. 1: VFB), and a first output end (Fig. 1: VNdrive, 112, 126) providing a driving signal (Fig. 1: VNdrive), wherein the first-stage amplifier circuit (Fig. 1: 129)comprises a first voltage (Fig. 1: VDD) source having a first voltage level; and
a second-stage amplifier circuit (Fig. 1: 130, 148, 134, 136, 162, 138, 144) comprising a third input end (Fig. 1: VNdrive, 130) connecting the first output (Fig. 1: VNdrive, 112, 126) end to receive the driving signal (Fig. 1: VNdrive), a second output end providing an output signal (Fig. 1: VOUT), and a third output end providing the feedback signal (Fig. 1: VFB), wherein the second-stage amplifier circuit comprises:
a pull-up subcircuit (Fig. 1: 136. 148) comprising a fourth input end (Fig. 1: VNdrive) and a fourth output end (Fig. 1: VOUT); and
a pull-down subcircuit (Fig. 1: 130, 134) comprising a fifth input (Fig. 1: VNdrive) end and a fifth output end (Fig. 1: VOUT), wherein the fourth input end (Fig. 1: VNdrive) and the fifth input end (Fig. 1: VNdrive) connect to the third input end (Fig. 1: VNdrive), and the fourth output end (Fig. 1: VOUT) and the fifth output end (Fig. 1: VOUT) connect to the second output end (Fig. 1: VOUT).
Wenske fails to teach a system comprising: a memory device, comprising:
a memory cell array comprising a plurality of memory cells and a plurality of word lines coupled to the plurality of memory cells; and
a peripheral circuit, coupled to the memory cell array, configured to control the memory cell array;
Rana teaches a system (Fig. 1: 100) comprising: a memory device (Fig. 1: 100), comprising:
a memory cell array (Fig. 1: 106) comprising a plurality of memory cells (Fig. 1: 102) and a plurality of word lines (Fig. 1: 124) coupled to the plurality of memory cells; and
a peripheral circuit (Fig. 1: 108, 112,116, 119, 121), coupled to the memory cell array (Fig. 1: 106), configured to control the memory cell array (Fig. 1: 106);
Rana teaches that a driving circuit with pull up and pull down capability can be used to provide voltages to word lines in memory arrays can be employed to overcome variations due to process and temperature and provide a more exact voltage to memory cells during a read operation. Overvoltaging cells is also an issue that can lead to VTH shift over time. Thus, implementing the driving circuit proposed by Wenske to drive word lines could prevent excessive voltage being placed on the cell in extreme use cases.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Rana to the teachings of Wenske to produce a memory devices with a two stage driver coupled to the memory array as part of the peripheral control circuits.
Claims 2-7, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wenske (US 20230091219 A1) and Rana et al (US 20220180944 A1) in view of Sim et al (US 20010052784 A1) and Lee et al (US 20200076426 A1).
Regarding Claim 17, Wenske and Rana teach the limitations of Claim 16. Claim 17 is rejected for the same reasons as Claim 2.
Regarding Claim 18, Wenske, Rana, Sim, and Lee teach the limitations of Claim 17. Claim 18 is rejected for the same reasons as Claim 3.
Allowable Subject Matter
Claims 8-9, 11-12. 14-15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8, requires that the voltage level of the second supply voltage be between 13 and 17 volts. None of the references cited require a second supply voltage have a voltage in this range. Therefore, this claim would be allowable if written in independent form.
Claim 9, is allowable for being dependent on claim 8.
Claim 11, required the limitation that there is a high voltage transistor in series between the first and second transistor. Though, Lee teaches a first and second transistor and Lee teaches transistors with tolerance for high votlages, Lee fails to disclose a high voltage transistor that is high voltage in series between them. The other references fail to disclose a similar feature. Therefore this claim would be allowable if written in independent form.
Claim 12 is allowable for being dependent on Claim 11.
Claim 14, requires the limitation of a fourth and fifth transistor connected in series between the second supply voltage and ground where the fourth transistor has a gate connected to the drain of the first transistor, a source connected to ground and a drain connected to the second supply voltage. And where the fifth transistor has a gate connected to ground, a source connected to the drain of the fourth transistor and a drain connected to the second supply voltage. None of the sources cited teach a structure like this. Therefore, the claim would be allowable if written in independent form.
Claim 15, is allowable for being dependent on Claim 14.
Claim 19, claim 19 requires the limitation that the second supply voltage is generated by a voltage regulator in the peripheral circuit. None of the references cited state that the supply voltages are being generated from local voltage sources. Therefore, this claim would be allowable if written in independent form.
Conclusion
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/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825