DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (KR 20230121691).
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(Claim 1) Lee et al. teach a memory device, comprising:
a first semiconductor structure (CP), comprising:
a semiconductor body (CP) extending along a first direction (Z);
a gate structure (WL1) located between adjacent semiconductor bodies;
a bit line (BL) extending along a second direction (Y) and connected to a first end (CP1) of two ends (CP1, CP2) of the semiconductor body (CP) that are opposite to each other along the first direction,
wherein the first direction (Z) is perpendicular to the second direction (Y); and
a first cavity (AG) located between the bit line (BL) and the gate structure (WL1).
(Claim 3) Lee et al. teach wherein the first semiconductor structure (CP) comprises a plurality of the semiconductor bodies, which include a plurality of semiconductor body groups, the semiconductor body group comprises a first semiconductor body (Alternate CP) and a second semiconductor body (Adjacent), which both extend along the first direction (Z) and are arranged along the second direction (Y),
the plurality of semiconductor body groups are arranged in an array along the second direction (Y) and a third direction (X), the third direction is perpendicular to the first direction and intersects with the second direction (fig. 1); and
the gate structure extends (WL1) along the third direction (X) and is located between the first semiconductor body and the second semiconductor body of the semiconductor body group (Adjacent semiconductor bodies, CP).
(Claim 4) wherein the first cavity (AG) extends along the third direction (X).
(Claim 12) Lee et al. teach a method of manufacturing a memory device, comprising:
forming a first semiconductor structure (CP), wherein the forming the first semiconductor structure comprises:
forming a semiconductor body (CP) extending along a first direction (Z);
forming a gate structure (WL1) located between adjacent semiconductor bodies;
forming a bit line (BL), extending along a second direction (Y) and connected to a first end (CP1) of two ends of the semiconductor body that are opposite to each other along the first direction,
wherein the first direction (Z) is perpendicular to the second direction (Y); and
forming a first cavity (AG) located between the bit line and the gate structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 20230121691) in view of Zhu et al. (US 2023/0062141).
(Claim 20) Lee et al. teach a memory system, comprising:
a memory device, comprising:
a semiconductor structure (CP), comprising:
a semiconductor body (CP) extending along a first direction (Z);
a gate structure (WL1) located between adjacent semiconductor bodies;
a bit line (BL) extending along a second direction (Y) and connected to a first end (CP1) of two ends (CP1, CP2) of the semiconductor body that are opposite to each other along the first direction,
wherein the first direction (Z) is perpendicular to the second direction (Y); and
a first cavity (AG) located between the bit line (BL) and the gate structure (WL1).
Lee et al. lack a controller coupled to the memory device and configured to control at least one operation of the memory device.
However, Zhu et al. teach a controller coupled to the memory device and configured to control at least one operation of the memory device for the benefit controlling the array of memory cells (paragraph 6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of for the benefit controlling the array of memory cells.
Allowable Subject Matter
Claims 2, 5 – 11 and 13 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claim 2) wherein a size of the first cavity along the second direction ranges from 10 nm to 60 nm, and/or a size of the first cavity along the first direction ranges from 10 nm to 100 nm.
(Claim 5) wherein a shape of a first surface of the gate structure is curved, and the first surface is a surface, proximate to the bit line, of two surfaces of the gate structure that are opposite to each other along the first direction.
(Claim 6) wherein the first semiconductor structure further comprises a dielectric layer, which is located between the first semiconductor body and the second semiconductor body of the semiconductor body group, and is located on a side surface of the first semiconductor body, on a side surface of the second semiconductor body,
on a surface, proximate to the bit line, of two surfaces of the gate structure that are opposite to each other along the first direction, and
on a surface, proximate to the gate structure, of two surfaces of the bit line that are opposite to each other along the first direction.
(Claim 13) forming the gate structure (WL1) and forming the first cavity (AG) comprise:
forming a first sacrificial structure between the first semiconductor body and the second semiconductor body of the semiconductor body group from a second side,
wherein the first sacrificial structure extends along the third direction, and a size of the first sacrificial structure along the first direction is less than a size of the semiconductor body group along the first direction, the first side and the second side are sides of the plurality of semiconductor body groups that are opposite to each other along the first direction;
forming an initial gate structure covering the first sacrificial structure between the first semiconductor body and the second semiconductor body of the semiconductor body group from the second side; and
removing the first sacrificial structure and a part of the initial gate structure from the first side to form the gate structure and the first cavity.
(Claim 17) wherein the forming the first semiconductor structure further comprises:
before forming a metal material layer on an initial bit line from a first side, forming third sacrificial structures in the first cavity, in a second cavity, and between adjacent initial bit lines; and
after forming the bit line, removing the third sacrificial structures to form third cavities between adjacent bit lines.
Conclusion
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
September 15, 2026
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