DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/11/2025 has been entered.
DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1, 3-13, 15-23, 25, and 26 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 11,256,624. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 11,256,624
1. A computing device, comprising:
a microprocessor configured to access memory via virtual memory addresses; first memory; and
a communication device configured to establish a network connection to communicate with a remote computing system having second memory;
wherein the computing device is configured to:
map a first portion of the virtual memory addresses to the first memory and map a second portion of the virtual memory addresses to the second memory of the remote computing system;
communicate, via the communication device with the remote computing system, to access the second memory, in response to the microprocessor accessing the second portion of the virtual memory addresses;
predict the microprocessor accesses the second portion of the virtual memory addresses; and
determine a prediction of degradation in the network connection in a subsequent time period in which the microprocessor is predicted to have activities to access the second portion of the virtual memory addresses.
1. A method implemented in a computing system, the method comprising:
provisioning memory resources for access through virtual memory addresses; mapping a first portion of the virtual memory addresses into local memory of a first computing device; establishing a network connection between the first computing device and a second computing device; requesting, over the network connection by the first computing device, to borrow an amount of memory from the second computing device; in response to the second computing device lending the amount of memory to the first computing device, mapping a second portion of the virtual memory addresses into local memory of the second computing device; predicting a time period during which the network connection degrades; predicting a usage of a first virtual memory address region; in response to a determination that the usage is predicted to occur in the first computing device during the time period during which the network connection degrades, and the first virtual memory address region is currently being mapped to the local memory of the second computing device: making a migration decision for content of the first virtual memory address region; communicating over the network connection to store the content of the first virtual memory address region into the first computing device, prior to the time period and in response to the migration decision; and changing, in response to the migration decision and after storing the content into the local memory of the first computing device, memory mapping of the first virtual memory address region, by mapping the first virtual memory address region into the local memory of the first computing device; wherein when the first virtual memory address region is mapped into the local memory of the first computing device, the first virtual memory address region is associated in a memory map of the second computing device with an identifier of the first computing device; and wherein when the first virtual memory address region is mapped into the local memory of the second computing device, the first virtual memory address region is associated in a memory map of the first computing device with an identifier of the second computing device.
3. The method of claim 1, wherein: when the first virtual memory address region is mapped into the local memory of the first computing device, the memory map of the first computing device maps the first virtual memory address region to a first physical memory address region in the local memory of the first computing device; and when the first virtual memory address region is mapped into the local memory of the second computing device, the memory map of the second computing device maps the first virtual memory address region to a second physical memory address region in the local memory of the second computing device; and wherein the communicating includes communicating the content from the second physical memory address region in the local memory of the second computing device to the first physical memory address region in the local memory of the first computing device.
This rejection has been made as all limitations of claim 1 of the instant application are present in the claims of 11,256,624, and therefore claim 1 of the instant application is anticipated by the claims of 11,256,624. See MPEP 804(II)(B)(2).
Independent claim 13 is the method corresponding to the computing device of claim 1, and is rejected under similar rationale. Independent claim 23 is the non-transitory computer storage medium corresponding to the computing device of claim 1, and is rejected under similar rationale. Further, the dependent claims of both cases contain substantially similar limitations.
Claims 1, 3-13, 15-23, 25, and 26 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 12,019,549. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Instant Application
US 12,019,549
1. A computing device, comprising:
a microprocessor configured to access memory via virtual memory addresses; first memory; and
a communication device configured to establish a network connection to communicate with a remote computing system having second memory;
wherein the computing device is configured to:
map a first portion of the virtual memory addresses to the first memory and map a second portion of the virtual memory addresses to the second memory of the remote computing system;
communicate, via the communication device with the remote computing system, to access the second memory, in response to the microprocessor accessing the second portion of the virtual memory addresses;
predict the microprocessor accesses the second portion of the virtual memory addresses
determine a prediction of degradation in the network connection in a subsequent time period in which the microprocessor is predicted to have activities to access the second portion of the virtual memory addresses.
1. A computing device, comprising:
a microprocessor configured to access memory via virtual memory addresses; first memory;
and a communication device configured to establish a network connection to communicate with a remote computing system having second memory; wherein the computing device and the remote computing system are two separate computers connected via a computer network using the network connection; and wherein the computing device is configured to: communicate, with the remote computing system over the network connection, to borrow an amount of memory from the remote computing system and to cause the remote computing system to allocate the second memory as the amount of memory borrowed by the computing device; map a first portion of the virtual memory addresses to the first memory and map a second portion of the virtual memory addresses to the second memory of the remote computing system; communicate, via the communication device with the remote computing system, to access the second memory, in response to the microprocessor accessing the second portion of the virtual memory addresses;
determine a prediction of degradation in the network connection in a subsequent time period in which the microprocessor is predicted to have activities to access the second portion of the virtual memory addresses; and in response to the prediction and before the subsequent time period: communicate with the computing system to retrieve data from the second memory of the remote computing system, before the activities of the microprocessor accessing the second portion of the virtual memory addresses; store, into a portion of the first memory, the data retrieved from the second memory of the remote computing system; and map the second portion of the virtual memory addresses to the portion of the first memory.
This rejection has been made as all limitations of claim 1 of the instant application are present in the claims of 12,019,549, and therefore claim 1 of the instant application is anticipated by the claims of 12,019,549. See MPEP 804(II)(B)(2).
Independent claim 13 is the method corresponding to the computing device of claim 1, and is rejected under similar rationale. Independent claim 23 is the non-transitory computer storage medium corresponding to the computing device of claim 1, and is rejected under similar rationale. Further, the dependent claims of both cases contain substantially similar limitations.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 10, 13, 15-18, 21-23, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), and Barker et al (US 11,689,593).
Regarding Claim 1, Domsch teaches a computing device, comprising:
a microprocessor (processor 18 of Fig. 1) configured to access memory via memory addresses (memory is accessed via the process of Fig. 4);
first memory (local memory 36 of Fig. 1); and
a communication device (RDMA manager 54 of Fig. 1) configured to establish a network connection (network 16 of Fig. 1) to communicate with a remote computing system having second memory (remote computing system 14 with remote memory 30 of Fig. 1);
wherein the computing device is configured to:
map a first portion of the memory addresses to the first memory (address range 1000-1999 of Fig. 2) and map a second portion of the memory addresses to the second memory of the remote computing system (address range 3000-3999 of Fig. 2);
communicate, via the communication device with the remote computing system, to access the second memory, in response to the microprocessor accessing the second portion of the memory addresses (shown on Fig. 4, particularly steps 108, 118, and 124).
However, the cited prior art does not explicitly teach to:
predict the microprocessor accesses the second portion of the virtual memory addresses.
Dropps teaches to predict microprocessor accesses to a portion of memory addresses in remote memory (Paragraphs 0006 & 0011-0012).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the prediction of Dropps in the cited prior art in order to increase speed of data retrieval.
Further, the cited prior art does not explicitly teach a microprocessor configured to access memory via virtual memory addresses; or
map a first portion of the virtual memory addresses to the first memory and map a second portion of the virtual memory addresses to the second memory of the remote computing system.
Guim Bernat teaches a microprocessor configured to access memory via virtual memory addresses; and
map a first portion of the virtual memory addresses to the first memory and map a second portion of the virtual memory addresses to the second memory of the remote computing system (Paragraph 0025).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the virtual addresses of Guim Bernat in the cited prior art in order to easily direct memory requests to an appropriate location.
Further, the cited prior art does not explicitly teach wherein the computing device is configured to: determine a prediction of degradation in the network connection in a subsequent time period in which the microprocessor is predicted to have activities to access the second portion of the virtual memory addresses.
Barker teaches to: determine a prediction of degradation in the network connection (corresponding to the data connection quality being below threshold 403 of Fig. 5B, C13 L31-51) in a subsequent time period in which a microprocessor is predicted to have activities to access a remote portion of data (C13 L52 – C124 L5).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the prediction of Barker for the second portion of the virtual memory addresses in the cited prior art in order to improve performance.
Regarding Claim 3, the cited prior art teaches the computing device of claim 1, wherein the computing device is configured to: communicate, in response to the prediction and before the subsequent time period, with the computing system to retrieve data from the second memory of the remote computing system, before the activities of the microprocessor accessing the second portion of the virtual memory addresses (C13 L52 – C124 L5 of Barker).
Regarding Claim 4, the cited prior art teaches the computing device of claim 1, wherein the virtual memory addresses are provisioned in a unified virtual memory space in the computing device and in the remote computing system (shown on Fig. 2 of Domsch).
Regarding Claim 5, the cited prior art teaches the computing device of claim 4, wherein memory resources are provisioned for access in the unified virtual memory space (shown on Fig. 2 of Domsch).
Regarding Claim 6, the cited prior art teaches the computing device of claim 1, wherein the computing device is configured to predict the subsequent time period during which both the degradation and the activities to access the second portion of the virtual memory addresses are predicted (C13 L52 – C124 L5 of Barker).
Regarding Claim 10, the cited prior art teaches the computing device of claim 1, wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted based at least in part on a scheduled operation of the computing device; and the data includes software or data for the scheduled operation (C13 L52 – C124 L5 of Barker).
Claim 13 is the method corresponding to the computing device of claim 1, and is rejected under similar rationale.
Claim 15 is the method corresponding to the computing device of claim 3, and is rejected under similar rationale.
Claim 16 is the method corresponding to the computing device of claim 4, and is rejected under similar rationale.
Claim 17 is the method corresponding to the computing device of claim 5, and is rejected under similar rationale.
Claim 18 is the method corresponding to the computing device of claim 6, and is rejected under similar rationale.
Regarding Claim 21, the cited prior art teaches the method of claim 18, wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted based at least in part on: a predicted location of the computing device, a scheduled operation of the computing device, or a battery power level of the computing device, or any combination thereof (C13 L52 – C124 L5 of Barker).
Regarding Claim 22, the cited prior art teaches the method of claim 18, wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted via an artificial neural network stored in a portion of the virtual memory addresses; the method further comprises: providing, by the computing device, data as input to the artificial neural network; and performing, by the remote computing system, at least a portion of computations of the artificial neural network (Paragraph 0014 of Dropps).
Claim 23 is the non-transitory computer storage medium corresponding to the computing device of claim 1, and is rejected under similar rationale.
Claim 25 is the non-transitory computer storage medium corresponding to the computing device of claim 3, and is rejected under similar rationale.
Claim 26 is the non-transitory computer storage medium corresponding to the computing device of claim 5, and is rejected under similar rationale.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576) Barker et al (US 11,689,593), and Zedlewski et al (US 7,434,002).
Regarding Claim 7, the cited prior art teaches the computing device of claim 1, bit does not explicitly teach wherein the computing device is further configured to: change, after storing the data into a portion of the first memory, memory mapping by mapping the second portion of the virtual memory addresses to the portion of the first memory.
Zedlewski teaches to change, after storing the data into a portion of a first memory, memory mapping by mapping the second portion of the virtual memory addresses to the portion of the first memory (“cache optimizer 3025 directs memory re-mapper 2020 to remap remote information to local storage, such as local RAM, to improve locality of data storage,” C15 L30-60).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the changing of Zedlewski in the cited prior art in order to “improve locality of data storage” (C15 L30-60 of Zedlewski).
Claims 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), Zedlewski et al (US 7,434,002), Barker et al (US 11,689,593) and Wong (US 7,596,654).
Regarding Claim 8, the cited prior art teaches the computing device of claim 7, but does not explicitly teach wherein the computing device is further configured to: after mapping the second portion of the virtual memory addresses to the portion of the first memory, causing the remote computing system to operate a portion of the second memory from which the data is stored into the portion of the first memory, as a cache, mirror, or a backup of the portion of the first memory.
Wong teaches a computing device configured to: causing a remote computing system to operate a portion of a second memory from which the data is stored into the portion of the first memory, as a cache, mirror, or a backup of the portion of the first memory (see cache of remote pages 112 of Fig. 7, indicating the remote memory is a mirror or backup of the cached data).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cache of Wong in the cited prior art after mapping the second portion of the virtual memory addresses to the portion of the first memory, in order to quickly access requested data.
Regarding Claim 11, the cited prior art teaches the computing device of claim 1, but does not explicitly teach wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted via an artificial neural network stored in a portion of the virtual memory addresses; the computing device is configured to provide data as input to the artificial neural network; and the remote computing system is configured to perform at least a portion of computations of the artificial neural network (Paragraph 0014 of Dropps).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), Barker et al (US 10,728,299), Barker et al (US 11,689,593), and Roese et al (US 10,341,458).
Regarding Claim 9, the cited prior art teaches the computing device of claim 1, but does not explicitly teach wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted based at least in part on a predicted location of the computing device.
Roese teaches to make predictions regarding content to be migrated based at least in part on a predicted location of the computing device (C3 L39-51).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the predictions of the cited prior art based at least in part on a predicted location of the computing device (as taught by Roese) in order to quickly provide data to a user.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), Barker et al (US 10,728,299), and Mogul et al (US 7,437,438).
Regarding Claim 12, the cited prior art teaches the computing device of claim 1, but does not explicitly teach wherein the degradation and the activities to access the second portion of the virtual memory addresses are predicted based at least in part on a battery power level of the computing device.
Mogul teaches to accessing data from a remote memory based at least in part on a battery power level of the computing device (Fig. 3, C4 L33-58).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the predictions of the prior art based at least in part on a battery power level of the computing device in order to balance speed and battery life (C4 L33-58 of Mogul).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), Barker et al (US 10,728,299), Barker et al (US 11,689,593) and Zedlewski et al (US 10,728,299).
Regarding Claim 19, the cited prior art teaches the method of claim 13, but does not explicitly teach: changing, after storing the data into a portion of the first memory, memory mapping by mapping the second portion of the virtual memory addresses to the portion of the first memory.
Zedlewski teaches to changing, after storing the data into a portion of a first memory, memory mapping by mapping the second portion of the virtual memory addresses to the portion of the first memory (“cache optimizer 3025 directs memory re-mapper 2020 to remap remote information to local storage, such as local RAM, to improve locality of data storage,” C15 L30-60).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the changing of Zedlewski in the cited prior art in order to “improve locality of data storage” (C15 L30-60 of Zedlewski).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Domsch et al (US 2009/0113143) in view of Dropps (US 2019/0114275), Guim Bernat et al (US 2017/0353576), Barker et al (US 10,728,299), Barker et al (US 11,689,593), Zedlewski et al (US 10,728,299) and Wong (US 7,596,654).
Regarding Claim 20, the cited prior art teaches the method of claim 19, but does not explicitly teach: causing, after mapping the second portion of the virtual memory addresses to the portion of the first memory, the remote computing system to operate a portion of the second memory from which the data is stored into the portion of the first memory, as a cache, mirror, or a backup of the portion of the first memory.
Wong teaches causing a remote computing system to operate a portion of a second memory from which the data is stored into the portion of the first memory, as a cache, mirror, or a backup of the portion of the first memory (see cache of remote pages 112 of Fig. 7, indicating the remote memory is a mirror or backup of the cached data).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cache of Wong in the cited prior art after mapping the second portion of the virtual memory addresses to the portion of the first memory, in order to quickly access requested data.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On pages 2-3 of the submitted remarks, applicant argues:
“There is no reasonable expectation of using the virtual memory address structure of Domsch in the content distribution network of Dropps. Thus, the combination of Domsch and Dropps suggested in the Office Action is seen entirely based on the blueprint of claimed invention and thus a hindsight reconstruction made using elements selectively-picked from Domsch and Dropps according to the blueprint of claimed invention.”
This argument has been considered but is not persuasive.
The examiner maintains it would be obvious to use the prefetching from remote memory (as taught by Dropps) in the computing device of Domsch in order to increase the speed of data retrieval. The examiner further notes that the concept of pre-fetching data before it is explicitly requested is common in the art. Therefore, the examiner maintains that one of ordinary skill in the art would find it obvious to fetch data from remote memory before it is requested using the teachings of Domsch and Dropps.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
For the above reasons, the rejection has been maintained.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Zohar et al (US 8,010,753) teaches Systems And Methods For Temporarily Transferring Use Of Portions Of Partitioned Memory Between Host Computers.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 3-13, 15-23, 25, and 26 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on (571) 272 - 5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135