DETAILED ACTION
The current Office Action is in response to the papers submitted 04/21/2026. Claims 1 – 9, 11, 13 - 39 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The claims disclose process behavior information, system utilization statistics cache misses, and page accessed before becoming unaccessed. There is no specific disclosure of these limitations in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 3, 26, and 29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 3, 26, and 29 disclose the use of process behavior information, system utilization statistics cache misses, and/or page accessed before becoming unaccessed. The original specification fails to disclose the use of these terms.
All remaining claims are rejected for being dependent on a rejected base claim.
Claims 1 – 9, 11, and 13 - 39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 4, 11, 16, 27, 33, and 39 recite the limitations “relatively faster memory” and/or “relatively slower memory” in multiple locations. The use of the term “relatively” indicates the memory is compared to something. The amendments disclose the access latency of the first memory is lower than the access latency of the second memory which makes the first memory faster than the second memory based on access latency. However, the limitations fail to indicate what the claimed faster and slower limitations are relative too. It is unclear why the first memory is considered faster when the claim already defined the first memory as being faster based on the access speed. This makes it unclear if the concept of relatively faster and relatively slower is based on a comparison between the first and second memories or the memories are compared against something else. Defining the first memory as being having a lower access latency then the second memory and then saying the first memory is relatively faster makes it unclear what the relatively faster means since the first memory already has a lower access latency which makes the first memory faster then the second memory. There is no indication what the first memory is compared against making the first memory relatively faster.
It is also unclear what aspect of the memory is considered faster or slower. This could mean the speed of data reads, writes, data access in general including both reads and writes, the speed of the memory to be accessible after start up, or any other number of aspects that can be considered faster or slower. This makes the limitation and claim indefinite since the scope of what is considered “relatively faster” and “relatively slower” is unclear. For examiner the limitations will be considered as referring to each other which means the computer system has a plurality of memories where a first memory of the plurality of memories is considered faster than a second memory of the plurality of memories in terms of general data access.
The first memory comprises relatively faster memory and the second memory comprises relatively slower memory. It is unclear if this is meant to mean the first memory, which was defined as being faster then the second memory based on access latency, comprises additional memory that is relative faster to something else of if the relatively faster memory is the first memory itself. The same uncertainty applies to the relatively slower memory comprised in the second memory.
Claims 2 and 28 recite the limitation “a local relatively fast memory”. The use of the term “relatively” indicates the memory is compared to something. However, the limitation fails to indicate what the fast limitation is compared to. It is also unclear what aspect of the memory is considered fast. This could mean the speed of data reads, writes, data access in general including both reads and writes, the speed of the memory to be accessible after start up, or any other number of aspects that can be considered fast. This makes the limitation and claim indefinite since the scope of what is considered “relatively fast” is unclear.
The terms “relatively faster”, “relatively slower”, and “relatively fast” in claims 1 - 2, 4, 11, 16, 27 - 28, 33, and/or 39 are relative terms which renders the claims indefinite. The terms “relatively faster”, “relatively slower”, and “relatively fast” are not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. There is no indication what aspect of memory is considered fast, faster, or slower. The claims fail to define what the degree of “relative” is to be considered fast, faster, or slower also.
The term “local” in claims 2 and 28 is a relative term which renders the claims indefinite. The term “local” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. There is no indication what the relatively fast memory is local to and what defines the meaning of local as compared to another memory that is not local.
Claims 4 and 30 recite the limitation the pages that are pushed are pushed independently of any transfer request by the process. Claim 4 is dependent on claim 1 and claim 30 is dependent on claims 27. Both claims 1 and 27 disclose inputting information corresponding to events, such as transfer requests, associated with a process running on the operating system. The inputted information is input into a machine learning component that is used to configure prefetching. This shows that in the independent claims the pushing of pages in a prefetch operation is based on requests of the process used to train the machine learning component. Requests of a process running on an operating system simplify down to read and write requests in a computer system. Read and write requests are transfer requests. This makes it unclear how the pushing of pages is independent of any transfer request when the prefetching that pushes data is based on transfer requests. The limitation will be treated as meaning the pushing of certain pages is performed before a request for the certain pages is received from the process.
The term “near” in claim 7 is a relative term which renders the claim indefinite. The term “near” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. There is no indication what defines near with regard to near future as compared to another version of the future.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 9, 11, 13 – 15, 17 – 18, 23 – 27, and 37 - 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dias et al. (Pub. No.: US 2020/0250096) referred to as Dias in view Zhuang et al. (Pub. No.: US 2016/0239423) referred to as Zhuang in view of BenHanokh et al. (Pub. No.: US 2022/0164313) of referred to as BenHanokh.
Regarding claim 1, Dias teaches a memory management method [Figs 2 – 4], for a computing system [Figs 1 and 8 – 9], in which the computing system [Figs 1 and 8 – 9] includes an operating system (OS) [Paragraph 0018; An operating system is the software that runs on the system hardware allowing the user to interact with the hardware] that supports virtual memory [130-1 and 130-N, Fig 1; Logical units shows the use of virtual memory] and that accesses at least two tiers of memory, including a first memory and a second memory, in which the first memory has a lower access latency than the second memory, the first memory [150, Fig 1; Paragraph 0018; Cache 150 is considered faster than other memory in the system such as 125 in figure 1] thereby comprising relatively faster memory and the second memory [125, Fig 1; Paragraph 0018; The storage 125 is considered slower than cache] thereby comprising relatively slower memory the memory management method [Figs 2 – 4] comprising:
inputting from the OS [Paragraph 0018] to a learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410] information [Paragraphs 0037 – 0039; The hit information and I/O traces are information input to the learning to component] corresponding to events associated with a process running on the OS [210, Fig 2; 410, Fig 410; The processes that cause the flow charts to be activated are run on the operating system of the system], in which the component is configured within a memory appliance [120, Fig 1; Figs 2 – 4; The prefetch adaptive prefetching process is configured in a memory appliance that is running on 120];
in the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410],
synthesizing a page access model from at least one sequence of the events inputted from the OS [310 and 320, Fig 3; Paragraphs 0037 – 0039; The look ahead window is a page access model used for prefetching based on I/O traces from the OS];
identifying patterns in the at least one sequence of the events [315, Fig 3; Paragraph 0037 – 0039; The look ahead window is optimized based on the traversal do the address space which is patterns of usage];
in real time, predicting page misses by the process in the relatively faster memory that are likely to happen by the process and, based on the predicted page misses, identifying most-likely-to-be-needed pages that the process may attempt to access in the relatively faster memory [315, Fig 3; Paragraphs 0037 – 0039; The simulation engine predicts pages that will be missed based on I/O traces and adjusts the look ahead window accordingly in real time as the system is running]; and
pushing at least some of the most-likely-to-be needed pages [Fig 6; The blocks between 1069 – 1255 and 5349 – 5511; These blocks are most likely to be accessed in the future and are prefetched] from the relatively slower memory [125, Fig 1] to the relatively faster memory [150, Fig 1],
whereby the pages the process will attempt to access in at least one relatively faster memory [150, Fig 1] are predictively pushed to and made available to the process in at least one relatively faster memory [150, Fig 1] before the process attempts access [Fig 6; Paragraphs 0046 - 0047; The blocks between 1069 – 1255 and 5349 – 5511; The blocks loaded to the cache include blocks predicted to be accessed outside of the actual requested blocks].
However, Dias may not specifically disclose the limitation of the component being a machine learning component that is configured within a memory appliance that is logically separate from the OS.
Zhuang discloses the component that manages the prefetching is configured within a memory appliance that is logically separate from the OS [Paragraph 0024; Claim 1; The prefetching rules are separate from the operating system].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zhuang in Dias, because it allows for prefetching rules to be applied to an operating system that does not support prefetching along with updating the prefetching rules without having to update the operating system based on data correlations associated with applications [Paragraph 0024].
However, Dias in view of Zhuang may not specifically disclose the limitation of the component being a machine learning component.
BenHanokh discloses the learning component is a machine learning component [Paragraphs 0015 – 0016 and 0032].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate BenHanokh in Dias in view of Zhuang, because the use of machine learning allows the prefetching to be tuned and adjusted based on complex and non-linear access patterns, adapt to irregular workloads, and generally adapt to behavior of the system.
Regarding claims 2 and 28, Dias teaches the memory appliance [120, Fig 1; Figs 2 – 4] accesses a local relatively fast memory [150, Fig 1; Paragraph 0018];
the memory appliance [120, Fig 1; Figs 2 – 4] and the computing system [Figs 1 and 8 – 9] communicate over a network [Figs 1 and 8 – 9; The lines indicate data paths of a network that allows the memory appliance and computer system to communicate to different devices]; and
the most-likely-to-be needed pages are pushed over the network [Figs 1 and 6; The data that is loaded into the cache is moved along the lines from the cache 150 to logical units 125 along the network of data lines].
Regarding claims 3 and 29, Dias teaches the memory appliance [120, Fig 1; Figs 2 – 4] and the OS [Paragraph 0018] run on a common hardware platform [100, Fig 1; The operating system and prefetch software run on the same hardware in figure 1]; and
the most-likely-to-be accessed pages are pushed into a memory space [150, Fig 1] shared by the memory appliance [120, Fig 1; Figs 2 – 4] and the OS [Paragraph 0018; The operating system accesses the cache for requests and the software prefetch application accesses the cache to perform prefetch operations].
Regarding claims 4 and 30, Dias teaches the most-likely-to-be-needed pages that are pushed from the relatively slower memory [125, Fig 1] to the relatively faster memory [150, Fig 1] are pushed independently of any corresponding transfer request by the process and transparent to the process [Fig 6; The blocks moved to cache outside the actual request are moved independent of a request for the blocks. A request resulting in extra blocks being transferred that were not directed to the extra blocks is not considered a corresponding request].
Zhuang discloses pages to be pushed are pushed independently of any page miss handler controlled by the OS [Paragraph 0024; The prefetch rules and operations are separate from the operating system showing the pushing is performed independently of operations of the operating system].
Regarding claims 5 and 31, Dias teaches comprising predicting the page misses according to an access prediction criterion [310, Fig 3; Paragraphs 0036 – 0039 and 0049 - 0051; The look ahead window predicts which pages will be missed in the future based on access prediction criteria indicating based on locality if current requests].
Regarding claim 6, Dias teaches in which the access prediction criterion is a function of an output of the page access model [310 and 320, Fig 3; Paragraphs 0049 – 0051; The output of the page access model is feed back into the model to set the criterion to set the model when the model is not optimized].
Regarding claim 7, Dias teaches generating the output as a list of pages currently residing in the memory appliance estimated to be needed by the process within a near future [320, Fig 3; The unseen I/O traces represent pages in the memory appliance that will be needed in the future].
Regarding claim 8, Dias teaches generating the list of pages as a ranked list; and
choosing a cutoff of the ranked list that is adjustable in real time in order to adjust a dimensionality of the page access model [Fig 6; Paragraphs 0037 – 0039 and 0046 - 0047; The look ahead window is a list of pages that are ranked as being optimal pages to be prefetched with regard to a request. The size of the look ahead window has a cutoff that can be adjusted by the page access model as needed].
Regarding claim 9, Dias teaches the access prediction criterion is whether an access score, which corresponds to a probability [310, Fig 3; Paragraphs 0046 – 0051; The look ahead window is equivalent to a probability score that indicates so many blocks beyond the actual requested blocks are likely to be requested and are thus prefetched into the cache] that the process, after detection of a trigger event, will refer to other pages within a number of subsequent memory access operations, exceeds a threshold score [Fig 6; Paragraphs 0046 – 0051; The blocks that are prefetched outside of the blocks actually requested are scored above a threshold indicating they have a high probability to be accessed, after a trigger event of the process executing, by the process within a number of accesses from the actual request based on time].
Regarding claim 11, Dias teaches the access prediction criterion is whether an access score, which corresponds to a probability [310, Fig 3; Paragraphs 0046 – 0051; The look ahead window is equivalent to a probability score that indicates so many blocks beyond the actual requested blocks are likely to be requested and are thus prefetched into the cache] that predicted pages are likely to be needed by the process before other, colder pages resident in the relatively faster memory [150, Fig 1; Paragraph 0018] exceeds a threshold score [310, Fig 3; Paragraphs 0046 – 0051; The look ahead window is an indication of predicted pages that are likely to be needed before other pages in the system including pages in the cache. The size of a window is based on a threshold score indicating how much extra data to prefetch based on the operation of the system].
Regarding claim 13, Dias teaches including in the access prediction criterion a threshold score that predicted pages are likely to be needed; and
dynamically adjusting the threshold score to change how many pages are designated as the most-likely-to-be needed pages [320, Fig 3; Fig 6; Paragraphs 0046 – 0051; The locality of blocks to actually requested blocks is a threshold score that is dynamically adjusted changing the number of blocks prefetched].
Regarding claim 14, Dias teaches the score is a probability [310, Fig 3; Paragraphs 0046 – 0051; The look ahead window is equivalent to a probability score that indicates so many blocks beyond the actual requested blocks are likely to be requested and are thus prefetched into the cache].
Regarding claims 15 and 32, Dias teaches the memory appliance [120, Fig 1; Figs 2 – 4; The prefetch adaptive prefetching process is configured in a memory appliance that is running on 120] directs the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410] to predict the page misses upon detection of at least one trigger event [Fig 6; Paragraphs 0046 – 0047; The pages predicted to be missed are predicted based on the actual request being received].
BenHanokh discloses the learning component is a machine learning component [Paragraphs 0015 – 0016 and 0032].
Regarding claims 17 and 34, Dias teaches the at least one trigger event includes run-time memory access behavior information in addition to page misses [710, Fig 7; Paragraphs 0029, 0036 – 0039, and 0052; Prefetching is performed and controlled by trace information which is considered run-time memory access behavior information and a miss occurring].
Regarding claims 18 and 35, Dias teaches the process is one of a plurality of processes running concurrently on the OS [210, Fig 2; 410, Fig 410; The processes that cause the flow charts to be activated are run on the operating system of the system. Operating systems run multiple processes concurrently]; and
the page access model is synthesized specific to the process, independent of behavior of any other of the plurality of processes [220, Fig 2; 315, Fig 3; The look ahead window is the page access model and is synthesized in the simulation based on the process that requested data].
Regarding claims 23 and 37, Dias teaches scanning blocks of the virtual memory [130-1 and 130-N, Fig 1; Logical units shows the use of virtual memory] to sample accesses by the process [315, Fig 3; Paragraph 0037 – 0038; The look ahead window is based on a hit ratio which indicates a scan of the blocks of the virtual memory to determine hits and misses to obtain the hit ratio]; and
inputting resulting scanning information [Paragraphs 0037 – 0039; The hit information and I/O traces are information input to the learning to component] to the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410].
BenHanokh discloses the learning component is a machine learning component [Paragraphs 0015 – 0016 and 0032].
Regarding claim 24 and 38, Dias teaches the sequence of events includes at least one event chosen from the group of events comprising a page miss, detection of contextual embedding actions including process/thread scheduling, the creation and destruction of a virtual address space, page hits, and page swapping [310 and 320, Fig 3; Paragraphs 0037 – 0039; The I/O traces result in either page hits or misses which allows the system to determine the hit ratio].
Regarding claim 25, Dias in view of Zhuang in view of BenHanokh teaches carrying out the steps of claim 1 [Refer back to the rejection of claim 1] independent of specific hardware support in the computing system [Dias, Paragraphs 0079 – 0086; Any type of hardware that supports the functions of claim 1 can implement the steps of claim 1].
Regarding claim 26, Dias teaches the information [Paragraphs 0037 – 0039; The hit information and I/O traces are information input to the learning to component] input to the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410] includes at least one of the information items including hardware performance counters, software counters, system utilization statistics cache misses, translation lookaside-buffer (TLB) misses, CPU load, I/O activity [Paragraphs 0037 – 0039; The I/O trace information is I/O activity], a thread identifier, the process’ name, offset of a page in a process virtual address space section, pressure stall information metrics, a page swap-out time, a time of most recent use of a respective page, process address space size upon swap-out, process cumulative page fault data when upon swap-out, process cumulative runtime upon swap-out of a memory block, I/O waiting time upon memory block swap-out, process working set size at swap-out, page sharing by more than one process/thread at swap-out, page unaccessed time exceeding an access time threshold, page accessed before becoming unaccessed, page accessed shortly after swap-out, identification of a number of pages accessed by context before a most recent page miss on a respective page, and a time at which a page block was first accessed in a virtual memory of a context.
Claim 27 is a system claim corresponding to claim 1 and is rejected using the same prior art and reasoning mutatis mutandis. Dias teaches the memory management system [Figs 1 and 8 – 9].
Claim(s) 19, 21, - 22, and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dias et al. (Pub. No.: US 2020/0250096) referred to as Dias in view Zhuang et al. (Pub. No.: US 2016/0239423) referred to as Zhuang in view of BenHanokh et al. (Pub. No.: US 2022/0164313) of referred to as BenHanokh as applied to claims 1 and 27 above, and further in view of Mayur Jain (Sampling in Machine Learning: A Beginner’s Guide) referred to as Jain.
Regarding claims 19 and 36, Dias teaches including page addresses [Paragraph 0039; The trace information indicating how the memory is traversed shows the use of address information to know the traversal of the memory] in the information input from the OS [Paragraph 0018; The operating system inputs requests for data to the prefetching process] to the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410].
BenHanokh discloses the learning component is a machine learning component [Paragraphs 0015 – 0016 and 0032].
However, Dias in view of Zhuang in view of BenHanokh may not specifically disclose the limitation(s) of reducing the number of page addresses used as inputs by sampling.
Jain discloses reducing the number of page addresses used as inputs by sampling [What is Sampling?, Pages 2 – 3; The use of sampling reduces the amount of any data by only using a small sample of the larger overall data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Jain in Dias in view of Zhuang in view of BenHanokh, because it reduces computational costs and saving time by only inputting, transferring, and analyzing a smaller representative sample of a larger group of data.
Regarding claim 21, Dias teaches including page addresses [Paragraph 0039; The trace information indicating how the memory is traversed shows the use of address information to know the traversal of the memory] in the information input from the OS [Paragraph 0018; The operating system inputs requests for data to the prefetching process] to the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410].
Jain discloses sampling input data [What is Sampling?, Pages 2 – 3; The use of sampling reduces the amount of any data by only using a small sample of the larger overall data].
Regarding claim 22, Dias teaches including page addresses [Paragraph 0039; The trace information indicating how the memory is traversed shows the use of address information to know the traversal of the memory] in the information input from the OS [Paragraph 0018; The operating system inputs requests for data to the prefetching process] to the learning component [Figs 2 – 4; The adaptive prefetching process is a component that performs prefetching that learns based on training data as in step 410].
Jain discloses sampling all input data [What is Sampling?, Pages 2 – 3; The use of sampling reduces the amount of any data by only using a small sample of the larger overall data].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dias et al. (Pub. No.: US 2020/0250096) referred to as Dias in view Zhuang et al. (Pub. No.: US 2016/0239423) referred to as Zhuang in view of BenHanokh et al. (Pub. No.: US 2022/0164313) of referred to as BenHanokh in view of Mayur Jain (Sampling in Machine Learning: A Beginner’s Guide) referred to as Jain as applied to claim 19 above, and further in view of IT Articles (The importance of sampling in Machine Learning) referred to as IT Articles.
Regarding claim 20, Jain discloses the sampling of data [What is Sampling?, Pages 2 – 3; The use of sampling reduces the amount of any data by only using a small sample of the larger overall data].
However, Dias in view of Zhuang in view of BenHanokh in view of Jain may not specifically disclose the limitation(s) of sampling is a function of an accuracy rate of the machine learning component.
IT Articles discloses sampling is a function of an accuracy rate of the machine learning component [Why is it important to choose carefully a sampling technique in Machine Learning, Pages 1 – 3; Performance comparison between different sample techniques, Pages 10 – 14; The sample that is used is a function of the performance of the machine learning].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate IT Articles in Dias in view of Zhuang in view of BenHanokh in view of Jain, because it allows the sampling to be adjusted to reduce overfitting and handle imbalances in the source dataset [Why is it important to choose carefully a sampling technique in Machine Learning?, Pages 1 – 3].
Allowable Subject Matter
Claims 16 and 33 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 39 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Response to Arguments
Applicant's arguments filed 04/21/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 13 – 16 that the specification provides proper support for previously rejected terms from the claims. The support is indicated as being in certain paragraphs and/or in Table 1. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
After looking over the table and indicated paragraphs from the specification most of the term or similar language has been identified in the specification. However, a couple terms are still unclear and do no appear to be properly disclosed in the specification at either a specific paragraph or in the Table 1.
Process behavior information is argued as being present in paragraphs 0034 and 0097. The closest the examiner is able to find is “other information about prior system behavior” in paragraph 0034 and “detect phase changes representing different behaviors over time” in paragraph 0097. In both paragraphs the terminology is different then what is in the claims and therefor the specification fails to provide proper support for the claimed limitation
The applicant points to paragraph 0097 for “system utilization statistics” support and both paragraph 0097 and Table 1 for “cache misses” support. The term in the claim is “system utilization statistics cache misses” from claim 26. The specification discloses cache misses in multiple location. Paragraph 0097 discloses system utilization statistics to monitor events such as cache misses. This makes the system utilization statistics separate from the cache misses that the statistics are used to monitor. The claim though makes the statistics and cache misses as a single item which the specification fails to support.
The claims discloses information input the machine learning component includes at least one of multiple types of information including page accessed before becoming unaccessed. The applicant points to Table 1 for support for this. The closest entry in the table that appears to be related to the claims page accessed before becoming unaccessed is on page 18 and is called Page accessed time very short before unaccessed. The entry in the table is based on a time that is very short. There is no mention of time in the claim regarding the page accessed before becoming unaccessed. This shows the information disclosed in the specification is different then what is claimed.
The applicant argues on pages 17 – 18 that the claims provide support for the terms rejected under 112(a). After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
As indicated above there are still three terms that the specification fails to properly describe in such a way as to reasonably convey to one skilled in the relevant art that the inventor had possession of the claimed invention. The terms are process behavior information, system utilization statistics cache misses, and page accessed before becoming unaccessed. The locations pointed to for support fail to provide proper support as indicated above.
The applicant argues on pages 18 – 19 that the amendments spell out what the relatively faster and relatively slower limitations mean. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The amendments actually make the meaning of relatively faster and relatively slower more unclear then they were before. The amendments define the first memory as having a lower access latency than the second memory. This inherently shows the first memory is faster than the second memory in terms of access latency. The amendments then go on further to state the first memory comprises relatively faster memory.
There is no indication as to what the faster memory is compared to in order to be relatively faster then. It is also unclear if the faster memory is the first memory itself or if it is another memory that is part of the first memory since the first memory now comprises the relatively faster memory. The same issues apply to the second memory and the relatively slower memory comprised in the second memory.
Defining the first memory as having a lower access latency then the second memory makes the first memory faster then the second memory. The limitation of the first memory comprising relatively faster memory is unclear since the claim already defined the first memory as being faster compared to the second memory. It is unclear what the memory is relatively faster then. The same reasoning applies to the second memory comprising relatively slower memory. There is no indication what the relative slower and relative faster memory are relatively slower and relatively faster then.
The applicant argues on pages 20 – 21 that the term “local” is a well-known concept requiring no further elucidation for those who are skilled in the art. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The local limitation in the claims is unbound making the scope of what is considered local unclear. It is unclear if local is meant in terms of the memory appliance, the first memory, the second memory, or some other device in the system. The term local can be related to the system overall that the method is operating in, a specific device in the system, or a larger local network the system is part of. A claim that accesses a local memory with no indication as to what is meant by local is unclear and indefinite.
The applicant argues on pages 24 – 25 that the specification provides support and definition of the “independently” limitation and therefor the claim is not indefinite. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The claims recite that the pages are pushed independently of any corresponding transfer request by the process. As indicated in the 112(b) rejection above, claim 1 defines the training of the prefetching is based in part on the patterns in the events. Claim 4 is dependent on claim 1. The events include transfer requests corresponding to processes running on the system. This shows the pushing of data is not independent of processes but is actually dependent on processes.
The claim further says the pushing is independent of any corresponding transfer request by the process. There are no bounds on what is meant by corresponding also. Any previous transfer request of a process would be considered corresponding to the process. Claim 1 shows that the pushing of data is dependent on any related transfer request by the process that is feed into the machine learning component. Claim 4 indicating the pushing is independent now is unclear since it negates what base claim 1 requires. The pushing might be independent of a specific transfer request but claim 1 prevents the pushing from being independent of any and all corresponding transfer requests by the process.
The applicant argues on pages 26 – 27 that the concept of “near” is not unclear based on paragraphs 0026 and 0044 which indicates the near future which may be defined in different ways and up to design choice. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The applicant’s arguments actually point to showing the scope of “near” is not clearly defined and is a relative term. The idea that the concept of near is not definitely defined and up to design choice shows the near concept is a relative term. What is considered near to one person might not be considered near to another person. This shows then the scope of the term is indefinite since a definitive meaning of the term near is not presented and left up to design choice, as argued by the applicant.
The applicant argues on page 29 that the process behavior information is defined in paragraphs 0088 and 0097 especially and therefor is not indefinite. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no indication of “process behavior information” as claimed in the cited sections of paragraphs 0088 or 0097 that the applicant relies on. The cited paragraphs disclose multiple types of information such as counters and statistics. However, none of these are referred to as process behavior information as disclosed in the claims. There is no clear link to indicate the counters and statistics are the process behavior information other then the applicant saying they are.
The applicant argues on pages 29 – 30 that Diaz teaches predicting access patterns of the entire storage system or of each logical area as compared to the predicting page misses by the process that are likely to happen by the process and identifying needed pages that the process may attempt to access. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Diaz teaches using unseen I/O trace data to change a look-ahead window size in step 320. The look-ahead window is passed on I/O trace information indicating locations the unseen I/O processes will likely try to access. The look-ahead window is adjusted based on the locations the processes will likely try to access when the processes are actually executed. This shows the window is adjusted based on the process before the process actually requests the data.
The applicant argues on page 31 that Dias works on a coarser granularity then the invention since a page is not disclose in Dias. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Paragraph 0030 discloses the memory 125 can be physical storage and use physical address. Blocks in physical memory are understood in the art to be comprised of smaller storage units called pages. The management of blocks according to figures 2 – 3 is also the management of the pages that make up the blocks. Deciding which blocks to push to the cache is also deciding which pages to push to the cache also based on the size of the look-ahead window.
The applicant argues on pages 31 – 32 that Dias will suffer from the fixed assumption solution since Dias pulls data where the claims now say the data is pushed since swap-ins are issued implicitly by the OS in response to a page fault before the client even knows it needs them as indicated in paragraph 0031 of the specification. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The push and pull language itself does not distinguish the claims from Dias. A push and pull of data is a result of a frame of reference when data is transferred from one device to another. A prediction of data that is needed and thus transferred is “pulled” from the memory when a device or method determines the data is needed. The data that is transferred is also “pushed” from the memory based on the view from the memory since the data is pushed from the memory to the receiving device.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the data is pushed since swap-ins are issued implicitly by the OS in response to a page fault before the client even knows it needs them) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on page 32 that Dias reacts to requests and is tied to execution flow whereas the invention as claimed may be decoupled from execution. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Dias teaches in figure 3 that the look-ahead window is based on unseen I/O traces. This shows the look-ahead window and associated prefetching is not entirely on current execution but based on predicted execution. This is the same as the argued decoupling. Dias reacts to current requests and also future requests to know which data is likely to be needed.
The applicant argues on pages 32 – 33 that there are multiple reasons why Zhuang cannot be combined with Dias since Zhuang fails to teach aspects that Dias is used to teach. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Zhuang does not have to specifically support or teach the same aspects that Dias is used to teach. Zhuang it only used to teach the prefetching is in a memory appliance that is logically separate from the OS. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant argues on pages 33 – 34 that the claims are allowable since the addition of BenHanokh fails to remedy the argued deficiencies of Dias. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above regarding Dias explaining how Dias teaches the current claim limitations. BenHanokh is used to teach the learning component of Dias is a machine learning component that adds the benefit of machine learning. The rejections are maintained base don Dias in view of Zhuang in view of BenHanokh as indicated in the rejections above.
The applicant argues on page 34 that most of the other claims are allowable since they inherent the argued deficiencies above from independent claims. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above shows how the prior art teaches the limitations in the independent claims. The rejections of similar independent claims and dependent claims are maintained based on the rejections of their respective independent claim.
The applicant argues on page 34 with regard to claim 4 that Dias reacts in response to access to the storage and does not operate independently of any corresponding transfer request from the process. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no clear indication as to what a corresponding transfer request from the process is currently. As indicated in the rejections above, a request for data from Dias results in extra data being prefetched along with the actual data that was requested as shown in figure 6. For example blocks 1070 – 1255 are transferred or pulled from the memory and there is no corresponding request from the process since the process did not specifically request blocks 1070 – 1255. The same goes for blocks 5350 – 5511 in figure 6. There is no corresponding request directly requesting the extra blocks. This shows then there is no corresponding request for the data from the process since the process did not directly request the extra data.
The applicant argues on page 34 with regard to claim 8 that Dias fails to teach a ranked list ranked for example by probability or a maximum list size, which can be adjusted as the system runs as disclosed in parages 0044. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The claims do not require what the applicant has argued. There is no specifics as to how the ranking is done. The window is a ranked list where the entries in the windows are ranked higher than entries not in the window when it comes to what to prefetch. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a ranked list ranked for example by probability or a maximum list size, which can be adjusted as the system runs) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on page 34 regarding claim 9 that Dias fails to teach a score that estimate the probability that a process will refer to other pages within a number of subsequent memory access operation exceeds a threshold. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no mention of the score being an estimate in the claim. The claim requires the score to correspond to a probability but there is no mention that the score actually estimates the probability as argued. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., score that estimate the probability) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The look-ahead windows in Dias is based on the additional blocks in the look-ahead window being marked or scored as having a higher probability then other blocks of being accessed shortly after a trigger even of a miss causing the additional blocks in the look-ahead window to be prefetched. The threshold is based on the cache hit ration. The blocks that provide a higher cache hit ratio are labeled or scored higher then other blocks.
The applicant argues on page 35 regarding claim 13 that Dias fails to teach the concept of a threshold since the term threshold is not specifically disclosed in Dias. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Paragraph 0038 disclose the look-ahead windows is determined and then analyzed to see if the window is a good window. If the window is not satisfactory the process starts again to re-create the look-ahead window as shown in figure 3. Knowing if the window is satisfactory or not shows the use of some form of a threshold that criteria of the window is compared against. If the cache hit ratio is not high enough then the criteria of the look-ahead window has not reached a certain cache hit ration threshold and a new window is calculated.
The applicant argues on page 35 that claims 16, 33, and 39 are allowable since claim 16 and 33 were not rejected under prior art and claim 39 incorporates claims 16 and 33. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Claims 16, 33, and 39 are all rejected under 112(b) as indicated above in the rejections. Claims 16 and 33 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b). Claim 39 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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