Prosecution Insights
Last updated: August 17, 2026
Application No. 18/751,342

DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING DISPLAY SUBSTRATE

Non-Final OA §102§103
Filed
Jun 24, 2024
Priority
Jul 28, 2023 — CN 202310942792.3
Examiner
SNYDER, ADAM J
Art Unit
Tech Center
Assignee
Xiamen Tianma Display Technology Co., Ltd.
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
638 granted / 913 resolved
+9.9% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
27 currently pending
Career history
946
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
63.5%
+23.5% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 913 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US 2021/0273035 A1). Clam 1, Cho (Fig. 1-17B) discloses a display substrate (100; Fig. 12; Paragraph [0091]; wherein discloses a base substrate), provided with a display region (AA; Fig. 1 and 2; Paragraph [0048]; wherein discloses a display area AA) and a non-display region (PA; Fig. 1 and 2; Paragraph [0049]; wherein discloses a peripheral area PA) at least partially surrounding the display region (AA; Fig. 1 and 2), comprising: data cables (DL1-DLn+1; Fig. 2; Paragraph [0069]; wherein discloses data lines) arranged in the display region (AA; Fig. 2); adapter cables (Connecting Line; Fig. 10) arranged in the display region (AA: Fig. 10), wherein at least a part of the data cables (Data Line (1-719); Fig. 10) are electrically connected (Contact; Fig. 10) to the adapter cables (Connecting Line; Fig. 10); and connecting cables (Data Spider Line; Fig. 10) arranged in the non-display region (PA; Fig. 9; Fig. 10; Paragraph [0072]; wherein discloses data spider line is in the peripheral area PA), wherein a part of the connecting cables (Data Spider Line; Fig. 10) are electrically connected (Contacts; Fig. 10) to the part of the data cables (Data Line; Fig. 10) through the adapter cables (Connecting Line; Fig. 10), and the remaining connecting cables (Connecting Line; Fig. 10) are electrically connected (Paragraph [0070]; wherein discloses “the data line may be directly connected to the data spider line DSPL through the spider contact hole SCNT”) to the remaining data cables directly (DL; Fig. 4; 589-1175; Fig. 5), wherein the data cables (DL1-DLn+1; Fig. 2; Paragraph [0069]; wherein discloses data lines) are arranged in a first direction (D1; Fig. 2), the connecting cables (Data Spider Line; Fig. 10; DSPL; Fig. 4) are arranged in the first direction (D1; Fig. 4), and the data cables (Data Line (1-590); Fig. 10) are arranged in a same sequence (Paragraph [0123]; wherein discloses “the data lines DATA LINE may be electrically connected to the data spider lines DATA SPIDER LINE in the same order as the data spider lines DATA SPIDER LINE are arranged”) as the connecting cables (Data Spider Line (1-590); Fig. 10) electrically connected (Connecting Line; Fig. 10) to the data cables (Data Line (1-590); Fig. 10). Claim 10, Cho (Fig. 1-17B) discloses wherein the data cables (DL1-DLn+1; Fig. 2) are grouped into first data cables (DLn and DLn+1; Fig. 2) and second data cables (DL1-DLn-1; Fig. 2), the connecting cables (DSPL1 and DSPL; Fig. 4) are grouped into first connecting cables (DSPL; Fig. 4) and second connecting cables (DSPL1; Fig. 4), the second connecting cables (DSPL1; Fig. 4) are electrically connected (SCNT1 and CCNT1; Fig. 4) to the second data cables (DL1-DLn+1; Fig. 2) through the adapter cables (CL1-CLn-1; Fig. 2; CL; Fig. 4), and the first connecting cables (DSPL; Fig. 4) are electrically connected (SCNT; Fig. 4) to the first data cables directly (DLn and DLn+1; Fig. 2 DL; Fig. 4); and the first data cables (DLn and DLn+1; Fig. 2) are sandwiched between the second data cables (DL1-DLn+1; Fig. 2; Fig. 2; wherein figure shows connecting lines used on both left and right side of the display area) and the first connecting cables (DSPL; Fig. 4) are sandwiched between the second connecting cables (DSPL1; Fig. 4), in the first direction (D1; Fig. 4). Claim 11, Cho (Fig. 1-17B) discloses wherein the display region (AA; Fig. 2 and 4) comprises an edge (Fig. 4; wherein figure shows an edge of the display area AA adjacent to peripheral area PA) comprising a corner edge (Fig. 4; wherein figure shows a curved edge portion) and a straight edge (Fig. 4; wherein figure shows a straight edge portion) extending along the first direction (DR1; Fig. 4), the second data cables (1-588; Fig. 5) each correspond to the corner edge (Fig. 5; wherein figure shows a curved edge portion) and a part of the straight edge (Fig. 5; wherein figure shows a straight edge portion), and the first data cables (589-1175; Fig. 5) each correspond to the straight edge only (Fig. 5; wherein figure shows a straight edge portion). Claim 12, Cho (Fig. 1-17B) discloses wherein the first data cables (589-1175; Fig. 5) are more than a half (Fig. 1 and 2; wherein further additional data lines are arranged between the two connection lines area on the left and right) of the second data cables (1-588; Fig. 5). Claim 13, Cho (Fig. 1-17B) discloses wherein the non-display region (PA; Fig. 9) comprises a binding region (COP; Fig. 9 and 4), data signal terminals (Paragraph [0053]) arranged in the binding region (COP; Fig. 9 and 4) along the first direction (D; Fig. 9 and 4), and the connecting cables (DSPL1 and DSPL; Fig. 4) are connected to the data signal terminals (Paragraph [0053]), respectively (Fig. 4); and the data cables (1-590; Fig. 10) are arranged in the same sequence (Paragraph [0123]; wherein discloses “Accordingly, unlike the display apparatus of FIGS. 4 and 5, it is unnecessary to change an order of output signals of a data driving chip that is connected to the data spider line, and a generally-designed data driving chip may be used”) as the data signal terminals (1-590; Fig. 10) electrically connected to the data cables (1590; Fig. 10). Claim 14, Cho (Fig. 1-17B) discloses a display panel (Fig. 1 and 2; wherein discloses a display apparatus), comprising: the display substrate (100; Fig. 1) according to claim 1 (see rejection to claim 1 above). Claim 15, Cho (Fig. 1-17B) discloses a display device (500; Fig. 17A and 17B), comprising: the display panel (Fig. 1 and 2; wherein discloses a display apparatus) according to claim 14 (see rejection to claim 14 above). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 2021/0273035 A1) in view of Choi et al (US 2024/0420633 A1). Claim 2, Cho (Fig. 1-17B) discloses wherein the data cables (DL1-DLn+1; Fig. 2) are n in number (Fig. 2; wherein figure shows a plurality of data lines), and n is an integer greater than or equal to 2 (Fig. 2; wherein figure shows more than two data lines). Cho does not expressly disclose the display substrate further comprises m*n auxiliary cables, m is an integer greater than or equal to 2, the auxiliary cables extend in a same direction as the data cables, and the m*n auxiliary cables are evenly distributed in the display region; the adapter cables comprise respective first segments extending in a same direction as the auxiliary cables; and at least part of the auxiliary cables are partially integrally formed with the first segments, respectively. Choi (Fig. 1-21) discloses the display substrate (110; Fig. 1-3) further comprises m*n auxiliary cables (ASL2; Fig. 8; Paragraph [0168]; wherein discloses second auxiliary lines ASL2), m is an integer greater than or equal to 2 (Fig. 8; wherein figure 8 shows two auxiliary arranged between two data lines DL1 or DL2), the auxiliary cables (ASL2; Fig. 8) extend in a same direction (DR2; Fig. 8) as the data cables (DL1 and DL2; Fig. 8), and the m*n auxiliary cables (ASL2; Fig. 8) are evenly distributed in the display region (DA; Fig. 7); the adapter cables (TASL1 and TASL2; Fig. 8; Paragraph [0167-0168]) comprise respective first segments (TASL2; Fig. 8) extending in a same direction (DR2; Fig. 8) as the auxiliary cables (ASL2; Fig. 8); and at least part of the auxiliary cables (ASL2; Fig. 8; Paragraph [0168]) are partially integrally formed with the first segments (TASL2; Fig. 8), respectively (Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 3, Choi (Fig. 1-21) discloses wherein the adapter cables (TASL1 and TASL2; Fig. 8) comprise respective second segments (TASL1; Fig. 8) extending along the first direction (DR1; Fig. 8), and the second segments (TASL1; Fig. 8) are electrically connected (Paragraph [0167]) to the data cables at first ends (DL1; Fig. 8), and are electrically connected (Paragraph [0168]) to the auxiliary cables (ASL2 and TASL2; Fig. 8) at second ends (Paragraph [0168]), respectively (Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 4, Choi (Fig. 1-21) discloses wherein m auxiliary cables (ASL2; Fig. 8; wherein figure shows two ASL2 lines arranged between two adjacent data lines DL1 or DL2) are arranged between two adjacent data cables (DL1 or DL2; Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 5, Choi (Fig. 1-21) discloses further comprising: pixel driving circuits (EPD; Fig. 5 and 8) arranged in columns (Paragraph [0081]) respectively connected to the data cables (DL1 or DL2; Fig. 8); and m is equal to 2 (Fig. 8; wherein figure 8 shows two auxiliary arranged between two data lines DL1 or DL2), each column (EPD; Fig. 8) corresponds to two of the auxiliary cables (VSAVL and TASL2; Fig. 8), wherein the corresponding data cable (DL1 or DL2; Fig. 8) is sandwiched between the two auxiliary cables (ASL2; Fig. 8) in the first direction (DR1; Fig. 8). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 6, Cho (Fig. 1-17B) discloses wherein the auxiliary cables (CL1c; Fig. 9) are arranged on a different film layer (CL1; Fig. 8) than the data cables (DL; Fig. 8), and the m*n auxiliary cables (CL1c; Fig. 9) are arranged on a same film layer (CL1; Fig. 8). Claim 7, Choi (Fig. 1-21) discloses further comprising: a first power cable (VDL; Fig. 8; Paragraph [0195]) extending along a second direction (DR2; Fig. 8), wherein the first power cable (VDL; Fig. 8) is configured to transmit a positive voltage signal (Paragraph [0095]; wherein discloses “a first power line VDL for transmitting the first power ELVDD”), the second direction (DR2; Fig. 8) intersects the first direction (DR1; Fig. 8), and the auxiliary cables (VSAVL or TASL2; 8) are arranged on a same film layer (VSAVL or TASL2; 10) as the first power cable (VDL; Fig. 10). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 8, Choi (Fig. 1-21) discloses wherein the auxiliary cables (ASL2; Fig. 8) are grouped into first auxiliary cables (TASL2; Fig. 8) and second auxiliary cables (VSAVL; Fig. 8); the first auxiliary cables (TASL2; Fig. 8) are partially integrally formed with the first segments (TASL2; Fig. 8) of the adapter cables (TASL1 and TASL2; Fig. 8), respectively (Fig. 8); and the second auxiliary cables (VSAVL; Fig. 8) are electrically connected to a constant voltage signal cable (VSSPL; Fig. 8; Paragraph [0193]). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Claim 9, Choi (Fig. 1-21) discloses, further comprising: a second power cable (VSSPL; Fig. 8) electrically connected to the second auxiliary cables (VSAVL; Fig. 8; Paragraph [0193]) and configured to transmit a negative voltage signal (ELVSS; Paragraph [0188]). Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Cho’s display device by applying auxiliary lines, as taught by Choi, so to use a display device with auxiliary lines for providing a display device capable of reducing the width of a non-display area (Paragraph [0010]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Adam J Snyder/Primary Examiner, Art Unit 2623 07/29/2026
Read full office action

Prosecution Timeline

Jun 24, 2024
Application Filed
Jul 31, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
89%
With Interview (+18.7%)
2y 7m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 913 resolved cases by this examiner. Grant probability derived from career allowance rate.

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