DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in respond to the amendment filed on 02/25/26.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (USP 5,121,014) in view of Yin et al. (US 2010/0264956).
For claim 1, Figures 1-3 of Huang each teaches a CMOS inverter circuit comprising: a first P-channel transistor (M1), having a gate terminal for receiving an input signal (IN in Figures 1-2, output of inverter M15-M16 in Figure 3) and a source terminal connected to a power supply voltage (VDD supply); a second P-channel transistor (M3), having a gate terminal for receiving the same input signal (IN in Figures 1-2, output of inverter M15-M16 in Figure 3) as the first P-channel transistor (M1), and having a source terminal connected in series with a drain terminal of the first P-channel transistor (M1); and a first N-channel transistor (M4), connected in series with the drain terminal of the second P-channel transistor (M3), having a gate terminal for receiving the same input signal (IN in Figures 1-2, output of inverter M15-16 in Figure 3) as the first and second P-channel transistors (M1 and M3), and having a source terminal connected to ground (ground, by way of M5 or M6). Huang does not teach the transistors (P-channel and N-channel transistors) in each of the inverter of Figures 1-3 comprise oxide thin-film transistors. However, Yin et al. teaches oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify each of Figures 1-3 of Huang so that the transistors (P-channel and N-channel transistors) in each inverter of the Figures 1-3 of Huang comprise oxide thin-film transistors for the purpose of low power applications because oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]). Thus, this combination/modification teaches all the limitations of claim 1 including the transistors comprise oxide thin-film transistors.
For claim 2, Figures 1-3 of Huang in the above combination/modification each teaches wherein the channel width of the first P-channel oxide thin film transistor (M1) is different from the channel width of the second P-channel oxide thin film transistor (M3), (see the Table in Col. 3 for the widths of M1 and M3 where M1 = 5µ and M3 = 20µ).
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (USP 4,464,587) in view of Yin et al. (US 2010/0264956).
For claim 1, Figure 16 of Suzuki et al. teaches a CMOS inverter circuit (14-17) comprising: a first P-channel transistor (16), having a gate terminal for receiving an input signal (IN) and a source terminal connected to a power supply voltage (VDD supply); a second P-channel transistor (14), having a gate terminal for receiving the same input signal (IN) as the first P-channel transistor (16), and having a source terminal connected in series with a drain terminal of the first P-channel transistor (16); and a first N-channel transistor (15), connected in series with the drain terminal of the second P-channel transistor (14), having a gate terminal for receiving the same input signal (IN) as the first and second P-channel transistors (16 and 14), and having a source terminal connected to ground (ground E, by way of transistor 17). Figure 16 of Suzuki et al. does not teach the transistors (P-channel and N-channel transistors) in the inverter of Figure 16 comprise oxide thin-film transistors. However, Yin et al. teaches oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the inverter in Figure 16 of Suzuki et al. so that the transistors (P-channel and N-channel transistors) in the inverter in the Figure 16 of Suzuki et al. comprise oxide thin-film transistors for the purpose of low power applications because oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]). Thus, this combination/modification teaches all the limitations of claim 1 including the transistors comprise oxide thin-film transistors.
For claim 3, Figure 16 of Suzuki et al. in the above combination/modification teaches a second N-channel oxide thin film transistor (18) connected to a node P (12), wherein the node P (12) is a node where the drain of the first P-channel oxide film transistor (16) and the source of the second P-channel oxide thin transistor (14) are connected in series (at node 12).
For claim 4, Figure 16 of Suzuki et al. teaches wherein a drain of the second N-channel oxide thin film transistor (18) is connected to the node P (12) and a source of the second N-channel oxide thin transistor (18) is connected to ground (ground).
For claim 5, Figure 16 of Suzuki et al. teaches wherein the input voltage applied to a gate terminal of the second N-channel oxide thin film transistor (input voltage applied to gate of N-channel oxide transistor 18) is the same as the input voltage of the first N-channel oxide thin film transistor (input voltage IN applied to gate of N-channel oxide transistor 15) (this is because the input voltage O2 at the gate of the second N-channel oxide transistor 18 is the same as the input voltage IN due to the signal IN is inverted through inverter 14-17 to generate signal O1 and then the signal O1 is inverted to generate signal O2, and thus signal O2 is the same as input signal IN).
Response to Arguments
Applicant’s arguments filed 02/25/26 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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/Long Nguyen/
Primary Examiner
Art Unit 2842