DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 08/12/26.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/12/26 has been entered.
Claim Objections
Claims 1, 2, 6 and 7 are objected to because of the following informalities:
In claim 1, line 26, “to ground” should be changed to “to said ground” (see line 23).
Claims 2, 6 and 7 are objected to because they depend on claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (USP 4,464,587) in view of Yin et al. (US 2010/0264956).
For claim 1, Figure 16 of Suzuki et al. teaches a CMOS inverter circuit (14-17) comprising: an input node (IN) configured to receive an input signal (IN); an output node (O1); a first P-channel transistor (16) having a gate terminal connected to the input node (IN), a source terminal connected to a power supply voltage (VDD), and a drain terminal connected to a node P (12); a second P-channel transistor (14) having a gate terminal connected to the input node (IN), a source terminal connected to the node P (12), and a drain terminal connected to the output node (O1); a first N-channel transistor (17) having a gate terminal connected to the input node (IN), a drain terminal connected to the output node (O1, by way of transistor 15), and a source terminal directly connected to ground (GND) (ground E); and a second N-channel transistor (18) having a gate terminal connected to the input node (IN, via the transistors 14-17 and inverter 33; this is because the input voltage O2 at the gate of the second N-channel oxide transistor 18 is the same as the input voltage IN due to the signal IN is inverted through inverter transistors 14-17 to generate signal O1 and then the signal O1 is inverted to generate signal O2, and thus signal O2 is the same as input signal IN), a drain terminal connected to the node P (12), and a source terminal directly connected to ground (GND), wherein the gate terminals of the first and second P-channel transistors (16 and 14) and the first and second N-channel transistors (17 and 18) are connected to one another at the input node (IN; note that the gate of the second NMOS transistor 18 is connected to the input node IN via the transistors 14-17 and inverter 33 because the claim does not recited “directly connection”).
Figure 16 of Suzuki et al. does not teach the transistors (P-channel and N-channel transistors) in the inverter of Figure 16 comprise oxide thin-film transistors. However, Yin et al. teaches oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]).
Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the inverter in Figure 16 of Suzuki et al. so that the transistors (P-channel and N-channel transistors) in the inverter in the Figure 16 of Suzuki et al. comprise oxide thin-film transistors for the purpose of low power applications because oxide thin-film transistor are formed using a low temperature process and has excellent mobility (Yin et al., Col. [0117]). Thus, this combination/modification teaches all the limitations of claim 1 including the transistors comprise oxide thin-film transistors.
For claim 7, Figure 16 of Suzuki et al. in the above combination/modification teaches wherein, when the input signal (IN) applied to the input node (IN) is at the power supply voltage (VDD), the second N-channel oxide thin-film transistor (18) pulls the node P (12) toward ground (GND) (ground E), such that a gate-to-source voltage of the second P-channel oxide thin- film transistor (18) is greater than zero (when IN is VDD, then the voltage O2 is also VDD), thereby turning off the second P-channel oxide thin- film transistor (14).
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (USP 4,464,587) in view of Yin et al. (US 2010/0264956), and further in view of Huang (USP 5,121,014).
For claim 2, the combination/modification of Suzuki et al. in view of Yin et al. as discussed in claim 1 above teaches all the limitations of this claim except for wherein a channel width of the first P-channel oxide thin-film transistor is different from a channel width of the second P-channel oxide thin-film transistor.
However, Figures 1, 2 and 4 of Huang each teach a circuit that includes an inverter (M1, M3, M4, M5) that includes a first P-channel transistor (M1) and a second P-channel transistor (M3), wherein the channel width of the first P-channel transistor (M1) is different from the channel width of the second P-channel transistor (M3), (see the Table in Col. 3 for the widths of M1 and M3 where M1 = 5µ and M3 = 20µ) for controlling the delay of circuit (see Col. 3, lines 20-60).
Therefore, it would have been obvious to one having ordinary skilled in the art at a time before the invention was effectively filed to modify the CMOS inverter of the combination/modification of Suzuki et al. in view of Yin et al. as discussed in claim 1 above so that a channel width of the first P-channel oxide thin-film transistor is different from a channel width of the second P-channel oxide thin-film transistor, as taught by Huang, so as to control the delay of the inverter to a specific desire delay. Thus, this combination/modification teaches all the limitations of claim 2.
For claim 6, the combination/modification (Suzuki et al. in view of Yin et al., and further in view of Huang) as discussed in claim 2 above teaches wherein the channel widths of the first and second P-channel oxide thin-film transistors (16 and 14 of Figure 16 of Suzuki et al. in the above combination/modification) are selected to adjust a voltage of the node P (12) (this is because the on-resistance and the current flowing through a transistor depends on the sizing (channel width) of the transistor).
Response to Arguments
Applicant's arguments filed on 08/12/26 have been fully considered but they are not persuasive.
Applicant argues that: “Amended Claim 1 explicitly requires that: “the gate terminals of the first and second P-channel oxide thin-film transistors and the first and second N-channel oxide thin-film transistors are connected to one another at the input node.” This is a structural limitation requiring a direct, physical connection of all four gate terminals to a single physical input node. In contrast, in Figure 16 of Suzuki, the gate terminal of transistor 18 is physically connected to the output terminal 02 of the load inverter 33, while the gates of the inverter transistors (14-17) are connected to the input terminal IN. The Examiner's assertion that 02 is "the same as" the input IN because the signal is double-inverted confuses *logical state equivalence* with *physical circuit connection*. In physical circuit design, a terminal driven by an active feedback stage (such as 02) is structurally and electrically distinct from a primary input node (IN). Because the gate of transistor 18 in Suzuki is physically isolated from the input node IN by multiple intervening active inverter stages (14-17 and 33), Suzuki structurally lacks the claimed common physical connection at the input node”.
However, the above argument is not persuasive because the claim does not specifically recite “the gate terminals of the first and second P-channel oxide thin-film transistors and the first and second N-channel oxide thin-film transistors are directly connected to one another at the input node”, and in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “this is a structural limitation requiring a direct, physical connection of all four gate terminals to a single physical input node”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Note that, for broadest reasonable interpretation, Suzuki, in Figure 16, teaches that the gate terminals of the first and second P-channel transistors (16 and 14) and the first and second N-channel transistors (17 and 18) are connected to one another at the input node (IN; note that the gate of the second NMOS transistor 18 is connected to the input node IN via the transistors 14-17 and inverter 33 because the claim does not recited “directly connection”).
Applicant further argues that “If a person of ordinary skill in the art (PHOSITA) were to modify Suzuki's circuit by disconnecting the gate of transistor 18 from the feedback node O2 and connecting it directly to the input node IN (as required by Claim 1), the state-dependent feedback mechanism would be completely destroyed. Without this feedback loop, the circuit would lose its hysteresis characteristics and fail to function as a Schmitt trigger”. However, this argument is not persuasive because, in the 103 rejection above, there was not proposed “to modify Suzuki's circuit by disconnecting the gate of transistor 18 from the feedback node O2 and connecting it directly to the input node IN” as applicant’s argument.
Applicant further argues that “In Figure 16 of Suzuki, the source of the first N-channel transistor 15 is not directly connected to ground; instead, it is connected to ground *by way of transistor 17*”. However, this argument is not persuasive because, in the rejection above, the first N-channel transistor is now the NMOS transistor 17 in Figure 16 of Suzuki.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights