DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Summary of Response
2. The 09/08/2025 response includes: (a) the specification including the abstract is currently amended; (b) claims 1-3, 7, 11 and 19 are currently amended; (c) claims 4-6, 9-10, 12-18 and 20 are original; (d) claim 8 is canceled; and (e) the grounds for rejection set forth in the 06/09/2025 office action are traversed. Claims 1-7 and 9-20 are currently pending and an office action follows:
Response to Arguments
3. Applicant's arguments filed 09/08/2025 have been fully considered but they are not persuasive.
Applicant argues that Li does not teach “a shield electrode, connected to the constant voltage line, the shield electrode and the constant voltage line configured to keep potential on the gate signal portion” and “the constant voltage line comprises the first initialization signal line” (09/08/2025 response p. 12).
In support of this, Li’s figure 5 is edited to show a line from drawn points a to b (09/08/2025 response p. 13), however this contradicts what examiner included in the 06/09/2025 nonfinal rejection as being the constant voltage line, i.e., the line directly below VDD or the line directly above VI (see below figure).
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Applicant argues that the wiring providing VDD transmits multiple DC power signals and therefore cannot be considered a constant voltage line (09/08/2025 response p. 12). Examiner disagrees as DC signals are inherently constant, VCC is a well-known term meaning voltage, and applicant’s claims are not limited to a constant voltage line that only carries a single constant voltage at all operating times.
Also, examiner’s new grounds of rejection of all claims is based on the constant voltage line being the line directly above VI, that transmits initialization or reset signals over time (¶¶0044, 0048) modified by the teaching of new prior art reference U.S. Patent Pub. No. 2021/0399078 A1 to Um et al. (“Um”) of initialization signals provided by a constant voltage line(line directly above Vint)(FIG. 2; ¶0069). Um also discloses a shield electrode connected to an initialization voltage line (¶¶0112, 0125), however examiner did not need to combine this teaching because as examiner pointed out in the 06/09/2025, the shield electrode is coupling connected, as opposed to electrically or operationally connected, to the signal line1 in which the signal line is modified by Um to be a constant voltage line.
Thus, in summary, all of applicant’s claims remain rejected.
Claim Objections
4. Claims 1-7 and 9-20 are objected to because of the following informalities:
Claim 1 at line 21 includes “provide initialization signal” that is grammatically incorrect. This objection may be overcome, for example, by amending it to “provide an initialization signal”. Appropriate correction is required. This objection applies to claims 2-7 and 9-18 that depend upon claim 1.
Claim 19 at line 22 includes “provide initialization signal” that is grammatically incorrect. This objection may be overcome, for example, by amending it to “provide an initialization signal”. Appropriate correction is required. This objection applies to claim 20 that depends upon claim 19.
Claim Rejections – 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-7, 9-10, 12 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2022/0367587 A1 to Li in view of U.S. Patent Pub. No. 2021/0399078 A1 to Um et al. (“Um”).
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As to claim 1, Li discloses a display panel (FIGs. 2, 12; ¶¶0029, 0053, 0056), comprising:
a base substrate(111)(FIG. 12; ¶¶0056);
a pixel unit(1011s in 100b)(FIGs. 3, 5: 101; ¶¶0030, 0036-0037, 0042), located on the base substrate(111)(FIG. 12; ¶¶0053, 0056) and comprising a plurality of pixel circuits(1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) comprises a driving transistor(M1)(FIG. 5; ¶0043), and the driving transistor(M1)(FIG. 5; ¶0043) comprises a gate electrode(G1)(FIG. 5: M1; ¶0045);
a first gate signal line(horizontal wire to the left of G1)(FIG. 5: M1; ¶0045), connected to the gate electrode(G1)(FIG. 5: M1; ¶0045) of the driving transistor(M1)(FIG. 5; ¶0043), wherein the first gate signal line(horizontal wire to the left of G1)(FIG. 5: M1; ¶0045) and the gate electrode(G1)(FIG. 5: M1; ¶0045) constitute a gate signal portion(horizontal wiring to the left of G1, G1)(FIG. 5: M1; ¶0045);
a signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067);
a shield electrode(15)(FIG. 11: 151, 152, 153; ¶0068), connected to the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0068-0070 – the shield electrode 15/151-153 is coupling connected to the line directly above VI), the shield electrode(15)(FIG. 11; ¶0068) and the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067) are configured to keep potential on the gate signal portion(horizontal wiring to the left of G1, G1)(FIG. 5: M1; ¶¶0045, 0048, especially – “the initialization signals transmitted by the initialization signal wire VI are read into the gate G1 of the driving transistor”, 0072, especially – “preventing the parasitic capacitance from making a potential of the gate of the driving transistor M1 unstable”);
a light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
an opaque display region(100b)(FIGs. 2-3; ¶¶0028-0029, 0031, 0033), located on at least one side of the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
a first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), a second pixel circuit(a second 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), and a first light-emitting element(110a1 or 100a2 in 100b)(FIG. 3; ¶0032), located in the opaque display region(100b)(FIGs. 2-3; ¶¶0028-0029, 0031, 0033), the plurality of pixel circuits(1011s in 110b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) comprise the first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) and the second pixel circuit(a second 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042);
a second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶0032), located in the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
wherein the first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) is connected to the first light-emitting element(110a1 or 100a2 in 100b)(FIG. 3; ¶¶0032, 0036), and the second pixel circuit(a second 1011 in 100b connected to 100a1 or 100a2 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) is connected to the second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶¶0032, 0036),
wherein at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a first initialization signal line(line directly above VI)(FIG. 5; ¶0044), the first initialization signal line(line directly above VI)(FIG. 5; ¶0044) is configured to provide initialization signal to the pixel unit(1011s in 100b)(FIGs. 3, 5: 101, M4, M7; ¶¶0030, 0036-0037, 0042, 0048, 0051), and the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067) comprises the first initialization signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067).
Li does not expressly disclose a constant voltage line.
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Um discloses a constant voltage line(line directly above Vint)(FIG. 2; ¶0069).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Li with Um to provide a display panel that uses less power and has a simplified fabrication.
As to claim 2, Li and Um teach the display panel according to claim 1, as applied above.
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Li further discloses wherein the second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶0032) and the second pixel circuit(a second 1011 in 100b connected to 100a1 or 100a2 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) connected to the second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶¶0032, 0036) are located in a same row and are connected with each other (FIGs. 3, 5: a second 1011 in 100b connected to 100a1 or 100a2 in 100b; ¶¶0030, 0036, 0042) through a conductive line(102)(FIG. 3; ¶0030).
As to claim 3, Li and Um teach the display panel according to claim 2, as applied above.
Li further discloses wherein one terminal(lower terminal of 102)(FIG. 3; ¶0030) of the conductive line(102)(FIG. 3; ¶0030) is connected to the second pixel circuit(a second 1011 in 100b connected to 100a1 or 100a2 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), and another terminal(upper terminal of 102)(FIG. 3; ¶0030) of the conductive line(102)(FIG. 3; ¶0030) is connected to the second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶¶0032, 0036); the conductive line(102)(FIG. 3; ¶0030) extends from the opaque display region(100b)(FIGs. 2-3; ¶¶0028-0029, 0031, 0033) to the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032).
As to claim 4, Li and Um teach the display panel according to claim 2, as applied above.
Li further discloses wherein the conductive line(102)(FIG. 3; ¶0030) is made of a transparent conductive material (¶0071).
As to claim 5, Li and Um teach the display panel according to claim 1, as applied above.
Li further discloses comprising: a plurality of second light-emitting elements(100a2s)(FIG. 3; ¶0032), located in the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032); a light-transmitting region(region of 100a1 between adjacent 100a2s)(FIG. 3; ¶0032), located between two adjacent second light-emitting elements(adjacent 100a2s)(FIG. 3; ¶0032) of the plurality of second light-emitting elements(100a2s)(FIG. 3; ¶0032),
wherein a plurality of light-transmitting regions(region of 100a1 adjacent to region of 100a2)(FIG. 3; ¶0032) are connected to each other to form a continuous light-transmitting region (FIG. 3: region of 100a1 adjacent to region of 100a2 are coupling connected to form a continuous light-transmitting region of a color formed by a combination of the colors displayed by these two regions; ¶0032).
As to claim 6, Li and Um teach the display panel according to claim 1, as applied above.
Li further discloses further comprising a second gate signal line(vertical wire directly above M4)(FIG. 5: M1; ¶0045), wherein, the second gate signal line(vertical wire directly above M4)(FIG. 5: M1; ¶0045) is connected with the first gate signal line(horizontal wire to the left of G1)(FIG. 5: M1; ¶0045); the gate electrode(G1)(FIG. 5: M1; ¶0045), the first gate signal line(horizontal wire to the left of G1)(FIG. 5: M1; ¶0045) and the second gate signal line(vertical wire directly above M4)(FIG. 5: M1; ¶0045) constitute a gate signal portion(vertical wire directly above M4, horizontal wire to the left of G1, G1)(FIG. 5: M1; ¶0045).
As to claim 7, Li and Um teach the display panel according to claim 1, as applied above.
Li further discloses wherein at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a first reset transistor(M4 or M7)(FIG. 5; ¶0043), the first reset transistor(M4 or M7)(FIG. 5; ¶0043) is connected to a second gate signal line(line providing SCAN(n-1) or line providing SCAN(n))(FIG. 5; ¶0044), a first electrode(M4’s left electrode or M7’s left electrode)(FIG. 5; ¶0043) of the first reset transistor(M4 or M7)(FIG. 5; ¶0043) is connected to the first initialization signal line(line directly above VI)(FIG. 5; ¶0044), and the second gate signal line(line providing SCAN(n))(FIG. 5; ¶0044) is multiplexed as a second electrode of the first reset transistor(M4 or M7)(FIG. 5; ¶¶0043, 0048, 0051).
As to claim 9, Li and Um teach the display panel according to claim 7, as applied above.
Li further discloses further comprising a first power supply line(horizontal line directly below VDD or line directly above VI)(FIG. 5; ¶¶0044, 0067), wherein the first power supply line(horizontal line directly below VDD or line directly above VI)(FIG. 5; ¶¶0044, 0067) is configured to provide a first power supply voltage(VDD or VI)(FIG. 5; ¶¶0044, 0067) to the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042, 0070), the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a storage capacitor(C)(FIG. 5; ¶0043), a first terminal(C1)(FIG. 5; ¶0045) of the storage capacitor(C)(FIG. 5; ¶0045) is connected to the gate electrode(G1)(FIG. 5: M1; ¶0045) of the driving transistor(M1)(FIG. 5; ¶0043), and a second terminal(C2)(FIG. 5; ¶0049) of the storage capacitor(C)(FIG. 5; ¶0049) is connected to the first power supply line(VDD or VI)(FIG. 5; ¶¶0044, 0067 – C2 is directly connected to VDD and coupling connected to VI).
As to claim 10, Li and Um teach the display panel according to claim 9, as applied above.
Li and Um further teach wherein the constant voltage line comprises the first power supply line (Li: FIG. 5: line directly above VI; ¶¶0044, 0067; Um: FIG. 2: line directly above Vint; ¶0069).
The motivation to combine the additional teachings of Um is for the same reasoning set forth above for claim 1.
As to claim 12, Li and Um teach the display panel according to claim 1, as applied above.
Li further discloses further comprising a gate line(line providing SCAN[n])(FIG. 5; ¶0044) and a data line(line providing D(m))(FIG. 5; ¶0044), wherein the gate line(line providing SCAN[n])(FIG. 5; ¶0044) is configured to provide a scan signal (¶0044) to the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), and the data line(line providing D(m))(FIG. 5; ¶0044) is configured to provide a data signal (¶0044) to the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042); and the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a data writing transistor(M2)(FIG. 5; ¶0045), a gate electrode(M2’s gate electrode)(FIG. 5; ¶0045) of the data writing transistor is connected to the gate line(line providing SCAN[n])(FIG. 5; ¶0044), a first electrode(M2’s right electrode)(FIG. 5; ¶0045) of the data writing transistor(M2)(FIG. 5; ¶0045) is connected to the data line(line providing D(m))(FIG. 5; ¶0044), and a second electrode(M2’s left electrode)(FIG. 5; ¶0045) of the data writing transistor(M2)(FIG. 5; ¶0045) is connected to a first electrode(M1’s top electrode)(FIG. 5; ¶0043) of the driving transistor(M1)(FIG. 5; ¶0043).
As to claim 14, Li and Um teach the display panel according to claim 1, as applied above.
Li further discloses further comprising a second reset control signal line(line providing SCAN(n-1) or line providing SCAN(n))(FIG. 5; ¶0044), wherein the at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a second reset transistor(M4 or M7)(FIG. 5; ¶0043), a gate electrode(M4’s gate or M7’s gate)(FIG. 5; ¶0043) of the second reset transistor(M4 or M7)(FIG. 5; ¶0043) is connected to the second reset control signal line(line providing SCAN(n-1) or line providing SCAN(n))(FIG. 5; ¶0044), a first electrode(M4’s lower electrode or M7’s left electrode)(FIG. 5; ¶0043) of the second reset transistor(M4 or M7)(FIG. 5; ¶0043) is connected to a second initialization signal line(line from VI to M4’s lower electrode or line from VI to M7’s left electrode)(FIG. 5; ¶0044), and a second electrode(M4’s upper electrode or M7’s right electrode)(FIG. 5; ¶0043 of the second reset transistor(M4 or M7)(FIG. 5; ¶0043) is connected to a first electrode(top electrode of OLED)(FIG. 5; ¶0045) of the light-emitting element(OLED)(FIG. 5; ¶0045 – M7’s right electrode is directly and electrically connected to OLED’s top electrode and M4’s top electrode is coupling connected to OLED’s top electrode).
As to claim 15, Li and Um teach the display panel according to claim 1, as applied above.
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Li further discloses comprising: a plurality of first pixel circuits(1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042), a plurality of second pixel circuits(1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042), and a plurality of first light-emitting elements(110a1 or 100a2 in 100b)(FIG. 3; ¶0032), located in the opaque display region(100b)(FIGs. 2-4; ¶¶0028-0029, 0031, 0033, 0038-0039), and;
a plurality of second light-emitting elements(110a2s or 100a1s in 100a)(FIG. 3; ¶0032), located in the light-transmitting display region(100a)(FIGs. 2-4; ¶¶0029, 0032, 0038-0039);
wherein the plurality of second pixel circuits(1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) are distributed among the plurality of first pixel circuits(1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) with intervals.
As to claim 16, Li and Um teach the display panel according to claim 15, as applied above.
Li further discloses wherein, at least one first pixel circuit of the plurality of first pixel circuits(one of 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) is connected to at least one first light-emitting element of the plurality of first light-emitting elements(one of 110a1 or 100a2 in 100b; OLED)(FIGs. 3, 5; ¶¶0032, 0045), and an orthographic projection of the at least one first pixel circuit(one of 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) on the base substrate(111)(FIG. 12; ¶¶0056) at least partially overlaps with an orthographic projection of the at least one first light-emitting element(one of 110a1 or 100a2 in 100b; OLED)(FIGs. 3, 5; ¶¶0032, 0045 – FIG. 5 shows OLED overlaps pixel circuit that drives it) on the base substrate(111)(FIG. 12; ¶¶0056); and
the at least one first pixel circuit(one of 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) is configured to provide a driving signal for a connected first light-emitting element(one of 110a1 or 100a2 in 100b; OLED)(FIGs. 3, 5; ¶¶0032, 0045) to drive the connected first light-emitting element(one of 110a1 or 100a2 in 100b; OLED)(FIGs. 3, 5; ¶¶0032, 0045) to emit light (¶0045).
As to claim 17, Li and Um teach the display panel according to claim 15, as applied above.
Li further discloses wherein, at least one second pixel circuit(one of: 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) of the plurality of second pixel circuits(1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) is connected to at least one second light-emitting element(one of: 110a2s or 100a1s in 100a)(FIG. 3; ¶0032) of the plurality of second light-emitting elements(110a2s or 100a1s in 100a)(FIG. 3; ¶0032) through a conductive line(102)(FIG. 3; ¶0030); and the at least one second pixel circuit(one of: 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) is used to provide a driving signal for a connected second light-emitting element(one of: 110a2s or 100a1s in 100a)(FIG. 3; ¶¶0032, 0045) to drive the connected second light-emitting element to emit light(one of: 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042, 0045).
As to claim 18, Li and Um teach the display panel according to claim 17, as applied above.
Li further discloses wherein: an orthographic projection of the at least one second pixel circuit(one of: 1011s in 100b in edited FIG. 4 above)(FIGs. 3-5; ¶¶0030, 0036, 0038-0039, 0042) on the base substrate(111)(FIG. 12; ¶¶0056) and an orthographic projection of the at least one second light-emitting element(one of: 110a2s or 100a1s in 100a)(FIG. 3; ¶0032) on the base substrate(111)(FIG. 12; ¶¶0056) have no overlapping region (FIGs. 3-5: one of: 1011s in 100b in edited FIG. 4 above provides a driving signal to at least one second light-emitting element {FIG. 3: 110a2s or 100a1s in 100a} via connection {FIG. 3: 102} and thus do not overlap in orthographic projection view on the substrate; ¶¶0030, 0036, 0038-0039, 0042).
As to claim 19, Li discloses a display device (FIG. 2; ¶0029), comprising a display panel (FIGs. 2, 12; ¶¶0029, 0053, 0056), the display panel (FIGs. 2, 12; ¶¶0029, 0053, 0056) comprising: a base substrate(111)(FIG. 12; ¶¶0056); a pixel unit(1011s in 100b)(FIGs. 3, 5: 101; ¶¶0030, 0036-0037, 0042), located on the base substrate(111)(FIG. 12; ¶¶0053, 0056) and comprising a plurality of pixel circuits(1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) comprises a driving transistor(M1)(FIG. 5; ¶0043), and the driving transistor(M1)(FIG. 5; ¶0043) comprises a gate electrode (G1)(FIG. 5: M1; ¶0045);
a first gate signal line(wire to the left of G1)(FIG. 5: M1; ¶0045), connected to the gate electrode(G1)(FIG. 5: M1; ¶0045) of the driving transistor (M1)(FIG. 5; ¶0043), wherein the first gate signal line(wire to the left of G1)(FIG. 5: M1; ¶0045) and the gate electrode(G1)(FIG. 5: M1; ¶0045) constitute a gate signal portion(wiring to the left of G1, G1)(FIG. 5: M1; ¶0045);
a signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067)
a shield electrode(15)(FIG. 11: 151, 152, 153; ¶0068), connected to the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0068-0070 – the shield electrode 15/151-153 is coupling connected to the line directly above VI), the shield electrode(15)(FIG. 11; ¶0068) and the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067) are configured to keep potential on the gate signal portion(horizontal wiring to the left of G1, G1)(FIG. 5: M1; ¶¶0045, 0048, especially – “the initialization signals transmitted by the initialization signal wire VI are read into the gate G1 of the driving transistor”, 0072, especially – “preventing the parasitic capacitance from making a potential of the gate of the driving transistor M1 unstable”);
a light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
an opaque display region(100b)(FIGs. 2-3; ¶¶0028-0029, 0031, 0033), located on at least one side of the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
a first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), a second pixel circuit(a second 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042), and a first light-emitting element(110a1 or 100a2 in 100b)(FIG. 3; ¶0032), located in the opaque display region(100b)(FIGs. 2-3; ¶¶0028-0029, 0031, 0033), the plurality of pixel circuits(1011s in 110b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) comprises the first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) and the second pixel circuit(a second 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042);
a second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶0032), located in the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032);
wherein the first pixel circuit(a first 1011 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) is connected to the first light-emitting element(110a1 or 100a2 in 100b)(FIG. 3; ¶¶0032, 0036), and the second pixel circuit(a second 1011 in 100b connected to 100a1 or 100a2 in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) is connected to the second light-emitting element(110a1 or 100a2 in 100a)(FIG. 3; ¶¶0032, 0036),
wherein at least one of the plurality of pixel circuits(one or more of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042) further comprises a first initialization signal line(line directly above VI)(FIG. 5; ¶0044), the first initialization signal line(line directly above VI)(FIG. 5; ¶0044) is configured to provide initialization signal to the pixel unit(1011s in 100b)(FIGs. 3, 5: 101, M4, M7; ¶¶0030, 0036-0037, 0042, 0048, 0051), and the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067) comprises the first initialization signal line(line directly above VI)(FIG. 5; ¶¶0044, 0067).
Li does not expressly disclose a constant voltage line.
Um discloses a constant voltage line(line directly above Vint)(FIG. 2; ¶0069).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Li with Um to provide a display panel that uses less power and has a simplified fabrication.
As to claim 20, Li and Um teach the display device according to claim 19, as applied above.
Li further discloses further comprising a sensor (¶0086), wherein the sensor (¶0086) is located on one side of the display panel (FIGs. 2, 12; ¶¶0029, 0053, 0056, 0086) and located in the light-transmitting display region(100a)(FIGs. 2-3; ¶¶0029, 0032, 0086).
7. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2022/0367587 A1 to Li in view of U.S. Patent Pub. No. 2021/0399078 A1 to Um et al. (“Um”) as applied to claim 9 above, in view of U.S. Patent Pub. No. 2010/0079419 A1 to Shibusawa.
As to claim 11, Li and Um teach the display panel according to claim 9, as applied above.
Li further discloses further comprising a third power supply line(horizontal line directly below VDD)(FIG. 5: line directly above VI is the first power supply line; ¶¶0044, 0067), wherein the third power supply line(horizontal line directly below VDD or)(FIG. 5: line directly above VI is the first power supply line; ¶¶0044, 0067) is connected in parallel with the first power supply line(line directly above VI)(FIG. 5; ¶¶0044, 0067), the shield electrode(15)(FIG. 11: 151, 152, 153; ¶0068) and the third power supply line(horizontal line directly below VDD)(FIG. 5: line directly above VI is the first power supply line; ¶¶0044, 0067) are formed (FIG. 11: 15, 151, 152, 153, horizontal line directly below VDD; ¶¶0044, 0067-0068), and the third power supply line(horizontal line directly below VDD)(FIG. 5: line directly above VI is the first power supply line; ¶¶0044, 0067) and the first power supply line(line directly above VI)(FIG. 5; ¶¶0044, 0067) extend in a same direction(vertical direction).
Li and Um do not expressly disclose the shield electrode and the third power supply line are formed as an integrated structure.
Shibusawa discloses the shield electrode and the power supply line are formed as an integrated structure (¶0050, especially – “the shield electrode 36 is integrally formed with the high potential voltage line Vdd”).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Li and Um with Shibusawa to provide a display panel that as fewer parts leading to lower fabrication costs.
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2022/0367587 A1 to Li in view of U.S. Patent Pub. No. 2021/0399078 A1 to Um et al. (“Um”) as applied to claim 9 above, in view of U.S. Patent Pub. No. 2022/0122540 A1 to Choi et al. (“Choi”).
As to claim 13, Li and Um teach the display panel according to claim 9, as applied above.
Li further discloses further comprising a block(122)(FIGs. 6, 8; ¶0057), wherein the block(122)(FIGs. 6, 8; ¶0057) is connected to the first power supply line(horizontal line directly below VDD or line directly above VI)(FIG. 5; ¶¶0044, 0067 – 122 is coupling connected to first power supply line {FIG. 5: horizontal line directly below VDD or line directly above VI}),
the at least one of the plurality of pixel circuits(at least one of: 1011s in 100b)(FIGs. 3, 5; ¶¶0030, 0036, 0042, 0070) further comprises a data input transistor(M2)(FIG. 5; ¶0045), a first electrode(M2’s left electrode)(FIG. 5; ¶0045) of the data input transistor(M2)(FIG. 5; ¶0045) is connected to a second electrode(M1’s top electrode)(FIG. 5; ¶0043) of the driving transistor(M1)(FIG. 5; ¶0043), a second electrode(M2’s right electrode)(FIG. 5; ¶0045) of the data input transistor(M2)(FIG. 5; ¶0045) is connected to the gate electrode(M1’s gate)(FIG. 5; ¶0043 – M2’s right electrode is electrically connected and coupling connected to M1’s gate electrode) of the driving transistor(M1)(FIG. 5; ¶0043), and a gate electrode(M2’s gate)(FIG. 5; ¶0045) of the data input transistor(M2)(FIG. 5; ¶0045) is connected to the gate line(line providing SCAN[n])(FIG. 5; ¶0044);
the gate electrode(M1’s gate electrode)(FIG. 5; ¶0043 of the driving transistor(M1)(FIG. 5; ¶0043) is connected to the second electrode(M2’s right electrode)(FIG. 5; ¶0045) of the data input transistor(M2)(FIG. 5; ¶0045) through the first gate signal line(horizontal wire to the left of G1)(FIG. 5: M1; ¶0045 – M1’s gate electrode is coupling connected to M2’s right electrode via the horizontal wire to the left of G1),
the data input transistor(M2)(FIG. 5; ¶0045) comprises a first channel(M2’s left electrode)(FIG. 5; ¶0045) and a second channel(M2’s right electrode)(FIG. 5; ¶0045), and the first channel and the second channel are connected with each other by a conductive connection portion(112a, 122)(FIG. 6; ¶¶0054, 0057); and
an orthographic projection of the block(122)(FIGs. 6, 8; ¶0057) on the base substrate(111)(FIG. 12; ¶¶0053, 0056) at least partially overlaps with an orthographic projection of the conductive connection portion(112a, 122)(FIG. 6; ¶¶0054, 0057) of data input transistor(M2)(FIG. 5; ¶0045) on the base substrate(111)(FIG. 12; ¶¶0053, 0056).
Li does not expressly disclose the at least one of the plurality of pixel circuits further comprises a threshold compensation transistor.
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Choi disclose the at least one of the plurality of pixel circuits(SP)(FIG. 2; ¶0060) further comprises a threshold compensation transistor(SWT)(FIG. 2; ¶¶0062, 0065, 0078, 0156-0157, 0162).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Li and Um with Choi (i.e., to modify Li’s data input terminal so that it inputs data signals that are threshold voltage compensated) to provide a display panel that provides uniform brightness.
Other Relevant Prior Art
9. Other relevant prior art includes:
(i) U.S. Patent Pub. No. 2020/0343312 A1 to Ryu discloses an initialization power line may be electrically connected to a light-blocking conductive pattern that causes the at least one of a pixel’s transistors electrical characteristics to improve resulting in for example more current flowing through the display element (¶¶0289-0298).
(ii) U.S. Patent Pub. No. 2021/0043709 A1 to Kim discloses a shield electrode that is connected to the gates of both a driving transistor and an initialization transistor (¶¶0115-0116).
(iii) U.S. Patent Pub. No. 2014/0167009 A1 to Lee et al. discloses a shield electrode set at a DC voltage level connected to a gate electrode of a driving transistor and a data line (¶¶0020-0021).
Conclusion
10. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIRK W HERMANN whose telephone number is (571) 270-3891. The examiner can normally be reached on Monday-Friday, 10am-7pm, EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIRK W HERMANN/Primary Examiner, Art Unit 2621
1 a shield electrode(15)(FIG. 11: 151, 152, 153; ¶0068), connected to the signal line(line directly above VI)(FIG. 5; ¶¶0044, 0068-0070 – the shield electrode 15/151-153 is coupling connected to the line directly above VI).