Prosecution Insights
Last updated: April 19, 2026
Application No. 18/751,604

SYSTEM, APPARATUS AND METHOD FOR FINE-GRAIN ADDRESS SPACE SELECTION IN A PROCESSOR

Non-Final OA §103
Filed
Jun 24, 2024
Examiner
CYGIEL, GARY W
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
3y 4m
To Grant
86%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
405 granted / 533 resolved
+21.0% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
20 currently pending
Career history
553
Total Applications
across all art units

Statute-Specific Performance

§101
5.1%
-34.9% vs TC avg
§103
42.4%
+2.4% vs TC avg
§102
29.2%
-10.8% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 533 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue et al. (US PGPub No. 2019/0042463), hereinafter referred to as SHANBHOGUE in view of KUMAR et al. (US PGPub 2019/0370050 – Published as WO2018/152688 on 30AUG2018). Consider Claim 1, SHANBHOGUE teaches a processor comprising: a decoder to decode (SHANBHOGUE, e.g., ¶0047, decode logic to decode) an enqueue command instruction from software in a virtual machine (SHANBHOGUE, e.g., Fig 23; ¶0304-0306), the enqueue command instruction having a first field to represent a destination operand and a second field to represent a source memory operand (SHANBHOGUE, e.g., ¶0304-0306, enqueue a 64-byte command (from the specified source) and put it in the shared work queue (to a specified destination).); and an execution circuit coupled to the decoder (SHANBHOGUE, e.g., ¶0047, execute logic to execute (decoded) instructions.), wherein in response to the decoded enqueue command instruction, the processor is to: read command data from a memory location identified by the source memory operand (SHANBHOGUE, e.g., ¶0305, 64-byte command is written to a shared work queue;Fig 23, 64-byte command written to the SWQ is not an enqueue command and, therefore, must have been read from a specified source location.). SHANBHOGUE further describes plural PASIDs (see, e.g., ¶0138, N PASIDs), including a PASID in the enqueued command (see, e.g., Fig. 23), and writing the command with a PASID to an identified destination (see, e.g., ¶0305). However, SHANBHOGUE fails to expressly teach a mechanism to use first process address space identifier (PASID) information from a configuration register to access a PASID translation structure to obtain a second PASID; format the command data to include the second PASID; and write the formatted command data to a location identified by the destination operand. KUMAR describes systems and methods for managing virtual systems with a plurality of address identifiers and is considered analogous prior art. KUMAR teaches a mechanism to use first address space identifier (PASID) information from a configuration register to access a ASID translation structure to obtain a second ASID (KUMAR, e.g.,Fig 5A:525; Fig 3:330;¶0047, hardware managed memory space with configuration information is considered analogous to the claimed configuration register.); format the command data to include the second ASID (KUMAR, e.g., ¶0050, guest ASID replaced with host ASID.); and write the formatted command data to a location identified by the destination operand (KUMAR, e.g., ¶0058, modified work descriptor is submitted to the SWQ.). Further, SHANBHOGUE appears to suggest to the reader that the identity mapping used is required because there is no guest to host PASID translation (SHANBHOGUE, e.g., ¶0306). It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to modify the PASID mapping of SHANBHOGUE with the ASID translation mechanism of KUMAR because it is a known alternative for identifying a PASID and is therefore a matter of design choice. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gary W Cygiel whose telephone number is (571)270-1170. The examiner can normally be reached Monday - Thursday 11am-3pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Gary W. Cygiel/Primary Examiner, Art Unit 2137
Read full office action

Prosecution Timeline

Jun 24, 2024
Application Filed
Sep 22, 2025
Non-Final Rejection — §103
Dec 19, 2025
Response after Non-Final Action
Dec 19, 2025
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
86%
With Interview (+9.7%)
3y 4m
Median Time to Grant
Low
PTA Risk
Based on 533 resolved cases by this examiner. Grant probability derived from career allow rate.

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