DETAILED ACTION
This action is in response to the application filed on 24 June 2024.
Claims 1-20 are under examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim 1 is provisionally rejected under the judicially created doctrine of nonstatutory obviousness-type double patenting over claim 1 of U.S. Patent No. 12,021,759 (the ‘759 patent). Both claims are directed to performing a first and second operation on a packet using first and second hardware offload units of a host computer that executes multiple machines. The patented claim recites configuring a program to identify a first offload unit and configuring the first offload unit to identify a second offload unit and pass the packet to it, while the pending claim recites identifying the first offload unit, configuring it to process an action stage without processor involvement, performing the first operation, and identifying the second offload unit. The distinctions are drawn to scope rather than inventive concept, and the pending claim represents an obvious variation of the patented claim. A terminal disclaimer would overcome this rejection.
Claim 2 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of U.S. Patent No. 12,021,759. The patented claim expressly requires the program to “provide the packet to the first hardware offload unit” and to “provide the packet to the second hardware offload unit.” The pending claim adds “providing the packet to the second hardware offload unit,” which is fully encompassed by and obvious over the patented disclosure of providing the packet to both offload units.
Claim 3 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim explicitly recites “configuring the second hardware offload unit to perform the second operation on the packet,” which is identical in substance to the limitation of claim 3.
Claim 4 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim requires configuring the first offload unit to identify and hand off the packet to the second offload unit. Writing to a register of the second offload unit is an obvious implementation detail of such configuration.
Claim 5 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim requires configuring the first offload unit to cause the second offload unit to perform the next operation. Writing to memory to trigger a notification is an obvious design choice for effecting such handoff.
Claim 6 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. Once the patented claim requires sequential processing through multiple offload units, extending the chain to a third offload unit is an obvious variant.
Claim 7 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim already requires a “program, over which the plurality of machines execute,” making association with a hypervisor an obvious implementation.
Claim 8 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim encompasses virtual machines by broadly reciting “plurality of machines.” Specifying that the machine is a virtual machine does not render the claim patentably distinct.
Claim 9 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. As with claim 8, identifying the machine as a container or Pod is merely naming an obvious species of “machine” and does not patentably distinguish the claim.
Claim 10 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim’s “first operation” is unrestricted and encompasses forwarding, middlebox functions, or any packet operation. Naming specific types of operations does not confer patentability.
Claim 11 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim requires configuring the program to identify which offload unit must apply which operation. Using match records and associated action records is an obvious implementation of such identification.
Claim 12 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. A “next action record identifying the second hardware offload unit” is a routine way to implement the patented requirement that the first offload unit identify the second.
Claim 13 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim’s “actions stage” inherently includes multiple sub-operations processed by the offload pipeline. Reciting that the first operation consists of multiple sub-operations is not a patentable distinction.
Claim 14 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim requires the first offload unit to “process an actions stage,” which is conventionally implemented using a pipeline of action stages. Naming the pipeline explicitly is an obvious variation.
Claim 15 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. Claim 15 merely places the same method in system form, reciting a host computer, processing units, memory, and hardware offload units. These are the same structural components implicit in the patented method, expressed in apparatus form.
Claim 16 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. As with claims 8 and 9, specifying that the machine is a virtual machine or container does not patentably distinguish from the patented claim’s “plurality of machines.”
Claim 17 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. Writing to a register of the second offload unit is an obvious implementation for configuring it to perform the second operation, as required in the patented claim.
Claim 18 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. Writing to memory is another obvious mechanism for causing the second offload unit to act, and is a routine alternative to writing to a register.
Claim 19 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. Triggering a notification to the second offload unit without CPU involvement is an obvious implementation of handing off the packet as required by the patented claim.
Claim 20 is provisionally rejected under the doctrine of nonstatutory ODP over claim 1 of the ’759 patent. The patented claim encompasses any type of hardware offload unit, and specifying that offload units include an FPGA, GPU, or smart NIC does not impart patentable distinctness.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under U.S.C. 103(a) as being unpatentable over Dalal et al (US 9,460,031) in view of McDonald (US Pub. 2014/0244983).
Regarding claim 1, Dalal teaches executing a plurality of machines on a host computer, the host computer comprising a plurality of hardware offload units and one or more processing units, because Dalal discloses servers (machines) 120 executing on a host with offload processor modules 140 (3:34–61; Fig. 1-0). Dalal teaches identifying the first hardware offload unit to perform a first operation on a packet associated with the first machine, because offload processor 140a is identified to process a packet for a specific server (3:47–61). Dalal teaches configuring the first hardware offload unit to process a first action stage without involving the one or more processing units, because offload processors execute packet-processing actions independently of host CPUs (10:39+). Dalal teaches performing the first operation using the first hardware offload unit on the packet (3:47–61). Dalal teaches identifying, by the first hardware offload unit, the second hardware offload unit to perform a second operation on the packet because offload processor 140a may pass packet context to offload processor 140b for further operations (7:40–41). Dalal does not explicitly disclose dynamic selection rules for the second offload unit; McDonald teaches scheduling tasks among multiple processing units based on load, task type, and operational criteria (Fig. 4; steps 408–412; ¶¶62–63). It would have been obvious to combine McDonald with Dalal to improve efficiency by enabling hardware offload units to dynamically select the next offload unit for continued processing based on known scheduling criteria.
Regarding claim 2, Dalal teaches providing the packet to the second hardware offload unit, because Dalal discloses transferring packet context from one offload processor to another (7:40–41).
Regarding claim 3, Dalal teaches configuring the second hardware offload unit to perform the second operation, because the second offload processor resumes and continues processing based on received context (7:40–41; 10:39+).
Regarding claim 4, Dalal teaches configuring the first hardware offload unit to write to a register of the second hardware offload unit, because Dalal discloses programmable registers within offload processors and the ability for one offload processor to write required context/state for another (3:47–61).
Regarding claim 5, Dalal teaches configuring the first hardware offload unit to write to a memory of the host computer to cause a notification to be provided to the second hardware offload unit without using the processing units, because Dalal teaches memory-based signaling and context transfer occurring entirely between offload units (7:40–41; 3:47–61).
Regarding claim 6, Dalal teaches providing the packet to a third hardware offload unit by the second hardware offload unit, because Dalal describes multi-stage offload processing chains where packets may be handed through multiple offload processors (e.g., 140a → 140b → 140c) (7:40–41).
Regarding claim 7, Dalal teaches the first operation is associated with a hypervisor executing on the host computer, as Dalal discloses offload processors operating in virtualized environments controlled by hypervisors (3:34–47).
Regarding claim 8, Dalal teaches the first machine comprises a virtual machine, because Dalal expressly references virtual machines operating on host servers (3:34–47).
Regarding claim 9, Dalal does not explicitly disclose a container or Pod. McDonald teaches distributed execution environments including containers and operating contexts equivalent to VMs (¶¶42–44). It would have been obvious to combine McDonald with Dalal because containers are well-known execution abstractions used interchangeably with VMs for packet-processing workloads, and adapting Dalal’s offloading architecture to containers is a predictable and straightforward substitution.
Regarding claim 10, Dalal teaches the first operation comprises a packet forwarding operation or a packet middlebox service operation, because Dalal discloses forwarding, switching, and middlebox-like packet-processing operations (3:34–61; 10:39+).
Regarding claim 11, Dalal teaches matching attributes of the packet to a match record, the first operation being specified by a first action record, because Dalal teaches packet classification and associated action stages in an offload pipeline (10:39+).
Regarding claim 12, Dalal teaches the match record comprises a next action record identifying the second hardware offload unit, because Dalal discloses metadata/context indicating which offload processor resumes processing next (7:40–41).
Regarding claim 13, Dalal teaches the first operation comprises a plurality of sub-operations specified by action records, because Dalal teaches multiple programmable action stages executed by offload processors (10:39+).
Regarding claim 14, Dalal teaches the first hardware offload unit comprises a plurality of action stages in a pipeline, because Dalal discloses multi-stage packet-processing pipelines in offload processors (3:34–61).
Regarding claim 15, Dalal teaches a host computer system comprising processing units, memory, and multiple hardware offload units, the processing units executing multiple machines, and performing the same sequence of identifying, configuring, and operating offload processors described in claim 1 (3:34–61; Fig. 1-0; 7:40–41). McDonald is relied on only for dynamic multi-unit scheduling logic as discussed in claim 1. Combining McDonald’s processor scheduling concepts with Dalal’s offload architecture would have been obvious to improve allocation efficiency.
Regarding claim 16, Dalal teaches the first machine comprises a virtual machine, and McDonald teaches containers (¶42–44). As discussed in claim 9, applying offload logic to containers is a predictable substitution.
Regarding claim 17, Dalal teaches the first hardware offload unit is configured to write to a register of the second hardware offload unit, because offload processors communicate via register/state passing (3:47–61; 10:39+).
Regarding claim 18, Dalal teaches the first hardware offload unit is configured to write to the memory, because offload processors store and retrieve context from host memory (7:40–41).
Regarding claim 19, Dalal teaches writing to memory causes a notification to the second hardware offload unit without using the processing units, because the state is consumed by the next offload processor without CPU intervention (3:47–61; 7:40–41).
Regarding claim 20, Dalal teaches hardware offload units may include FPGA or NIC-based accelerators (3:34–61; Fig. 1-0). McDonald teaches GPU-based offloading (¶29–31). It would have been obvious to treat FPGA, GPU, and smart NIC as interchangeable hardware offloading platforms that perform packet-processing tasks, which is a known design choice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure (see form 892).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUAT T PHUNG whose telephone number is (571)270-3126. The examiner can normally be reached on M-F 9 AM - 6 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Asad Nawaz can be reached on (571) 272-3988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Luat Phung/
Primary Examiner, Art Unit 2464