DETAILED ACTION
Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims1-10 and 15-20 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claims 1 and 15 recites the limitations " … semiconductor chip proximate to a plurality of respective target… according to claim 1" and “…sensing elements proximate to the integrated circuit… according to claim 14”. The term “proximate” is a relative term which renders the claim indefinite. The term “proximate” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The remaining claims are also rejected under 35 U.S.C. 112(b), for being dependent upon a rejected base claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1
Each of claims1-10 falls within one of the four statutory categories. See MPEP § 2106.03. For example, each of claim 1-10 falls within category of process.
Regarding Claims 1-10
Step 2A – Prong 1
Exemplary claim 1 is directed to an abstract idea of r evaluating the measured outputs.
The abstract idea is set forth or described by the following italicized limitations:
1. A method comprising:
forming a plurality of thermal sensing elements at predetermined locations on a semiconductor chip proximate to a plurality of respective target locations;
measuring a temperature of the semiconductor chip at each target location using a corresponding one of the plurality of thermal sensing elements; and
determining an operating condition of the semiconductor chip using the temperatures measured at each of the target locations,
wherein measuring the temperature of the semiconductor chip comprises:
measuring an output from each of the thermal sensing elements; and
evaluating the measured outputs using processor logic.
The bold limitations above represent a mental step because a process that can be performed by can be performed mentally and/or with pen and paper or merely data observations, evaluations, and/or judgements . Therefore, the italicized limitations fall within the subject matter groupings of abstract ideas enumerated in Section I of the 2019 Revised Patent Subject Matter Eligibility Guidance.
For example, the limitations “determining an operating condition [..]; evaluating the measured outputs [..] ” a mental step (i.e., a process that can be performed by can be performed mentally and/or with pen and paper or a mental judgment) because these limitations are merely data observations, evaluations, and/or judgements in order to re-diagnose the abnormal state.
Limitations are considered together as a single abstract idea for further analysis. (discussing Bilski v. Kappos, 561 U.S. 593 (2010)).
Step 2A – Prong 2
Claims 1 does not include additional elements (when considered individually, as an ordered combination, and/or within the claim as a whole) that are sufficient to integrate the abstract idea into a practical application.
For example, first additional first element is “forming a plurality of thermal sensing elements at predetermined locations on a semiconductor chip proximate to a plurality of respective target locations; measuring a temperature of the semiconductor chip at each target location using a corresponding one of the plurality of thermal sensing elements; wherein measuring the temperature of the semiconductor chip comprises: measuring an output from each of the thermal sensing elements” to be performed, at least in-part, these additional elements appear to only add insignificant extra-solution activity (e.g., data gathering and or pre solution activity and /or field of use) and only generally link the abstract idea to a particular field. Therefore, this element individually or as a whole does not provide a practical application. See MPEP 2106.05(f).
In view of the above, the “additional elements” individually do not provide a practical application of the abstract idea. Furthermore, the “additional elements” in combination amount to a plurality of generic component with software, where such computers and software amount to mere instructions to implement the abstract idea on a computer(s) and/or mere use of a generic computer component(s) as a tool to perform the abstract idea. Therefore, these elements in combination do not provide a practical application. The combination of additional elements does no more than generally link the use of the abstract idea to a particular technological environment, and for this additional reason, the combination of additional elements does not provide a practical application of the abstract idea. Noting MPEP 2106.04(d)(I): “It is notable that mere physicality or tangibility of an additional element or elements is not a relevant consideration in Step 2A Prong Two. As the Supreme Court explained in Alice Corp., mere physical or tangible implementation of an exception does not guarantee eligibility. Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 224, 110 USPQ2d 1976, 1983-84 (2014) ("The fact that a computer ‘necessarily exist[s] in the physical, rather than purely conceptual, realm,’ is beside the point")”.
Step 2B
Claims1 does not include additional elements, when considered individually and as an ordered combination, that are sufficient to amount to significantly more than the abstract idea. For example, the limitation of Claim 1 contains additional elements that are, i.e. “thermal sensing element, semiconductor chip, processor”, generic devices, which are well understood, routine and convention (see background of current discloser and IDS and PTO 892) and MPEP 2106.05(d))The reasons for reaching this conclusion are substantially the same as the reasons given above in § Step 2A – Prong 2. For brevity only, those reasons are not repeated in this section. See MPEP §§ 2106.05(g) and MPEP §§2106.05(II).
.
Dependent Claims 2-10
Dependent claims 2-10 fail to cure this deficiency of independent claim 1 (set forth above) and are rejected accordingly. Particularly, claims 2-10 recite limitations that represent (in addition to the limitations already noted above) either the abstract idea or an additional element that is merely extra-solution activity, mere use of instructions and/or generic computer component(s) as a tool to implement the abstract idea, and/or merely limits the abstract idea to a particular technological environment.
For examples:
3. The method of claim 1, wherein the predetermined locations are determined from a power density distribution of the semiconductor chip..
The bold limitations above represent a mental step because a process that can be performed by can be performed mentally and/or with pen and paper or merely data observations, evaluations, and/or judgements . Therefore, the italicized limitations fall within the subject matter groupings of abstract ideas enumerated in Section I of the 2019 Revised Patent Subject Matter Eligibility Guidance.
The dependent claims do not include any additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements, as described above with respect to Step 2A Prong 2, merely amount to a general purpose computer system that attempts to apply the abstract idea in a technological environment, limiting the abstract idea to a particular field of use, and/or merely performs insignificant extra-solution activit(ies).
For examples claim 2, 4-7:generic structural component of semiconductor circuit. These elements individually does not provide a practical application. In view of the above, the “additional element” individually or combine does not provide a practical application of the abstract idea. see MPEP 2106.05(d).
For examples claim 8-10: to be performed, at least in-part, these additional elements appear to only add insignificant extra-solution activity (e.g., data gathering and or pre solution activity and /or field of use) and only generally link the abstract idea to a particular field. Therefore, this element individually or as a whole does not provide a practical application. See MPEP 2106.05(f)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-20 is/are rejected under 35 U.S.C. 102(a)(1/(2)) as being anticipated by Rajwan et al. (US 2023/0031415).
Regarding Claim 1. Rajwan teaches a method comprising(abstract; claim 9):
forming a plurality of thermal sensing elements at predetermined locations (111: fig.2) on a semiconductor chip (200: fig. 2) proximate to a plurality of respective target locations(Hotspot: 205, fig.2);
measuring a temperature of the semiconductor chip at each target location using a corresponding one of the plurality of thermal sensing elements(receive temperature readings:[0031]); and
determining an operating condition of the semiconductor chip using the temperatures measured at each of the target locations(determining that a reported temperature has exceeded a particular threshold value: [0032], [0028]),
wherein measuring the temperature of the semiconductor chip comprises([0031]):
measuring an output from each of the thermal sensing elements([0031]-[0032]); and
evaluating the measured outputs using processor logic(101-121: fig. 2; [0032]-[0035]).
Regarding Claim 2. Rajwan further teaches the thermal sensing elements comprise thermal ring oscillators([0026], [0030]).
Regarding Claim 3. Rajwan further teaches the predetermined locations are determined from a power density distribution of the semiconductor chip (closer to Hotspots: fig. 2; According to definition “High power density frequently creates hotspots—localized areas of extreme heat on microchips”; supported by US 20170110384 A1, [0027], “A thermal hotspot is an area of high temperature caused by situations such as higher power densities at various areas on a die 120” ).
Regarding Claim 4. Rajwan further teaches the semiconductor chip comprises a central processing unit (CPU)(121: fig.2; [0030]).
Regarding Claim 5. Rajwan further teaches at least one of the target locations comprises a hotspot(205: fig.1).
Regarding Claim 6. Rajwan further teaches at least one of the target locations(205) is located proximate to a central processing unit(processor:[0030]).
Regarding Claim 7. Rajwan further teaches comprising altering operation of the semiconductor chip based on the temperatures at the target locations(thermal control: [0030]).
Regarding Claim 8. Rajwan further teaches altering operation of the semiconductor chip comprises one or more of changing voltage, changing clock frequency, and changing a number of instructions executed per cycle(e.g. control signals and/or voltage control signals:[0030]-[0035], [0028]).
Regarding Claim 9. Rajwan further teaches the temperature of the semiconductor chip at each target location is measured simultaneously([0031]-[0032]).
Regarding Claim 11. Rajwan teaches a system comprising (200: fig.2):
a memory integrated circuit(functional circuit 205: fig.2; These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory), [0118]);
a processing integrated circuit communicatively coupled to the memory integrated circuit and configured to access data stored in the memory integrated circuit(The functional circuit 205 may be one of a number of different types of circuitry, such as an execution unit of a general purpose processor, a graphics processing unit, and so on. The circuit may be designated as a hotspot due to its operations generating a larger amount of heat relative to at least some other circuits on IC 200 [0030]); and
a plurality of thermal sensing elements(111: fig.2), each comprising a digital MOS-based element, located within at least one of(ΔVbe-type temperature sensors based on bandgap circuitry: [0026]):
semiconductor material of the memory integrated circuit(These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory), [0118]), or
semiconductor material of the processing integrated circuit([0030]).
Regarding Claim 12. Rajwan further teaches the plurality of thermal sensing elements are located within the semiconductor material of the processing integrated circuit(111: fig. 2); and
the processing integrated circuit comprises a central processing unit([0030]).
Regarding Claim 13. Rajwan further teaches the plurality of thermal sensing elements are located within the semiconductor material of the memory integrated circuit(111, 205: fig. 11; These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory),); and
the memory integrated circuit comprises random access memory(0118).
Regarding Claim 14. Rajwan further teaches a system on a chip that comprises the memory integrated circuit and the processing integrated circuit(1106: fig.11; [0030], [0118]).
Regarding Claim 15. Rajwan teaches a semiconductor chip comprising(1106: fig.11):
an integrated circuit(200: fig.2); and
a plurality of thermal sensing elements proximate to the integrated circuit(111: fig.2), wherein the thermal sensing elements each comprise a digital MOS-based element(ΔVbe-type temperature sensors based on bandgap circuitry: [0026]).
Regarding Claim 16. Rajwan further teaches the thermal sensing elements comprise ring oscillators([0026], [0030]).
Regarding Claim 17. Rajwan further teaches each of the plurality of thermal sensing elements is located proximate to a respective hot spot(205: fig.1).
Regarding Claim 18. Rajwan further teaches comprising a remediation module connected to each of the plurality of thermal sensing elements.
Regarding Claim 19. Rajwan further teaches the remediation module is configured to execute one or more thermal remediation tasks(101: fig. 2; [0032]-[0033]).
Regarding Claim 20. Rajwan further teaches the one or more thermal remediation tasks are selected from the group consisting of changing voltage, changing clock frequency, and changing a number of instructions executed per cycle(e.g. control signals and/or voltage control signals:[0030]-[0035], [0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rajwan in view of Schweikert et al. (US 2020/0321262).
Regarding Claim 10. Rajwan further teaches measuring the temperature of the semiconductor chip at each target location comprises measuring the temperatures at each thermal sensing element(111: fig.2).
Rajwan silent about sensing element at a measurement interval of less than approximately 20 microseconds.
Schweikert thermal sensing element at a measurement interval of less than approximately 20 microseconds([0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the invention of Rajwan, sensing element at a measurement interval of less than approximately 20 microseconds, as taught by Schweikert, so as to more of the expensive power area of a power semiconductor chip has to be provided to do so.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a) US 20130166885:In modern complex processors, unexpected thermal events such as localized hotspots can occur when a small area of the processor is continuously active when executing a given set of instructions. The resulting power density increases the temperature of the chip and causes a hotspot to form in the processor. These hotspots may cause spatial thermal gradients that affect the performance and lifetime of the chip.
b) US 20130020716: disclose there usually exists hotspots, areas of higher power density, where most of the processing takes place, which results in a temperature gradient across the chip. These areas of higher heat and power density need to be kept within a set temperature range in order for the chip to perform properly and to pass quality and specification tests at the end of manufacturing.
c) US 7419299: methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece
d) US 6674623: In a microcomputer equipped with a built-in temperature sensor.
e) US 20180156672: The operation of the CMOS based temperature sensor is based on electron movement from emitter to collector.
f) US 20210272827: the temperature profile is created from the temperature data of 3000 points acquired between the time t11 and the time 15. Since the data collection cycle is 20 microseconds,
g) US 20130306871 A1: Temperature measurement system 234 includes the ultrafast radiometer 102, identical to that disclosed in the incorporated U.S. Pat. No. 7,445,382, configured to produce real-time temperature measurements of the device side 122 of the wafer 120 during the irradiance pulse 600 at a sampling rate of 100 kHz, so that the device side temperature is measured once every ten microseconds. (In this embodiment the backside temperature measurement system 236 also continues to measure the temperature of the substrate side 124 of the wafer, before, during and after the irradiance pulse 600. In the present embodiment, as backside temperature measurements are not used for real-time feedback control of the irradiance pulse 600, the backside temperature measurement system measures the substrate side temperature at a slower sampling rate of 1 kHz.)
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD K ISLAM whose telephone number is (571)270-0328. The examiner can normally be reached M-F 9:00 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby A Turner can be reached at 571-272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD K ISLAM/ Primary Examiner, Art Unit 2857
Prosecution Insights