DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments, filed Apr 23, 2026, with respect to how the newly amended claim features of claim 1 differ from the prior art cited in the last office have been fully considered. These arguments are found to be persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in this office action using a different secondary reference Pub No. US 20160093090 A1 (also called Shin).
Allowable Subject Matter
Claims 3-7, 8-10, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11-13, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Clark et al. (U.S. Patent Publication No. 20210407171), hereinafter as Clark, in view of Shin et al. (U.S. Patent Publication No. 20160093090), hereinafter as Shin.
Regarding independent Claim 1, Clark discloses a processing system, comprising:
a memory circuit configured to store a bounding volume hierarchy (BVH) structure (Clark paragraph [0137], element 304) that comprises ray tracing context data (Clark Fig. 1, element 104 in paragraph [0005]); and a processing circuit configured to: generate the BVH structure (Clark Fig. 1, element 106; paragraph [0137], element 306) comprising generating a plurality of nodes (Clark Fig. 1, element 106 in paragraph [0005]); and generate a stream of frames by traversing the BVH structure, comprising: in response to detecting that a ray intersects with a first bounding volume (BV) (Clark Fig. 4; paragraph [0136]) or primitive corresponding to a first node of the BVH structure (Clark Fig. 1, element 108 in paragraph [0005]).
Clark alone does not teach all the remaining claim features of claim 1. However, Shin in combination with Clark teaches the claimed:
checking a first discard value generated based on whether the first BV or primitive overlaps with at least one BV or primitive corresponding to at least one sibling node along a path of the ray (Shin shows a hierarchical structure with sibling nodes in figure 8, e.g. node L2 is the sibling node or R2. Also please see Shin in [0105] “In an operation 920, the ray tracing core 100 determines whether a node among nodes above the intersecting leaf node includes child nodes that overlap each other. In other words, the ray tracing core 100 determine whether an overlap flap of a node from among traversed nodes is set to “0.” A node of which overlap flag is set to “0” includes overlapped child nodes. If there is a node of which overlap flag is set to “0” from among traversed nodes, the method proceeds to an operation 930. If overlap flag of every node in a traversed path is set to “1” and there is an object intersecting ray data from among objects belonging to the final leaf node, traversal of the acceleration structure is terminated at this point.”); and
in response to the first discard value indicating that the at least one sibling node does not overlap with the first BV or primitive along the path of the ray (This is shown in Shin in figure 8, e.g. the sibling node of node R2 is node L2. The first discard value “0” in node L2 does not overlap with the first BV or primitive along the path of the ray), omitting traversal of the at least one sibling node by removing entries corresponding to the at least one sibling node from a BVH traversal stack (Shin teaches this in [0127] “… The traverser 120 may skip and not traverse nodes that do not overlap one another among the nodes popped from the stack 121. In other words, after the traverser 120 finds an intersected leaf node, the traverser 120 does not traverse nodes that do not overlap each other from among nodes popped from the stack 121 and terminates traversal.”
In this passage, the skipping the traversal of nodes that do not overlap one another corresponds to the claimed “omitting traversal of the at least one sibling node”.
In this passage, the nodes popped from the stack 121 correspond to the claimed “by removing entries corresponding to the at least one sibling node from a BVH traversal stack”);
Clark and Shin are both considered to be analogous to the claimed invention because they are both in the same field of creating an accelerated process of Ray Tracing through a tree structure by skipping nodes. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Clark to incorporate the teachings of Shin and provide an accelerated ray tracing process by checking whether the ray intersects with the overlap region based on the ray context data (Shin paragraph [0012]). Doing so would reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claim 2, Clark further discloses the processing system of Claim 1, wherein traversing the BVH structure (Clark Fig. 3, elements 310 and 320; Fig. 4-6; Fig. 13; paragraphs [0134], [0143], [0151], [0152]) further comprises: in response to the first discard value indicating that a second node of the at least one sibling node is not to be discarded, retaining an entry corresponding to the second node in the BVH traversal stack and traversing the second node (Shin teaches in [0110], in reference to figure 8 “Since the child nodes R1 and L1 of the root node R do not overlap each other, overlap flag of the root node R is set to “1.” The ray tracing core 100 traverses a near node, which is the node L1, from the root node. The ray tracing core 100 pushes the node R1 to a stack and stores the node R1. Therefore, the ray tracing core 100 may later pops the node R1 stored in the stack and traverses the node R1.” Nodes L1 and R1 are sibling nodes, and R1 corresponds to the claimed “second node of the at least one sibling node” ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the BVH traversal stack as taught by Shin with the system of Clark in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claim 13, the combination of Clark and Shin further teaches the method of claim 12, wherein the second BV or primitive overlaps with the first BV or primitive at a location outside of a path of the ray (Shin teaches in paragraph [0100] “The node L2 includes a child node R4 and a child node L4. Since the node R4 and the node L4 overlap each other, an overlap flag of the node R1 is set to “0.” The acceleration structure generating apparatus 200 sets an overlap flag of the node L2 to 0 to mark that the child nodes thereof overlap each other.” In Figure 10, the child nodes R4 and L4 overlap outside the path of the ray).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claim 15, the combination of Clark and Shin further teaches the method of claim 11, wherein omitting the traversal of the at least one sibling node for the ray (Clark Fig. 7a; paragraphs [0153], [0156]) further comprises: removing at least one entry of the BVH traversal stack corresponding to the at least one sibling node (Shin teaches this in [0127] “… The traverser 120 may skip and not traverse nodes that do not overlap one another among the nodes popped from the stack 121. In other words, after the traverser 120 finds an intersected leaf node, the traverser 120 does not traverse nodes that do not overlap each other from among nodes popped from the stack 121 and terminates traversal.”
In this passage, the skipping the traversal of nodes that do not overlap one another corresponds to the claimed “omitting traversal of the at least one sibling node”.
In this passage, the nodes popped from the stack 121 correspond to the claimed “by removing at least one entry corresponding to the at least one sibling node from a BVH traversal stack”);
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claim 18, the combination of Clark and Shin further teaches the method of claim 17, wherein generating the discard value (Please refer to claim 1) further comprises: setting an overlap stack pointer to a current stack pointer of a BVH stack (“First-in-last-out (FILO)” Clark paragraph [0134]) corresponding to the BVH structure in response to identifying that the second BV or primitive overlaps with the first BV or primitive along the path of the ray (Shin teaches in paragraph [0100] “The node L2 includes a child node R4 and a child node L4. Since the node R4 and the node L4 overlap each other, an overlap flag of the node R1 is set to “0.” The acceleration structure generating apparatus 200 sets an overlap flag of the node L2 to 0 to mark that the child nodes thereof overlap each other.” In Figure 12 of Shin, the child nodes R4 and L4 overlap along the path of the ray. This figure also shows the bounding volumes (BV) for nodes R4 and L4 as well as their overlap).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claim 20, the combination of Clark and Shin further teaches the method of claim 16, wherein at least one BV or primitive corresponding to the at least one sibling node overlaps with the first BV or primitive outside of the path of the ray (Shin teaches in paragraph [0100] “The node L2 includes a child node R4 and a child node L4. Since the node R4 and the node L4 overlap each other, an overlap flag of the node R1 is set to “0.” The acceleration structure generating apparatus 200 sets an overlap flag of the node L2 to 0 to mark that the child nodes thereof overlap each other.” In Figure 10, the child nodes R4 and L4 overlap outside the path of the ray).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0136] and Clark paragraph [0004]).
Regarding claims 11 and 16, both are corresponding method of claim 1, thus they are rejected for the same rationale as set forth in claim 1 above.
Regarding claims 12 and 17, both have similar limitations as claim 2, therefore they are rejected under the same rationale as set forth in claim 2 above.
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Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Clark in view of Shin further in view of Vaidyanathan et al. (U.S. Patent Publication No.20210287429), hereinafter as Vaidyanathan.
Regarding claim 19, the combination of Clark, Shin, and Vaidyanathan further teaches the method of claim 18, wherein omitting the traversal of the at least one sibling node (Clark abstract; skipping sub-trees based on intersection tests in paragraphs [0007], [0013], 0018], [0053-0055], [0058-0059] of “next pointers “ paragraphs [0153], [0154]) is performed in response to determining that all of the at least one sibling node corresponds to stack positions in the BVH stack below a stack position referred to by the overlap stack pointer (Vaidyanathan abstract; paragraphs [0531], [0551], [0525]) .
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0136] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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SARAH Y. LEE
Examiner
Art Unit 2616
/DANIEL F HAJNIK/Supervisory Patent Examiner, Art Unit 2616
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