Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 06/24/2024 fails to comply with 37 CFR 1.97(c) because it lacks a timing statement as specified in 37 CFR 1.97(e). It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, 11-14, 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Clark et al. (U.S. Patent Publication No. 20210407171), hereinafter as Clark, in view of Shin et al. (U.S. Patent Publication No.20170116775), hereinafter as Shin.
Regarding independent Claim 1, Clark discloses a processing system, comprising:
a memory circuit configured to store a bounding volume hierarchy (BVH) structure (Clark paragraph [0137], element 304) that comprises ray tracing context data (Clark Fig. 1, element 104 in paragraph [0005]); and a processing circuit configured to: generate the BVH structure (Clark Fig. 1, element 106; paragraph [0137], element 306) comprising generating a plurality of nodes (Clark Fig. 1, element 106 in paragraph [0005]); and generate a stream of frames by traversing the BVH structure, comprising: in response to detecting that a ray intersects with a first bounding volume (BV) (Clark Fig. 4; paragraph [0136]) or primitive corresponding to a first node of the BVH structure (Clark Fig. 1, element 108 in paragraph [0005]).
While Clark fails to teach an action based on a region of overlap, Shin teaches checking a first discard value generated based on overlaps between the first BV or primitive (Shin abstract; paragraphs [0010], [0102], [0114], [0116]; Claims 1, 3) and at least one BV or primitive corresponding to at least one sibling node (Shin abstract, paragraph [0020] ); and in response to the first discard value indicating that at least one sibling node is to be discarded, omitting traversal of at least one sibling node (Shin Claims 1, 3).
Clark and Shin are both considered to be analogous to the claimed invention because they are both in the same field of creating an accelerated process of Ray Tracing through a tree structure by skipping nodes. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Clark to incorporate the teachings of Shin and provide an accelerated ray tracing process by checking whether the ray intersects with the overlap region based on the ray context data (Shin paragraph [0027]; Claims 1, 3). Doing so would reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0008] and Clark paragraph [0004]).
Claims 11 and 16 are corresponding method, thus they are rejected for the same rationale as set forth in claim 1 above.
Regarding claim 2, Clark further discloses the processing system of Claim 1, wherein traversing the BVH structure (Clark Fig. 3, elements 310 and 320; Fig. 4-6; Fig. 13; paragraphs [0134], [0143], [0151], [0152]) further comprises: in response to the first discard value indicating that a second node is not to be discarded, traversing the second node (Clark claim 2; paragraph [0014]).
Regarding claims 12 and 17, both have similar limitations as claim 2, therefore they are rejected under the same rationale as set forth in claim 2 above.
Regarding claim 8, the combination of Clark and Shin teaches the processing system of claim 1, wherein traversing the BVH structure (Clark paragraphs [0129], [0164]) further comprises:
generating a BVH stack of entries corresponding to respective nodes of the plurality of nodes and corresponding BVs or primitives to check for a closest hit for the ray (Clark paragraphs [0150], [0151], [0208], [0209]); and
Shin further teaches managing a first entry of the BVH stack, wherein the first entry corresponds to the first node and the first BV or primitive and comprises the first discard value (Shin claims 1, 3; paragraphs [0010], [0016], [0020], [0026]; Figs 5).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0008] and Clark paragraph [0004]).
Regarding claim 13, the combination of Clark and Shin further teaches the method of claim 12, wherein the second BV or primitive overlaps with the first BV or primitive (Shin paragraph [0112]) at a location outside of a path of the ray (Shin Fig. 6, element 540).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0008] and Clark paragraph [0004]).
Regarding claim 14, the combination of Clark and Shin further teaches the method of claim 11, wherein the discard value (Shin paragraphs [0010], [0012]) further comprises a parent overlap value (Shin element P2 in Fig. 7, paragraph [0097]) that indicates whether a BV corresponding to a parent node of the first node overlaps with any BVs corresponding to sibling nodes of the parent node (Shin element H2 in Fig. 8 and paragraph [0108]; paragraph [0112]; claim 11).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0008] and Clark paragraph [0004]).
Regarding claim 20, the combination of Clark and Shin further teaches the method of claim 16, wherein at least one BV or primitive corresponding to the at least one sibling node overlaps (Shin paragraph [0112]) with the first BV or primitive outside of the path of the ray (Shin Fig. 6, element 540).
Since Clark and Shin are both from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Shin in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test and splitting or dividing a scene object to be rendered (Shin paragraph [0008] and Clark paragraph [0004]).
Claims 3-7, 9-10, 15, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Clark et al. (U.S. Patent Publication No. 20210407171), hereinafter as Clark, in view of Shin et al. (U.S. Patent Publication No.20170116775), hereinafter as Shin, further in view of Vaidyanathan et al. (U.S. Patent Publication No.20210287429), hereinafter as Vaidyanathan.
Regarding Claim 3, Clark and Shin fail to teach generating a plurality of discard nodes based on the first discard value. However, Vaidyanathan discloses the processing system of claim 2, wherein the processing circuit is further configured to: generate a plurality of discard values corresponding to respective nodes of the plurality of nodes and including the first discard value (Vaidyanathan paragraphs [0531], [0551], [0558]).
Clark, Shin, and Vaidyanathan are considered to be analogous to the claimed invention because they are all in the same field of Ray Tracing through a tree structure by skipping nodes. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Clark and Shin to incorporate the teachings of Vaidyanathan and provide a system of generating a plurality of nodes to be discarded based on the discard value of the parent node (Vaidyanathan paragraph [0096]). Doing so would to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 4, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 3, wherein generating the BVH structure (Vaidyanathan Abstract, paragraph [0114], [0437]) further comprises: generating the plurality of discard values (Vaidyanathan Abstract, paragraphs [0531, [0551], [0561]; claims 6, 14, 22).
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 5, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 4, wherein generating the first discard value (Shin abstract; paragraphs [0010], [0102], [0114], [0116]; Claims 1, 3) further comprises: first discard value to indicate whether the first BV or primitive overlaps with any of at least one BV or primitive (Shin paragraphs [0010], [0020], [0104], [0116-0117]; Fig. 9) corresponding to the at least one sibling node (Shin abstract; paragraphs [0010], [0093], [0112]).
Regarding claim 6, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 3, wherein traversing the BVH structure (Vaidyanathan paragraph [0110], [0338], [0413]; Fig. 33) further comprises: generating the plurality of discard values (Vaidyanathan Abstract, paragraphs [0531, [0551], [0561]; claims 6, 14, 22).
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 7, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 6, wherein generating the first discard value (Shin abstract; paragraphs [0010], [0102], [0114], [0116]; Claims 1, 3) further comprises: setting the first discard value to indicate whether the first BV or primitive overlaps with any of the at least one BV or primitive (Shin paragraphs [0010], [0020], [0104], [0116-0117]; Fig. 9) corresponding to the at least one sibling node along a path of the ray (Shin paragraphs [0111 - 0112]; Fig. 9; claim 11).
Regarding claims 9 and 15, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 8, wherein omitting the traversal (Shin paragraphs [0012], [0022], [0039]; claims 3. 13) of the at least one sibling node for the ray (Clark Fig. 7a; paragraphs [0153], [0156]) further comprises: culling at least one entry of the BVH stack corresponding to the at least one sibling node (Vaidyanathan paragraphs [0096], [0341], [0343]).
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 10, the combination of Clark, Shin, and Vaidyanathan further teaches the processing system of claim 8, wherein the first entry further comprises: an indication of a number of nodes that are pushed onto the BVH stack (Vaidyanathan paragraphs [0519], [0531]) per level of the BVH structure (Vaidyanathan abstract; paragraph [0340]; Fig. 33); and a parent overlap value (Shin element P2 in Fig. 7; paragraph [0097]) that indicates whether a BV corresponding to a parent node of the first node overlaps with any BVs corresponding to sibling nodes of the parent node (Shin paragraph [0112]; claim 11).
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 18, the combination of Clark, Shin, and Vaidyanathan further teaches the method of claim 17, wherein generating the discard value (Shin abstract; paragraphs [0010], [0102], [0114], [0116]; Claims 1, 3) further comprises: setting an overlap stack pointer to a current stack pointer of a BVH stack (“First-in-last-out (FILO)” Clark paragraph [0134]; Vaidyanathan paragraph [0549]) corresponding to the BVH structure (Vaidyanathan abstract; paragraphs [0553], [0561], [0569]; claims 1, 9, 17) in response to identifying that the second BV or primitive overlaps with the first BV or primitive (Shin paragraphs [0010], [0020], [0102], [0104], [0114]) along the path of the ray (Shin Figs. 5-8).
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Regarding claim 19, the combination of Clark, Shin, and Vaidyanathan further teaches the method of claim 18, wherein omitting the traversal of the at least one sibling node (Clark abstract; skipping sub-trees based on intersection tests in paragraphs [0007], [0013], 0018], [0053-0055], [0058-0059] of “next pointers “ paragraphs [0153], [0154]; Shin claims 3, 13) is performed in response to determining that all of the at least one sibling node corresponds to stack positions in the BVH stack below a stack position referred to by the overlap stack pointer (Shin paragraph [0113]; Vaidyanathan abstract; paragraphs [0531], [0551], [0525] .
Since Clark, Shin, and Vaidyanathan are all from the same field of endeavor, it would have been obvious to an artisan before the effective filing date of this application to incorporate the known technique of Vaidyanathan in order to reduce the large amount of computation resources needed for a ray tracing process by conducting an intersection test to reduce the number of sub-tree traversals (Shin paragraph [0008] and Clark paragraph [0004], and Vaidyanathan paragraph [0338]).
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH Y. LEE whose telephone number is (571)272-8374. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricardo Magallanes can be reached at (571) 272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARAH YEO LEE/Examiner, Art Unit 2619 /JASON CHAN/Supervisory Patent Examiner, Art Unit 2619