DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Drawings
The drawings were received on 24 July 2026. These drawings are acceptable.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. See MPEP 2111.04(II). "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016).
The term “storage unit” as recited in Claims 1, 6, and 10 has been claimed as being a part of a register, and thus has sufficient structure such that it has not been interpreted as invoking 35 USC §112(f).
The term “execution unit” as recited in Claims 1-4 and 10 has been disclosed and claimed as referring to instructions selected from the instruction set and is not a physical or structural element, and thus has not been interpreted as invoking 35 USC §112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim(s) 6 is/are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 6 recites the limitation “the operation fields and the address fields of the multiple bit operation instructions of the same type are the same, and the data fields the multiple bit operation instructions of the same type correspond to different storage units of the register”. However, Claim 1, from which Claim 6 depends (via Claims 5 and 3), recites the limitation “operation fields and address fields of the multiple bit operation instructions of the same type are the same, and data fields of the multiple bit operation instructions of the same type correspond to different storage units of the register” in Lines 16-18. Thus, Claim 6 recites no limitations that are not already present in its parent claim.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2013/0262841 to Gschwind et al. (“Gschwind”).
In reference to Claim 1, Gschwind discloses a method for accessing registers (See Figure 1 Number 15 and Figure 2 Number 24) of a device (See Figure 2 Number 21), wherein the device is connected to a CPU (See Figure 2 Number 26) via a bus (See Figure 2 bus connecting Numbers 21 and 26), the device comprises multiple registers (See Figure 1 Number 15, Figure 2 Number 24, and Paragraphs 20, 23, and 46), each of which corresponds to a different address (See Paragraph 46), each register comprises one or more storage units, each storage unit occupying one or more bits of the register, the one or more storage units share a register address (See Paragraph 46 [a register necessarily contains one or more bits that share a register address]), and the method comprises: creating an instruction set for accessing the device (See Paragraph 22); in response to operation requests from the CPU to the device, selecting corresponding instructions from the instruction set, so as to generate execution units with a minimum execution granularity corresponding to the operation requests (See Figure 5 Numbers 51 and 52 and Paragraphs 16, 20, 22, and 45 [an instruction from the instruction set is formed into an internal instruction involving specific registers and/or data by the CPU, and each internal instruction executes in a single operation cycle]); detecting the execution units (See Paragraph 46); in response to detecting that there are multiple execution units corresponding to the same type of operation request and that the multiple execution units comprise multiple bit operation instructions of the same type corresponding to the same register address, merging and optimizing the multiple execution units to generate optimized execution units, and sending the optimized execution units to the bus, wherein operation fields and address fields of the multiple bit operation instructions of the same type are the same, and data fields of the multiple bit operation instructions of the same type correspond to different storage units of the register; and performing calculation on data in the data fields of these multiple instructions of the same type corresponding to the same register address based on the operation fields of these multiple instructions of the same type to obtain data in the data field of an optimized instruction, the operation field and the address field of the optimized instruction are respectively the same as those in the operation fields and the address fields of the multiple bit operation instructions of the same type, wherein in response to not detecting that there are multiple execution units corresponding to the same type of operation request or the multiple execution units do not comprise multiple bit operation instructions of the same type corresponding to the same register address, the execution units are sent directly to the bus (See Paragraph 28).
It is noted that Claim 1 is a method claim that recites contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 2, Gschwind discloses the limitations as applied to Claim 1 above. Gschwind further discloses that the method further comprises: detecting whether the register address corresponding to the multiple bit operation instructions of the same type is marked as an optimizable address (See Paragraphs 28-29 and 46), and merging and optimizing these multiple execution units when determining that the register address is the optimizable address (See Paragraphs 27-32 and 46-47).
It is noted that Claim 2 is a method claim that recites contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 3, Gschwind discloses the limitations as applied to Claim 1 above. Gschwind further discloses that merging and optimizing the multiple execution units comprises: merging the multiple bit operation instructions of the same type corresponding to the same register address of the multiple execution units and generating the optimized instruction.
It is noted that Claim 3 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 4, Gschwind discloses the limitations as applied to Claim 3 above. Gschwind further discloses that merging and optimizing the multiple execution units comprises: sorting instructions that do not participate in merging and optimizing and the optimized instruction, so that relative order between any two instructions in the optimized execution units is the same as their relative order in the execution units before optimization.
It is noted that Claim 4 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 5, Gschwind discloses the limitations as applied to Claim 3 above. Gschwind further discloses that each of the instructions in the instruction set comprises the operation field (See Paragraph 46 [instruction such as Ld]), the address field (See Paragraph 46 [register address]), and the data field (See Paragraph 46 [constant]).
In reference to Claim 6, Gschwind discloses the limitations as applied to Claim 5 above. Gschwind further discloses that the operation fields and the address fields of the multiple bit operation instructions of the same type are the same, and the data fields the multiple bit operation instructions of the same type correspond to different storage units of the register (See Paragraph 46).
It is noted that Claim 6 is a method claim that recites previously recited limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
Allowable Subject Matter
Claim 10 is allowed.
The following is a statement of reasons for the indication of allowable subject matter: The claims are allowable in light of Applicant’s amendments and persuasive arguments. The prior art fails to disclose, either alone or in combination, all of the claimed limitations in the combinations as claimed. The most relevant prior art is Gschwind as applied in the above rejections of the corresponding method claims. Gschwind discloses a system for accessing registers (See Figure 1 Number 15 and Figure 2 Number 24) of a device (See Figure 2 Number 21), wherein the device is connected to a CPU (See Figure 2 Number 26) via a bus (See Figure 2 bus connecting Numbers 21 and 26), the device comprises multiple registers (See Figure 1 Number 15, Figure 2 Number 24, and Paragraphs 20, 23, and 46), each of which corresponds to a different address (See Paragraph 46), each register comprises one or more storage units, each storage unit occupying one or more bits of the register, the one or more storage units share a register address (See Paragraph 46 [a register necessarily contains one or more bits that share a register address]), and the access system comprises a processor configured to: create an instruction set for accessing the device (See Paragraph 22); select corresponding instructions from the instruction set in response to operation requests from the CPU to the device, so as to generate execution units with a minimum execution granularity corresponding to the operation requests (See Figure 5 Numbers 51 and 52 and Paragraphs 16, 20, 22, and 45 [an instruction from the instruction set is formed into an internal instruction involving specific registers and/or data by the CPU, and each internal instruction executes in a single operation cycle]); detect the execution units (See Paragraph 46); and in response to not detecting that there are multiple execution units corresponding to the same type of operation request or the multiple execution units do not comprise multiple bit operation instructions of the same type corresponding to the same register address, the execution units are sent directly to the bus (See Paragraph 28). However, Gschwind does not explicitly disclose that in response to detecting that there are multiple execution units corresponding to the same type of operation request and that the multiple execution units comprise multiple bit operation instructions of the same type corresponding to the same register address, merging and optimizing the multiple execution units to generate optimized execution units, and sending the optimized execution units to the bus, wherein operation fields and address fields of the multiple bit operation instructions of the same type are the same, and data fields of the multiple bit operation instructions of the same type correspond to different storage units of the register; and the processor is further configured to perform calculation on data in the data fields of these multiple instructions of the same type corresponding to the same register address based on the operation fields of these multiple instructions of the same type to obtain data in the data field of an optimized instruction, the operation field and the address field of the optimized instruction are respectively the same as those in the operation fields and the address fields of the multiple bit operation instructions of the same type. Furthermore, such features would not have been obvious to one of ordinary skill in the art in view of the prior art. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted the performing calculation on data in the data fields of the multiple bit operation instructions in accordance with the disclosure in the paragraph spanning Pages 9-10.
Response to Arguments
Applicant’s arguments, See Pages 8-12, filed 24 July 2026, with respect to Claim 10 have been fully considered and are persuasive in combination with the amendments to the claims. The rejection of Claim 10 has been withdrawn.
Applicant's arguments See Pages 8-12, filed 24 July 2026, with respect to Claims 1-6 have been fully considered but they are not persuasive. Applicant’s arguments are directed to various recited features of contingent limitations. As indicated above, since Claims 1-6 are method claims, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed. Thus, Gschwind need only disclose one of the mutually exclusive claimed contingencies (detecting that there are multiple execution units corresponding to the same type of operation request and that the multiple execution units comprise multiple bit operation instructions of the same type corresponding to the same register address, or not detecting that there are multiple execution units corresponding to the same type of operation request or the multiple execution units do not comprise multiple bit operation instructions of the same type corresponding to the same register address) and their associated limitations in order to reject Claims 1-6. As indicated above, Gschwind discloses that in response to not detecting that there are multiple execution units corresponding to the same type of operation request or the multiple execution units do not comprise multiple bit operation instructions of the same type corresponding to the same register address, no optimization, merging, or combining is performed and the execution units are sent directly to the bus (See Paragraph 28).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
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