DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. See MPEP 2111.04(II). "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016).
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “storage units” in Claims 1, 6, and 10 and “instruction creating module, configured to create…”, “execution unit generator module, configured to select…so as to generate…”, and “interpreter module, configured to detect…merge and optimize…and send…” in Claim 10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The term “execution unit” as recited in Claims 1-4 and 10 has been disclosed and claimed as referring to instructions selected from the instruction set and is not a physical or structural element, and thus has not been interpreted as invoking 35 USC §112(f).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2013/0262841 to Gschwind et al. (“Gschwind”).
In reference to Claim 1, Gschwind discloses a method for accessing registers (See Figure 1 Number 15 and Figure 2 Number 24) of a device (See Figure 2 Number 21), wherein the device is connected to a CPU (See Figure 2 Number 26) via a bus (See Figure 2 bus connecting Numbers 21 and 26), the device comprises multiple registers (See Figure 1 Number 15, Figure 2 Number 24, and Paragraphs 20, 23, and 46), each of which corresponds to a different address (See Paragraph 46), and each register comprises one or more storage units which share a register address (See Paragraph 46), and the method comprises: creating an instruction set for accessing the device (See Paragraph 22); in response to operation requests from the CPU to the device, selecting corresponding instructions from the instruction set, so as to generate execution units with a minimum execution granularity corresponding to the operation requests (See Figure 5 Numbers 51 and 52 and Paragraphs 16, 20, 22, and 45 [an instruction from the instruction set is formed into an internal instruction involving specific registers and/or data by the CPU, and each internal instruction executes in a single operation cycle]); detecting the execution units (See Paragraph 46), and when detecting that there are multiple execution units corresponding to the same type of operation request (See Paragraph 32 [integer type instructions are eligible for optimization by merging with each other]) and the multiple execution units comprises multiple instructions of the same type corresponding to the same register address (See Paragraph 46), merging and optimizing these multiple execution units to generate optimized execution units, and sending the optimized execution units to the bus (See Paragraphs 27-32 and 46-47).
It is noted that Claim 1 is a method claim that recites contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 2, Gschwind discloses the limitations as applied to Claim 1 above. Gschwind further discloses that the method further comprises: detecting whether the register address corresponding to these multiple instructions of the same type is marked as an optimizable address (See Paragraphs 28-29 and 46), and merging and optimizing these multiple execution units when determining that the register address is the optimizable address (See Paragraphs 27-32 and 46-47).
It is noted that Claim 2 is a method claim that recites contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 3, Gschwind discloses the limitations as applied to Claim 1 above. Gschwind further discloses that merging and optimizing these multiple execution units comprises: merging these multiple instructions of the same type corresponding to the same register address of the multiple execution units and generating an optimized instruction (See Paragraphs 27-32 and 46-47).
It is noted that Claim 3 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 4, Gschwind discloses the limitations as applied to Claim 3 above. Gschwind further discloses that merging and optimizing these multiple execution units comprises: sorting instructions that do not participate in merging and optimizing and the optimized instruction, so that relative order between any two instructions in the optimized execution units is the same as their relative order in the execution units before optimization (See Paragraphs 16, 18, 28, 30, and 41).
It is noted that Claim 4 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 5, Gschwind discloses the limitations as applied to Claim 3 above. Gschwind further discloses that each of the instructions in the instruction set comprises an operation field (See Paragraph 46 [instruction such as Ld]), an address field (See Paragraph 46 [register address]), and a data field (See Paragraph 46 [constant]).
In reference to Claim 6, Gschwind discloses the limitations as applied to Claim 5 above. Gschwind further discloses that operation fields and address fields of these multiple instructions of the same type are the same, and data fields of these multiple instructions of the same type correspond to different storage units of the register (See Paragraph 46).
It is noted that Claim 6 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 7, Gschwind discloses the limitations as applied to Claim 5 above. Gschwind further discloses that merging multiple instructions of the same type corresponding to the same register address comprises: performing calculation on data in the data fields of these multiple instructions of the same type corresponding to the same register address based on the operation fields of these multiple instructions of the same type to obtain data in the data field of the optimized instruction, the operation field and the address field of the optimized instruction are respectively the same as those in the operation fields and the address fields of these multiple instructions of the same type (See Paragraphs 46-47).
It is noted that Claim 7 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 8, Gschwind discloses the limitations as applied to Claim 7 above. Gschwind further discloses that these multiple instructions of the same type are bit operation instructions of the same type.
It is noted that Claim 8 is a method claim that recites further limitations of a contingent limitation of a parent claim, and thus such limitations are themselves contingent limitations. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed.
In reference to Claim 9, Gschwind discloses the limitations as applied to Claim 1 above. Gschwind further discloses that the instruction set is created in a domain specific language manner (See Paragraph 22 [the RISC instruction set of Gschwind is a defined instruction set used to access the registers of the device, and is thus created in a domain specific language manner in accordance with the definition provided on Page 7 Lines 3-5 of Applicant’s disclosure]).
11. In reference to Claim 10, Gschwind discloses a system for accessing registers (See Figure 1 Number 15 and Figure 2 Number 24) of a device (See Figure 2 Number 21), wherein the device is connected to a CPU (See Figure 2 Number 26) via a bus (See Figure 2 bus connecting Numbers 21 and 26), the device comprises multiple registers (See Figure 1 Number 15, Figure 2 Number 24, and Paragraphs 20, 23, and 46), each of which corresponds to a different address (See Paragraph 46), and each register comprises one or more storage units which share a register address (See Paragraph 46), and the access system comprises: an instruction creating module, configured to create an instruction set for accessing the device (See Paragraph 22); an execution unit generator module, configured to select corresponding instructions from the instruction set in response to operation requests from the CPU to the device, so as to generate execution units with the minimum execution granularity corresponding to the operation requests (See Figure 5 Numbers 51 and 52 and Paragraphs 16, 20, 22, and 45 [an instruction from the instruction set is formed into an internal instruction involving specific registers and/or data by the CPU, and each internal instruction executes in a single operation cycle]); an interpreter module, configured to detect the execution units (See Paragraph 46), and when multiple execution units corresponding to the same type of operation request (See Paragraph 32 [integer type instructions are eligible for optimization by merging with each other]) and comprising multiple instructions of the same type corresponding to the same register address are detected (See Paragraph 46), merge and optimize the multiple execution units to generate optimized execution units, and send the optimized execution units to the bus (See Paragraphs 27-32 and 46-47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are alternatively rejected under 35 U.S.C. 103 as being unpatentable over Gschwind as applied to Claim 7 above, and further in view of knowledge commonly known in the art, as evidenced by “OpenRISC 1000 Architecture Manual”, Revision 1.3, by Damjan Lampret et al. (“OpenRISC 1.3”).
Alternatively, in reference to Claim 8, Gschwind discloses the limitations as applied to Claim 7 above. Gschwind further discloses that these multiple instructions of the same type are RISC instruction set operations of the same type (See Paragraphs 22 and 32), but is silent as to the particular RISC instruction set used. However, upon occurrence of the contingent limitation, Gschwind does not explicitly disclose that these multiple instructions of the same type are bit operation instructions of the same type. Official Notice is taken that the use of the OpenRISC instruction set, which is a RISC instruction set that performs the bit operation instructions AND and OR, is well known in the art, as evidenced by OpenRISC 1.3 (See Pages 14-15 Section 2.2 and Pages 37-38 and 84-85).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gschwind using the well-known OpenRISC instruction set as the RISC instruction set, resulting in the invention of Claim 8, because Gschwind is silent as to the particular RISC instruction set used, and the simple substitution of the well-known OpenRISC instruction set as the RISC instruction set of Gschwind would have yielded the predictable result of performance, simplicity, low power requirements, and scalability (See Page 10 Section 1.1 of OpenRISC 1.3).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the CPU and the bus connecting the device and the CPU must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 24 June 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Conclusion
The art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. CLEARY/ Primary Examiner, Art Unit 2175
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