Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. Claims 1-20 are pending.
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim 20 is drawn towards a “A computer program product.” Applying the broadest reasonable interpretation in light of the specification and taking into account the meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art (MPEP 2111). The claim as a whole does not recite any hardware and does not fall into any of the 4 categories of invention (process, machine, manufacture, or composition of matter). The rejection may be overcome by: amending the claim(s) to include a recitation of a "non-transitory" computer program product. Appropriate correction required.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AlA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable Das Sharma (US 20140281067 A1) hereinafter Das Sharma in view of Hopgood (US 20160321227 A1) hereinafter Hopgood.
Regarding claims 1, 14 and 20 Das Sharma discloses a method for wired data transmission applied at a first end (see para. [0071] PCIe bus link) comprising:
receiving a first training bitstream sent by a second end (para. [0141] a root complex device may transmit data along each lane of a bus interface link to an endpoint device.[0142] advertising a second maximum data transmission rate at which the endpoint device may transmit data along each lane of the bus interface link to the root complex device (block 1402));
wherein the second rate range belongs to a transmission rate range supported when the second end receives data over a first data link (para. [0094] Phase 0 (e.g., of a PCIe link training and equalization procedure) may include transmitting a first set of data (e.g., TS1 Ordered Sets, Preset value(s), Hints, etc.) from the upstream port (e.g., of endpoint device 801) to the downstream port (e.g., of root complex device 803). Data may be transferred between the devices 801, 803 at a first data transmission rate. The rate at which data is transmitted in Phase 0 may be less than or equal to a first maximum data transmission rate associated with the root complex device 801 and a second maximum data transmission rate associated with the endpoint device 803. See also Fig 9);
wherein the first training bitstream comprises a second rate range (para.[0138] block 707 of method 700 provides applying the computed first set of coefficients to set up a transmitter component (e.g., transmission logic) of the link partner component of the first component during Phase of PCIe Gen 3 link training and equalization procedure. [0144] Block 1404 provides validating whether the root complex device and the endpoint device may transmit data at a second data transmission rate that is the lesser of the first maximum data transmission rate and the second maximum data transmission rate to each other along each lane of the bus interface link with a bit error rate of less than or equal to one error per every 10.sup.4 bits);
wherein data transmission is performed between the first end and the second end over the first data link, and wherein the first data link is a serial data link or a parallel data link (para. [0069] [0072] FIG. 5 is a schematic diagram illustrating of a PCIe serial point to point fabric 500 is illustrated. A basic PCIe link includes two, low-voltage, differentially driven signal pairs: a transmit pair 501/504 and a receive pair 502/503). [0184] A link training and equalization procedure for devices coupled to a bus interface link, comprising: performing Phase 0 and Phase 1 of a PCI Express Generation 3 (PCIe Gen3) link training and equalization procedure);
sending a second training bitstream to the second end, wherein the second training bitstream comprises a first rate, belonging to the second rate range (para [0135] FIG. 12 is a schematic diagram illustrating of Phase 2 of a PCIe link training and equalization procedure (block 706 of method 700). As shown, root complex device 1201 and endpoint device 1203 (having transmission logic 1202a, 1204b and receiver logic 1202b, 1204a) have transitioned to Phase 2 of the PCIe link training and equalization procedure. [0136] In Phase 2 the upstream port (e.g., of the endpoint device) adjusts the transmitter settings of the Downstream port (e.g., of the root complex device) to ensure that the upstream port receives the bit stream compliant with the target BER (e.g., less than or equal to 10.sup.-12) for all channels (e.g., lanes) of a communications link. An exemplary list of presets (5/5, 6/5, 7/4) indicate that multiple iterations may be performed to achieve the optimum link training and equalization transmitter (or receiver) settings)
Das Sharma may not explicitly discloses sending the data to the second end at the first rate over the first data link.
However, Hopgood discloses sending the data to the second end at the first rate over the first data link (para. [0067] In step 412, the Burst Link Training is again paused after the completion of the second Burst Link Training quantum. Again, the PCIe link speed is transitioned back down to Gen1/Gen2 speeds and data traffic can again be transmitted and/or received by the rootport 102 and endpoint 104. In step 414, the cycle continues as each Burst Link Training quantum is followed by a low-speed up-time for the PCIe link to handle data traffic, thereby preventing or reducing PCIe link down-time issues until the equalization training completes and the PCIe link can handle data traffic at PCIe Gen3 speeds).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Das Sharma and include sending the data to the second end at the first rate over the first data link using the teaching of Hopgood. One would have been motivated to do so in order to allow an interleave high speed equalization training with lower speed data traffic handling to avoid or minimize a risk of system delays.
Regarding claims 2 and 15, claim 1 is incorporated. Das Sharama further discloses wherein the first end corresponds to a first rate range, that is a transmission rate range supported when the first end sends the data over the first data link; and the first rate is determined based on a target rate range that is an intersection set of the first rate range and the second rate range (para. [0104] Once stored, the present disclosure provides a mechanism to compute a set of coefficients from the FS and LF values which may also be stored in a configuration and status register(s). In some embodiments, the computed set of coefficients includes a pre-cursor component (C.sub.0), cursor component (C.sub.-1), and post-cursor component (C.sub.+1). Most notably, in some embodiments of the present disclosure, the computed set of coefficients are coordinates of a midpoint along a maximum boost line. ([0108] the computed coefficients may be coordinates of a midpoint along a maximum boost line. In some embodiments, the midpoint along a maximum boost line may be computed according to the following algorithm see [0109]-[0121])
Regarding claims 3 and 16, claim 1 is incorporated. Das Sharama further discloses wherein the first end corresponds to a first rate range, that is a transmission rate range wherein the second rate range is a transmission rate range supported when the second end receives the data over the first data link; or when the first end is connected to the second end via a repeater, the second rate range is a transmission rate range jointly supported by the second end and the repeater when the second end and the repeater transmit data over the first data link, and the repeater is configured to forward, to the second end, the data sent by the first end (see Figs 9-12)
Regarding claims 4 and 17, claim 2 is incorporated. Das Sharama further discloses wherein the first training bitstream further comprises second declaration information, comprising information that the second end supports data transmission at any rate in the second rate range, and the method further comprises; sending a third training bitstream to the second end, wherein the third training bitstream comprises first declaration information comprising information that the first end supports data transmission at any rate in the first rate range ( para. [0136] In Phase 2 the upstream port (e.g., of the endpoint device) adjusts the transmitter settings of the Downstream port (e.g., of the root complex device) to ensure that the upstream port receives the bit stream compliant with the target BER (e.g., less than or equal to 10.sup.-12) for all channels (e.g., lanes) of a communications link. An exemplary list of presets (5/5, 6/5, 7/4) indicate that multiple iterations may be performed to achieve the optimum link training and equalization transmitter (or receiver) settings. See also Hopgood para. [0030], [0034] –[0035]).
Regarding claims 5 and 15, claim 2 is incorporated. Das Sharama further
wherein the first rate is a highest rate in the target rate range (see para. [0094]-[0096] and [0141] advertising a first maximum data transmission rate at which a root complex device may transmit data along each lane of a bus interface link to an endpoint device).
Regarding claim 6, claim 1 is incorporated. Das Sharama further discloses wherein the second training bitstream further comprises a speed changing identifier corresponding to the first rate, and the speed changing identifier indicates to adjust a transmission rate of the first data link (para. [0145] [0149] Block 1405 provides adjusting a transmitter setting of the root complex device and the endpoint device for each lane of the bus interface link, based upon feedback from each device, until each device transmits data to each other along each lane of the bus interface link with a bit error rate of less than or equal to one error per every 10.sup.4 bits).
Regarding claim 7, claim 2 is incorporated. Das Sharama further discloses
obtaining a corresponding first bit error rate when the data is sent to the second end at the first rate over the first data link; and when the first bit error rate is in a preset range, sending the data to the second end at the first rate over the first data link (para. [0094], [0136] Phase 0 (e.g., of a PCIe link training and equalization procedure) may include transmitting a first set of data (e.g., TS1 Ordered Sets, Preset value(s), Hints, etc.) from the upstream port (e.g., of endpoint device 801) to the downstream port (e.g., of root complex device 803). Data may be transferred between the devices 801, 803 at a first data transmission rate. The rate at which data is transmitted in Phase 0 may be less than or equal to a first maximum data transmission rate associated with the root complex device 801 and a second maximum data transmission rate associated with the endpoint device 803).
Regarding claims 8 and 19, claim 7 is incorporated. Das Sharama further discloses: when the first bit error rate exceeds the preset range, sending the data to the second end at a second rate over the first data link, wherein the second rate is in the target rate range and is less than the first rate (para. [0144] Block 1404 provides validating whether the root complex device and the endpoint device may transmit data at a second data transmission rate that is the lesser of the first maximum data transmission rate and the second maximum data transmission rate to each other along each lane of the bus interface link with a bit error rate of less than or equal to one error per every 10.sup.4 bits. [0145] Block 1405 provides adjusting a transmitter setting of the root complex device and the endpoint device for each lane of the bus interface link, based upon feedback from each device, until each device transmits data to each other along each lane of the bus interface link with a bit error rate of less than or equal to one error per every 10.sup.4 bits).
Regarding claim 9, claim 8 is incorporated. Das Sharama further discloses wherein the sending the data to the second end at the second rate over the first data link comprises: sending a fourth training bitstream to the second end, wherein the fourth training bitstream comprises the second rate; and sending the data to the second end at the second rate over the first data link ( para. [0136] In Phase 2 the upstream port (e.g., of the endpoint device) adjusts the transmitter settings of the Downstream port (e.g., of the root complex device) to ensure that the upstream port receives the bit stream compliant with the target BER (e.g., less than or equal to 10.sup.-12) for all channels (e.g., lanes) of a communications link. An exemplary list of presets (5/5, 6/5, 7/4) indicate that multiple iterations may be performed to achieve the optimum link training
and equalization transmitter (or receiver) settings).
Regarding claim 10, claim 8 is incorporated. Das Sharama further discloses
wherein the target rate range comprises multiple target rate subranges, an intersection set of any two of the multiple target rate subranges is empty, and a union set of all of the multiple target rate subranges is the target rate range; the second rate is in a first target rate subrange and is less than the first rate, or the second rate is any rate in a second target rate subrange; and the first target rate subrange and the second target rate subrange belong to the multiple target rate subranges, the first target rate subrange comprises the first rate, and a highest rate in the second target rate subrange is less than a lowest rate in the first target rate subrange.
Regarding claim 11, claim 8 is incorporated. Das Sharama further discloses wherein the first training bitstream further comprises a second step set, comprising one or more second steps with different sizes, the second step is supported by the second end when the transmission rate of the first data link is adjusted, and the step is a unit for adjusting the transmission rate; and the fourth training bitstream further comprises adjustment information, comprising one or more of: a target step, an adjustment direction, an amount of adjustment performed on the target step, wherein the target step is any step in the second step set, the adjustment direction is an addition direction or a subtraction direction, adjustment amount is a total amount, corresponding to the target step, of adjustment to be performed on the target step, and the adjustment amount is a positive integer (see para [0144]-[0149] and Figs 14A-B).
Regarding claim 12, claim 12 is incorporated. Das Sharama further discloses wherein the first end corresponds to a first step set, comprising one or more first steps with different sizes, and the first step is supported by the first end when the transmission rate of the first data link is adjusted; and the target step is any step in a target step set, and the target step set is an intersection set of the first step set and the second step set (see para [0144]-[0149] and Figs 14A-B).
Regarding claim 13, claim 1 is incorporated. Das Sharama further discloses: receiving a fifth training bitstream sent by the second end, wherein the fifth training bitstream comprises a third rate, determined based on the target rate range; and sending the data to the second end at the third rate over the first data link (see para [0136] In Phase 2 the upstream port (e.g., of the endpoint device) adjusts the transmitter settings of the Downstream port (e.g., of the root complex device) to ensure that the upstream port receives the bit stream compliant with the target BER (e.g., less than or equal to 10.sup.-12) for all channels (e.g., lanes) of a communications link. An exemplary list of presets (5/5, 6/5, 7/4) indicate that multiple iterations may be performed to achieve the optimum link training and equalization transmitter (or receiver) settings).
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kidest Mendaye whose telephone number is (571)272-2603. The examiner can normally be reached on Monday through Friday 7:00 am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ario Etienne can be reached on (571) 272-4001. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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03/21/2026
/KIDEST MENDAYE/
Examiner, Art Unit 2457
/ARIO ETIENNE/Supervisory Patent Examiner, Art Unit 2457