Reissue
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Claim Status
Amended patent claims 1-20 and new claims 21-32 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5 June 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 depends from claim 1 and recites “at least a contact layer disposed on the target circuit substrate, wherein the plurality of conductive particles are disposed inside or above the contact layer.” However claim 1 has been amended to now require that “an intervening layer is not disposed within an area where the conductive particle…overlaps with the…conductive electrodes.” Thus a contact layer wherein the conductive particles are disposed above the contact layer would constitute an intervening layer, which is excluded by claim 1. Claim 8 is rejected for containing the same language and depends from claim 6 which also excludes an intervening layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0068350 to Kim et al. (hereinafter Kim ‘350) in view of US 7,109,058 to Yamada et al. (hereinafter Yamada).
With respect to claims 1 and 4-8, Kim ‘350 teaches a pre-conductive array (matrix arrangement of regions 240) disposed on a target circuit substrate 205, the pre-conductive array comprising a plurality of conductive electrode groups 217,270 (Figure 3) disposed on the target circuit substrate 205, wherein a first distance L1 is provided between every two of the plurality of conductive electrode groups (see annotated Figure 2B below), and each of the plurality of conductive electrode groups comprises at least a
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pair of conductive electrodes. Instead of conductive particles Kim ‘350 discloses solder
bumps 270 on electrode pads 217 to connect substrate 205 to solder material 170 on lower substrate 105. See Figure 3; paras [0070-0090].
Yamada teaches a bumpless semiconductor device wherein electrode pads 2, a passivation contact layer 3, and insulation adhesive contact layer 7 are disposed on a target substrate 1 and conductive particles 4 are disposed on each electrode pad such that the particles are within the layers 3,7. The layers do not intervene between the conductive particles and the electrode pads. The conductive particles 4 are subsequently
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bonded to a terminal 6 on circuit board 5. See col.3, lines 26-34; Figures 2(d) and (e).
Yamada discloses that this means of connection is superior to the solder balls taught by Kim ‘350 and also shown in Figure 5 of Yamada. Yamada describes the prior art method of Figure 5 and of Kim ‘350 as being difficult to achieve a fine pitch (col.2, lines 16-24). As solder bumps are placed closer together there is the risk that adjacent bumps may touch, thereby causing an electrical short. It would have been obvious to replace the opposing bumps of Kim ‘350 with the conductive particles of Yamada, as Yamada teaches that use of conductive particles produces chips “with high reliability and low cost without forming bumps on the semiconductor device, while suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board.” See col.2, lines 25-33.
When replacing the solder bumps of Kim ‘350 with conductive particles in the manner of Yamada, at least one conductive particle will be disposed on each of the pairs of the conductive electrodes wherein the conductive particles and the corresponding pair of the conductive electrodes form pre-conductive structures, and the pre-conductive structures form the pre-conductive array. As to the density of conductive particles, when the array of Kim (shown in Figure 2B) is modified by Yamada such that each electrode has at least one conductive particle therein, a first density is defined to represent a number of the plurality of conductive particles within a unit area of each of the pre-conductive structures, a second density is defined to represent a number of the plurality of conductive particles within a unit area between two of the pre-conductive structures, and the first density is greater than the second density. Since no conductive particles are located between each conductive structure, the first density will necessarily be larger than the second density which includes the empty areas between adjacent conductive structures.
As to claims 2 and 3, each of the plurality of conductive electrode groups of Kim ‘350 comprises multiple pairs of conductive electrodes, a second distance L2 is provided between adjacent two pairs of the conductive electrodes, and a third distance L3 is provided between two of the conductive electrodes of each pair. See Annotated Figure 2B above.
As to claims 9 and 10, in Kim ‘350 each pre-conductive structure may additionally be divided into a first number of conductive electrodes/electrode groups having a pair of conductive electrodes and a second number of conductive electrodes as shown in annotated Figure 2B as “electrode pairs.”
With respect to claims 11 and 12, as shown in Figure 2B of Kim ‘350 each pre-conductive structure contains a plurality of electrode groups arranged in a first array pattern and each group having at least a pair of conductive electrodes arranged in a second array pattern.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of copending Application No. 18/753739 (reference application) in view of Yamada.
Although the claims at issue are not identical, they are not patentably distinct from each other.
The limitations of claims 1-8 are substantially recited by claims 1-5 of the ‘739 application. The claims of the ‘739 application do not recite the absence of an intervening layer within an area where the conductive particle of the plurality of conductive particles overlaps with the at least one of the pair of the conductive electrodes in a plan view.”
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However, Yamada teaches a bumpless semiconductor device wherein electrode pads 2, a passivation contact layer 3, and insulation adhesive contact layer 7 are disposed on a target substrate 1 and conductive particles 4 are disposed on each electrode pad such that the particles are within the layers 3,7. The layers do not intervene between the conductive particles and the electrode pads. The conductive particles 4 are subsequently to a terminal 6 on a circuit board 5. See Figures 2(d) and (e).
Yamada discloses that this means of connection is superior to solder balls and describes the prior art method of Figure 5 as being difficult to achieve a fine pitch (col.2, lines 16-24). As solder bumps are placed closer together there is the risk that adjacent bumps may touch, thereby causing an electrical short. It would have been obvious to use the conductive particles of Yamada in the pre-conductive array of the ‘739 claims, as Yamada teaches that use of conductive particles produces flip chips “with high reliability and low cost without forming bumps on the semiconductor device, while suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board.” See col.2, lines 25-33.
Claims 13 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 and 24 of copending Application No. 18/753739 (reference application).
The limitations of claim 13 are recited by claim 24 of the ‘739 application.
The limitations of claim 17 are recited by claim 17 of the ‘739 application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 13 and 17 will be allowable upon filing of an acceptable terminal disclaimer to overcome the non-statutory double-patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter: Claim 13 recites " array-type micro semiconductor structures disposed corresponding to a part or all of the pre-conductive array of the target circuit substrate, wherein each of the micro semiconductor structures has a pair of electrodes, and each of the electrodes of each of the micro semiconductor structures and a corresponding pre-conductive structure of the target circuit substrate together form a conductive structure." Claim 17 is substantially the same but instead requires "an electrode" instead of a "pair of electrodes."
Li, however, makes clear that the array of dies 110 shown in Figure 1A are singulated before packaging, shown in Figure 3B. See also, col.2, lines 53-55; col.3, lines 50-52; col.6, lines 12-17. Thus, Li does not teach or suggest array-type semiconductor structures disposed on corresponding pre-conductive structures of the pre-conductive array as required by claim 13. Instead, Li teaches semiconductor structures disposed on singulated dies. Yamada and Kim fail to cure the deficiencies of Li. Claims 14-16 and 18-32 are likewise allowable as depending from one of claims 13 or 17.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH L MCKANE whose telephone number is (571)272-1275. The examiner can normally be reached Mon-Thu 6:30a-4:30p EST.
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/ELIZABETH L MCKANE/Specialist, Art Unit 3991
Conferees:
/LEONARDO ANDUJAR/Primary Examiner, Art Unit 3991
/Patricia L Engle/SPRS, Art Unit 3991
Prosecution Insights