DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stark et al. (US 9,819,585 B1, hereinafter refers Stark).
Regarding claim 1, Stark discloses an apparatus comprising:
a crossbar circuit that routes one or more packets between a plurality of ingress nodes and one or more egress nodes (Fig. 4, el. 112, crossbar circuit, Ingress port, and Egress port);
and a shared hardware interface, wherein each of the plurality of ingress nodes is available to the crossbar circuit via the shared hardware interface (Fig. 4, Ingress ports (el. A11, A21, and A31) is available to crossbar circuit, via A1, A2, and A3 interfaces).
Regarding claim 2, Stark discloses comprising a central hardware logic circuit (Fig. 4).
Regarding claim 3, Stark discloses wherein: the shared hardware interface includes a pool of hardware interfaces (Fig. 5), the plurality of ingress nodes shares the pool of hardware interfaces (Fig. 5, el. 114), and the central hardware logic circuit prevents traffic from the plurality of ingress nodes exceeding a respective throughput for a respective hardware interface of the pool of hardware interfaces (Fig. 5, el. 114, e.g., a switch and buffer to prevent the traffic).
Regarding claim 4, Stark discloses wherein: the shared hardware interface includes a pool of hardware interfaces, the one or more egress nodes comprise a plurality of egress nodes that share the pool of hardware interfaces, and the central hardware logic circuit prevents traffic from the plurality of egress nodes exceeding a respective throughput for a respective hardware interface of the pool of hardware interfaces (Fig. 5, el. 129, a buffer to prevent the traffic).
Regarding claim 5, Stark discloses one or more buffers storing credits, wherein the credits resolve collisions between different ingress nodes (Fig. 5, el. 114, a buffer).
Regarding claim 6, Stark discloses wherein the shared hardware interface manages credits on the one or more buffers when data sent from each ingress nodes arrives at one of the one or more egress nodes (Fig. 5, el. 129, a buffer).
Regarding claim 7, Stark discloses wherein the central hardware logic circuit is configured to resolve a collision of data from two or more ingress nodes by choosing an oldest transaction from among the data (Fig. 5, CCF circuit or crossbar circuit to process the data flow according its timestamp, ).
Regarding claim 8, Stark discloses wherein the one or more egress nodes are associated with a destination multiplexer, wherein the destination multiplexer and an associated destination buffer absorb a burst in traffic (Fig. 5, el. 128, the multiplexer).
Regarding claim 9, Stark discloses wherein data is output by each ingress node to the shared hardware interface without direction by a central hardware logic circuit (Fig. 4 and 5, the data flow from the ingress port to flow to the crossbar circuit).
Regarding claim 10, the instant claim is analyzed with respect to claim 1.
Regarding claim 11, the instant claim is analyzed with respect to claim 2.
Regarding claim 12, the instant claim is analyzed with respect to claim 3.
Regarding claim 13, the instant claim is analyzed with respect to claim 5.
Regarding claim 14, the instant claim is analyzed with respect to claim 6.
Regarding claim 15, the instant claim is analyzed with respect to claim 7.
Regarding claim 16, the instant claim is analyzed with respect to claim 8.
Regarding claim 17, the instant claim is analyzed with respect to claim 3.
Regarding claim 18, the instant claim is analyzed with respect to claim 9.
Regarding claim 19, the instant claim is analyzed with respect to claim 1.
Regarding claim 20, the instant claim is analyzed with respect to claim 2.
Regarding claim 21, the instant claim is analyzed with respect to claim 3.
Conclusion
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/CAI Y CHEN/ Primary Examiner, Art Unit 2425