DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matari et al. (US 2024/0406122 A1, hereinafter refers as Matari).
Regarding claim 1, Matari discloses an apparatus comprising:
a crossbar circuit that routes one or more packets between a plurality of ingress nodes and one or more egress nodes (Fig. 1, el. 102, Ingress Domain to Crossbar Circuit to Egress domain);
and a shared hardware interface comprising a plurality of hardware interfaces (Fig. 1), wherein each of the plurality of ingress nodes is available to the crossbar circuit via the shared hardware interface, and wherein the crossbar circuit connects to the plurality of hardware interfaces of the shared hardware interface via a plurality of inputs and to the one or more egress nodes via a plurality of outputs (Fig.2. the hardware interface refers as el. 201, el. 106 from Ingress domain size, and el. 280, el. 290, el. 291 refers as the hardware interface from Egress Domain side).
Regarding claim 2, Matari discloses a central hardware logic circuit associated with the shared hardware interface (Fig. 1).
Regarding claim 3, Matari discloses wherein: the plurality of ingress nodes shares plurality of hardware interfaces of the shared hardware interface, and the central hardware logic circuit prevents traffic from the plurality of ingress nodes exceeding a respective throughput for a respective hardware interface of plurality of hardware interfaces of the shared hardware interface (Fig. 1 and 2, para. 38-39, para. 41-43).
Regarding claim 4, Matari discloses wherein: the one or more egress nodes comprise a plurality of egress nodes that share the plurality of hardware interfaces of the shared hardware interface, and the central hardware logic circuit prevents traffic from the plurality of egress nodes exceeding a respective throughput for a respective hardware interface of the plurality of hardware interfaces of the shared hardware interface (Fig. 1 and 2, para. 38-39, para. 41-43).
Regarding claim 5, Matari discloses one or more buffers storing credits, wherein the credits resolve collisions between different ingress nodes (Fig. 2, el. 130).
Regarding claim 6, Matari discloses wherein the shared hardware interface manages credits on the one or more buffers when data sent from each ingress nodes arrives at one of the one or more egress nodes (Fig. 2, el. 130).
Regarding claim 7, Matari discloses wherein the central hardware logic circuit is configured to resolve a collision of data from two or more ingress nodes by choosing an oldest transaction from among the data (Fig. 1-2, para. 42, para. 47-48).
Regarding claim 8, Matari discloses wherein the one or more egress nodes are associated with a destination multiplexer, wherein the destination multiplexer and an associated destination buffer absorb a burst in traffic (Fig. 2, para. 50, el. 140).
Regarding claim 9, Matari discloses wherein data is output by each ingress node to the shared hardware interface without direction by a central hardware logic circuit (Fig. 1-2).
Regarding claim 10, the instant claim is met by the rejection of claim 1.
Regarding claim 11, the instant claim is met by the rejection of claim 2.
Regarding claim 12, the instant claim is met by the rejection of claim 3.
Regarding claim 13, the instant claim is met by the rejection of claim 4.
Regarding claim 14, the instant claim is met by the rejection of claim 5.
Regarding claim 15, the instant claim is met by the rejection of claim 6.
Regarding claim 16, the instant claim is met by the rejection of claim 7.
Regarding claim 17, the instant claim is met by the rejection of claim 8.
Regarding claim 18, the instant claim is met by the rejection of claim 9.
Regarding claim 19, the instant claim is met by the rejection of claim 1.
Regarding claim 20, the instant claim is met by the rejection of claim 2.
Regarding claim 21, the instant claim is met by the rejection of claim 3.
Conclusion
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/CAI Y CHEN/ Primary Examiner, Art Unit 2425
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