Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I and Species B in the reply filed January 5, 2026 is acknowledged. Claim 20 drawn to the non-elected invention(s) has been withdrawn from examination for patentability.
Claim Objections
Claims 4-6 and 14-15 are objected to because of the following informalities: “PMOS” and “NMOS” in claim 4 should be changed to “PMOS transistors” and “NMOS transistors”, respectively; “the first voltage” in claims 5 and 14 should be changed to “the second voltage”; “the second voltage” in claims 6 and 15 should be changed to “the first voltage”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0409020 to Singrigowda et al. (“Singrigowda”).
With respect to claim 13, Singrigowda discloses in Fig. 11 a system comprising:
a first, second and third PMOS transistor (e.g., P1-P3, respectively) serially coupled between a first high voltage power supply (e.g., 3.3V) and a pad (e.g., PAD), a gate of the first PMOS transistor (e.g., P1) coupled to a first signal (e.g., 1102) from an internal circuit, the first signal (e.g., 1102) configured to switch between a first voltage (e.g., 2V) and the first high voltage power supply (e.g., 3.3V), the first voltage (e.g., 2V) being lower than the first high voltage power supply (e.g., 3.3V), a gate of the second PMOS transistor (e.g., P2) being applied the first voltage (e.g., 2V), and a gate and drain of the third PMOS transistor (e.g., P3) connected to an adaptive control node (e.g., 1112) and the pad (e.g., PAD), respectively; and
a first, second and third NMOS transistor (e.g., N1-N3, respectively) serially coupled between the pad (e.g., PAD) and a ground, a gate of the first NMOS transistor (e.g., N1) coupled to a second signal (e.g., 1110) from the internal circuit, the second signal (e.g., 1110) configured to switch between a second voltage (e.g., 1.1.V) and the ground (e.g., 0V), the second voltage (e.g., 1.1V) being higher than the ground but lower than the first voltage (e.g., 2V), a gate of the second NMOS transistor (e.g., N2) being applied the second voltage (e.g., 1.1V), and a gate and drain of the third NMOS transistor (e.g., N3) connected to the adaptive control node (e.g., 1112) and the pad (e.g., PAD), respectively, wherein the adaptive control node (e.g., 1112) is configured to switch between the first (e.g., 2V) and second voltage (e.g., 1.1V).
With respect to claim 14, when the gate of the first PMOS transistor (e.g., P1) is at the first voltage (e.g., 2V) and the gate of the first NMOS transistor (e.g., N1) is at the ground (e.g., 0V), the adaptive control node (e.g., 1112) is at the second voltage (e.g., 1.1V).
With respect to claim 15, when the gate of the first PMOS transistor (e.g., P1) is at the first high voltage power supply (e.g., 3.3V) and the gate of the first NMOS transistor (e.g., N1) is at the second voltage (e.g., 1.1V), the adaptive control node is at the first voltage (e.g., 2V).
With respect to claims 1-3, the above discussion for claim 13 similarly applies with the exception of the following change, for example: the third PMOS transistor and the third NMOS transistor in claim 13 respectively correspond to the second PMOS transistor and the second NMOS transistor in claim 1; and the second PMOS transistor and the second NMOS transistor in claim 13 respectively correspond to the third PMOS transistor and the third NMOS transistor in claim 3.
With respect to claim 4, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” MPEP Section 2113. Here, the first, second and third PMOS and the first, second and third NMOS may be manufactured in a same process as the internal circuit and the end product is the same or obvious over the Fig. 11 circuit, and thus, the claimed feature is met in the Fig. 11 circuit.
With respect to claims 5-6, the above discussion for claims 14-15 similarly applies.
Allowable Subject Matter
Claims 7-12 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842