DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-29 and 31-40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim et al 20160372185 herein Shim.
Per claim 21, Shim discloses: a memory array, wherein the memory array comprises memory blocks, each memory block includes memory cell strings, (fig. 3&4; ¶0078) and each memory cell string includes a first memory cell coupled with a first word line, (WL)second memory cells respectively coupled with second word lines, and a third memory cell coupled with a third word line, wherein the second memory cells are between the first memory cell and the third memory cell, the first memory cell is adjacent to a bit line, (BL) and the third memory cell is a memory cell closest to a source line (SL); and a control logic (fig. 3) coupled to the memory array and is configured to: (fig. 3&4, ¶0078; The memory cell array 110 may include a plurality of memory cells that are disposed at cross points of a plurality of rows or word line and a plurality of columns or bit lines. The memory cells in the memory cell array 110 may form a plurality of memory blocks. As illustrated in FIG. 4, the memory cells in each memory block 101 of the memory cell array 110 may have the NAND string structure; the examiner notes that the memory array is merely a 3D NAND) perform a first program operation on the third memory cells coupled with the third word line in a memory block of the memory blocks; (fig. 6&7, ¶0099; the first memory cells MC1 may be programmed to the first programmed state PS1, and the programming of the first memory cells MC1 is verified.) and after performing the first program operation on the third memory cells, perform a second program operation on the second memory cells in the memory block (fig. 6&7, ¶0099; Then, the second memory cells MC2 may be programmed to the second programmed state PS2, and the programming of the second memory cells MC2 is verified).
Per claim 22, Shim discloses: wherein after performing the first program operation on the third memory cells, an average value of threshold voltages of the third memory cells in the memory block is higher than or equal to a target value (¶0101-102; After applying the first program voltage VPGM11, a first program verification voltage VPVF1 is applied to the selected wordline WLs to verify whether the threshold voltages of all of the first memory cells MC1 have reached a target voltage level. If the first memory cells MC1 are not fully programmed, a second program loop PLP12 may be performed. The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.).
Per claim 23, Shim discloses: the control logic is further configured to: before performing the first program operation on the third memory cells, obtain a first average value of threshold voltages of the third memory cells in the memory block; and in response to the first average value being less than the target value, perform the first program operation (¶0101-102; After applying the first program voltage VPGM11, a first program verification voltage VPVF1 is applied to the selected wordline WLs to verify whether the threshold voltages of all of the first memory cells MC1 have reached a target voltage level. If the first memory cells MC1 are not fully programmed, a second program loop PLP12 may be performed. The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.).
Per claim 24, Shim discloses: the control logic is further configured to: before performing the first program operation on the third memory cells, obtain a first average value of threshold voltages of the third memory cells in the memory block; and in response to the first average value being higher than or equal to the target value, skip the first program operation on the third memory cells, and perform the second program operation on the second memory cells in the memory block (¶0101-102; The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.).
Per claim 25, Shim discloses: wherein the first average value of threshold voltages of the third memory cells is greater than 0 volt (¶0027; wherein the plurality of memory cells have a threshold voltage distribution in the erased state such that at least some of the plurality of memory cells have a threshold voltage that is greater than zero, and programming the plurality of memory cells based on the program data such that each of the plurality of memory cells is programmed to one of a plurality of programmed states).
Per claim 26, Shim discloses: wherein the first average value of threshold voltages of the third memory cells is greater than a second average value of threshold voltages of first memory cells in the memory block (¶0027; wherein the plurality of memory cells have a threshold voltage distribution in the erased state such that at least some of the plurality of memory cells have a threshold voltage that is greater than zero, and programming the plurality of memory cells based on the program data such that each of the plurality of memory cells is programmed to one of a plurality of programmed states).
Per claim 27, Shim discloses: the second memory cells comprise a first cell group coupled with a first line group of the second word lines, a second cell group coupled with a second line group of the second word lines, and a third cell group coupled with a third line group of the second word lines, wherein the first cell group is between the third memory cell and the second cell group, and the second cell group is between the third cell group and the first cell group; (fig. 3&4, ¶0078; The memory cell array 110 may include a plurality of memory cells that are disposed at cross points of a plurality of rows or word line and a plurality of columns or bit lines. The memory cells in the memory cell array 110 may form a plurality of memory blocks. As illustrated in FIG. 4, the memory cells in each memory block 101 of the memory cell array 110 may have the NAND string structure; the examiner notes that the memory array is merely a 3D NAND) and performing the second program operation on the second memory cells comprises: applying a program voltage to the third line group; applying a first pass voltage to the first line group; and applying a second pass voltage to the second line group, wherein the first pass voltage is less than the second pass voltage (¶0101-102; After applying the first program voltage VPGM11, a first program verification voltage VPVF1 is applied to the selected wordline WLs to verify whether the threshold voltages of all of the first memory cells MC1 have reached a target voltage level. If the first memory cells MC1 are not fully programmed, a second program loop PLP12 may be performed. The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.; the examiner notes the incremental step pulse programming).
Per claim 28, Shim discloses: the second word lines include word line WLO, word line WL1,..., word line WLm,.., word line WLn,..., and word line WLk arranged in a sequential order, wherein m, n, and k are integers, and m is less than k; andthe control logic is further configured to, when the first line group includes word line WLO and word line WL1, and the third line group has word line WLn: (fig. 3&4, ¶0078; The memory cell array 110 may include a plurality of memory cells that are disposed at cross points of a plurality of rows or word line and a plurality of columns or bit lines. The memory cells in the memory cell array 110 may form a plurality of memory blocks. As illustrated in FIG. 4, the memory cells in each memory block 101 of the memory cell array 110 may have the NAND string structure; the examiner notes that the memory array is merely a 3D NAND) apply the second pass voltage to the second line group including word line WL2 to word line WLm-1; and apply a third pass voltage to the second line group including word line WLn-4 to word line WLm, wherein (n-4) is greater than m (¶0101-102; After applying the first program voltage VPGM11, a first program verification voltage VPVF1 is applied to the selected wordline WLs to verify whether the threshold voltages of all of the first memory cells MC1 have reached a target voltage level. If the first memory cells MC1 are not fully programmed, a second program loop PLP12 may be performed. The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.; the examiner notes the incremental step pulse programming).
Per claim 29, Shim discloses: wherein the third pass voltage comprises a set of voltage values different from the first pass voltage and the second pass voltage (¶0101-102; If the first memory cells MC1 are not fully programmed, a second program loop PLP12 may be performed. The second program loop PLP12 is similar to the first program loop PLP11, but a second program voltage VPGM12 that is higher than the first program voltage VPGM11 is applied to the selected wordline WLs in the second program loop PLP12. In this manner, incremental step pulse programming (ISPP) may be performed by increasing the program voltage after each programming loop until the programming of the first memory cells MC1 is completed.; the examiner notes the incremental step pulse programming).
Per claim 31, Shim discloses: a memory array, wherein the memory array comprises memory blocks, each memory block includes memory cell strings, (fig. 3&4; ¶0078) and each memory cell string includes a first memory cell coupled with a first word line, (WL)second memory cells respectively coupled with second word lines, and a third memory cell coupled with a third word line, wherein the second memory cells are between the first memory cell and the third memory cell, the first memory cell is adjacent to a bit line, (BL) and the third memory cell is a memory cell closest to a source line (SL); and a control logic (fig. 3) coupled to the memory array and is configured to: (fig. 3&4, ¶0078; The memory cell array 110 may include a plurality of memory cells that are disposed at cross points of a plurality of rows or word line and a plurality of columns or bit lines. The memory cells in the memory cell array 110 may form a plurality of memory blocks. As illustrated in FIG. 4, the memory cells in each memory block 101 of the memory cell array 110 may have the NAND string structure; the examiner notes that the memory array is merely a 3D NAND) perform a first program operation on the third memory cells coupled with the third word line in a memory block of the memory blocks; (fig. 6&7, ¶0099; the first memory cells MC1 may be programmed to the first programmed state PS1, and the programming of the first memory cells MC1 is verified.) and after performing the first program operation on the third memory cells, perform a second program operation on the second memory cells in the memory block (fig. 6&7, ¶0099; Then, the second memory cells MC2 may be programmed to the second programmed state PS2, and the programming of the second memory cells MC2 is verified).
Claims 32-39 are the method claims corresponding to the device claims 22-29 and are rejected under the same reasons set forth in connection with the rejection of claims 22-27.
Per claim 40, Shim discloses: a memory array, wherein the memory array comprises memory blocks, each memory block includes memory cell strings, (fig. 3&4; ¶0078) and each memory cell string includes a first memory cell coupled with a first word line, (WL)second memory cells respectively coupled with second word lines, and a third memory cell coupled with a third word line, wherein the second memory cells are between the first memory cell and the third memory cell, the first memory cell is adjacent to a bit line, (BL) and the third memory cell is a memory cell closest to a source line (SL); and a control logic (fig. 3) coupled to the memory array and is configured to: (fig. 3&4, ¶0078; The memory cell array 110 may include a plurality of memory cells that are disposed at cross points of a plurality of rows or word line and a plurality of columns or bit lines. The memory cells in the memory cell array 110 may form a plurality of memory blocks. As illustrated in FIG. 4, the memory cells in each memory block 101 of the memory cell array 110 may have the NAND string structure; the examiner notes that the memory array is merely a 3D NAND) perform a first program operation on the third memory cells coupled with the third word line in a memory block of the memory blocks; (fig. 6&7, ¶0099; the first memory cells MC1 may be programmed to the first programmed state PS1, and the programming of the first memory cells MC1 is verified.) and after performing the first program operation on the third memory cells, perform a second program operation on the second memory cells in the memory block (fig. 6&7, ¶0099; Then, the second memory cells MC2 may be programmed to the second programmed state PS2, and the programming of the second memory cells MC2 is verified) a memory controller coupled to the memory device and configured to control the memory device (fig. 3, comp 150).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al 20160372185 herein Shim in view of Lee discloses 20160141011 herein Lee.
Per claim 30, Shim disclose SLC and MLS configuration but does not specifically discloses: wherein the second memory cells coupled to word line WLO are of one type of a single-level cell SLC memory cell, a multi-level cell MLC memory cell, or a three-level cell TLC memory cell; and the second memory cells coupled to remaining word lines are four-level cell QLC memory cells.
However, Lee discloses: wherein the second memory cells coupled to word line WLO are of one type of a single-level cell SLC memory cell, a multi-level cell MLC memory cell, or a three-level cell TLC memory cell; and the second memory cells coupled to remaining word lines are four-level cell QLC memory cells (¶0025; The memory cells may include a three-dimensional structure whereby the memory cells are arranged in a vertical direction with respect to a substrate. The memory cells may include single level cells (SLC) storing one bit of data, multi level cells (MLC), triple level cells (TLC) or quadruple level cells (QLC) storing two or more bits of data. For example, two bits of data may be stored in each of the multi level cells (MLC), three bits of data may be stored in each of the triple level cells (TLC), and four bits of data may be stored in each of the quadruple level cells (QLC).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Shim and Lee’s multi level cells configuration to reduce program errors. Lee improves reliability (¶0022; a semiconductor device capable of reducing a soft program operation time).
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138