Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/28/2026 have been fully considered but they are not persuasive.
Applicant argues that Jin fails to disclose a voltage supply circuit for a first analog output of a measuring device and instead relates to an LED driver, and further asserts that paragraph
[0019] of Jin merely discusses a manufacturing calibration procedure.
The Examiner agrees that paragraph [0019] concerns a manufacturing calibration procedure. However, the rejection does not rely solely upon paragraph [0019). Rather, Jin is relied upon for teaching a DC/DC converter configured to regulate a supply voltage based upon a monitored output condition through a feedback arrangement. Jin teaches monitoring the output voltage associated with an output channel, determining an appropriate boost voltage while maintaining a desired voltage margin, and controlling the DC/DC converter accordingly.
Accordingly, the particular application of Jin to an LED driver does not detract from its applicability because claim 1 is directed to a voltage supply circuit for a first analog output and merely states that the analog output is "in particular of a measuring device," which is not a structural limitation restricting the claimed circuit to measuring device applications.
Applicant further argues that Jin employs a digital control loop including an ADC and luminance controller rather than the claimed circuit.
This argument is not persuasive because claim 1 does not exclude the use of digital circuitry, nor does it require that regulation be performed exclusively through analog circuitry. Claim 1 recites a DC/DC converter, a p-channel MOSFET having specified electrical connections, and a DC supply voltage formed by adding a constant surplus voltage to a sampled voltage value. The claim does not require that the addition of the surplus voltage be performed solely by the p-channel MOSFET or exclusively by analog transistor operation. The Examiner relies upon Jin for teaching regulation of a DC/DC converter based upon a monitored output voltage and relies upon Mathe for teaching maintaining a target supply voltage corresponding to a monitored voltage plus a predetermined headroom (surplus) voltage. The references are relied upon for their combined teachings under 35 U.S.C. §103 and need not individually disclose every claimed feature.
Applicant additionally argues that Mathe fails to disclose the claimed p-channel MOSFET
arrangement. However, Mathe is relied upon for teaching the functional relationship between a
monitored voltage and a target voltage that includes a predetermined headroom or surplus
voltage, rather than as an identical disclosure of Applicant's circuitry. Likewise, Jin is relied upon
for the regulated DC/DC converter architecture. The rejection does not require bodily
incorporation of one reference into another. Rather, it would have been obvious to one of
ordinary skill in the art to incorporate Mathe's headroom based regulation technique into Jin's
regulated DC/DC converter in order to maintain sufficient operating margin while minimizing
unnecessary power dissipation, thereby achieving the predictable result of providing a supply
voltage that follows the monitored output while maintaining a substantially constant voltage
margin.
Applicant further argues that the cited references fail to disclose the claimed gate, source, drain, and resistor connections. The Examiner notes that obviousness under 35 U.S.C. §103 does not require that the prior art disclose an identical circuit or identical implementation. The proper inquiry is whether the combined teachings would have suggested the claimed subject matter to one of ordinary skill in the art. Jin teaches regulating the converter output according to a monitored output condition, while Mathe teaches establishing the converter target voltage by adding a predetermined headroom voltage to the monitored voltage. In view of these combined teachings, one of ordinary skill in the art would have recognized that implementing the known feedback relationship using an appropriate transistor based feedback arrangement connected to the converter feedback path would have been an obvious design choice to achieve the predictable result of maintaining a substantially constant surplus voltage above the sampled analog output while reducing power dissipation.
Applicant's arguments are directed primarily to the particular implementation disclosed in the Specification but do not demonstrate that claim 1 excludes other implementations that achieve the claimed functional relationship or that the Examiner's proposed combination would have been beyond the ordinary level of skill in the art.
Applicant further argues with respect to claim 2 that neither Jin nor Mathe teaches or suggests the claimed arrangement including first and second p-channel MOSFETs connected in series and that the claimed circuit inherently determines the higher of the two sampled analog output voltages without requiring a separate maximum selection circuit. Applicant further argues that one of ordinary skill in the art would instead employ a separate comparator or maximum selection circuit rather than the claimed arrangement.
These arguments are not persuasive because they import limitations from the Specification into claim 2 that are not positively recited by the claim. Claim 2 recites first and second p-channel MOSFETs connected in series and further recites that the DC supply voltage is formed by adding a constant surplus voltage to the respective higher of the two sampled voltage values.
However, claim 2 does not recite the particular mechanism by which the higher of the two sampled voltage values is determined, nor does it require that such determination occur solely through the intrinsic electrical operation of the series connected p-channel MOSFETs.
Accordingly, Applicant's arguments are not commensurate with the scope of claim 2. As set forth in the rejection, Jin is relied upon for teaching regulation of a DC/DC converter according to monitored output conditions in order to provide sufficient operating voltage while avoiding unnecessary excess supply voltage. Mathe is relied upon for teaching generation of a target supply voltage by adding a predetermined headroom (surplus) voltage to a monitored voltage. The combined teachings therefore establish regulating the supply voltage according to a monitored output voltage while maintaining a substantially constant surplus voltage.
When extending the same regulation technique to a circuit having multiple monitored analog outputs, it would have been obvious to one of ordinary skill in the art to regulate the common DC/DC converter according to the monitored output requiring the greater supply voltage so that each analog output receives sufficient operating voltage while avoiding unnecessary excess supply voltage and the associated power dissipation. Such a modification merely applies the same headroom based regulation taught by the combined references to a circuit having multiple monitored outputs and yields the predictable result of maintaining a substantially constant surplus voltage above the monitored output requiring the greatest supply voltage.
Applicant further argues that the cited references fail to disclose the claimed series connection between the first and second p-channel MOSFETs. However, obviousness under 35 U.S.C. §103 does not require that the prior art disclose an identical circuit arrangement or that one reference be bodily incorporated into another. Rather, the proper inquiry is whether the combined teachings of the references would have suggested the claimed subject matter to one of ordinary skill in the art. In view of the combined teachings of Jin and Mathe, it would have been obvious to implement the headroom based regulation of a common DC/DC converter for multiple monitored analog outputs using the claimed arrangement so that the converter output follows the monitored output requiring the higher operating voltage while maintaining the desired surplus voltage, thereby achieving the same objective of providing sufficient operating voltage with reduced power dissipation.
Accordingly, Applicant has not identified reversible error in the rejection of claims 1 and 2. The combination of Jin and Mathe continues to teach or render obvious the subject matter of claim 1, and the rejection under 35 U.S.C. §103 is therefore maintained.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin (U.S. Publication 20110062872) in view of Mathe (U.S. Publication 20140111276).
Regarding claim 1, Jin teaches a voltage supply circuit (1.1) for a first analog output (5.1) (fig. 3 (LED driver circuit 300) fig. 3 the voltage supply circuit with Boost converter 301 and it feedback circuitry which supplies DC supply voltage Vboost to at least one analog current output formed by an LED channel including LDO 304 and LED string 302 [0035-39]), in particular of a measuring device (“The on-resistance of the PWM transistor is measured during the manufacturing process” [0019]), the voltage supply circuit comprising:
a DC/DC converter (2) (fig. 3 (301)) comprising a supply output (2.1) (fig. 3 (312)), an internal or external reference voltage reference (2.2) (fig. 3 (reference voltage with boost controller 316)) and a feedback terminal (2.3) (feedback terminal implemented via resistive divider R/R2 fig. 3 [0036-37]), wherein the DC/DC converter (2) is configured to provide a DC supply voltage (8) at the supply output (2.1) (boost converter 301 fig. 3 provide a regulated DC supply voltage Vboost at its output to supply downstream circuit [0037]);
a first signal input (5.3), via which the voltage value (9.1) provided at the first analog output (5.1) is supplied to the voltage supply circuit (1.1) (output signal Vsense 315 fig. 3 supplied from the analog output circuitry to the supply control circuitry via 311 and 313 influencing controls of the DC/DC converter [0040-44]) and
wherein the value of the DC supply voltage (8) is formed by adding a constant surplus voltage (10) to the sampled voltage value (9.1) (the DC/DC supply voltage Vboost is adjusted such that it exceeds the output voltage by a defined headroom voltage sufficient to maintain regulation of the linear current regulator [0047-49]).
Jin does not explicitly teach a first p-channel MOSFET (3) comprising a first gate terminal (3.1), a first source terminal (3.2) and a first drain terminal (3.3); sampled by the first gate terminal (3.1), wherein the first source terminal (3.2) is connected to the supply output (2.1) via a first resistor (4.1) and the first drain terminal (3.3) is connected to the feedback terminal (2.3) and to 0 volts via a second resistor (4.2).
Mathe in a relevant art teaching techniques for controlling boost converter operation in an envelope tracking (ET) system teaches a first p-channel MOSFET (3) comprising a first gate terminal (3.1), a first source terminal (3.2) and a first drain terminal (3.3) (Mosfet based circuitry used to sample voltage and control boost converter feedback signal fig. 2, 6 where transistor based elements process the sample tracking voltage to generate a control signal for the DC/DC converter [0044-46]);
sampled by the first gate terminal (3.1) (sampling a tracking voltage Vamp fig. 6 using control circuitry that process the sampled voltage prior to regulating the boost converter output, corresponding to sampling by a transistor control terminal [0044]),
wherein the first source terminal (3.2) is connected to the supply output (2.1) via a first resistor (4.1) (resistive coupling associated with the generation of Vtarget fig. 6, which is derived from the sampled voltage and supplied to the boost converter control input, implying resistive scaling between the supply related signal and the control circuitry) and the first drain terminal (3.3) is connected to the feedback terminal (2.3) and to 0 volts via a second resistor (4.2) (supplying the generated Vtarget fig. 6 signal to the boost converter control input referenced to ground through associated circuitry, corresponding to a resistively referenced feedback injection path [0045-49]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to apply the explicit summation-based headroom control or Mathe to the headroom control DC/DC supply of Jin in order to achieve predictable improvement in efficiency and regulator operation.
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Regarding claim 2, Jin teaches a voltage supply circuit (1.2) for two preferably reciprocal analog outputs (5.1, 5.2) (LED driver 300 supplying multiple LED channels 302 fig. 3 [0035-39]), in particular of a measuring device (“The on-resistance of the PWM transistor is measured during the manufacturing process” [0019]), the voltage supply circuit comprising:
a DC/DC converter (2) (fig. 3 (301)) comprising a supply output (2.1) (fig. 3 (312)), an internal or external reference voltage reference (2.2) (fig. 3 (reference voltage with boost controller 316)) and a feedback terminal (2.3) (feedback terminal implemented via resistive divider R/R2 fig. 3 [0036-37]), wherein the DC/DC converter (2) is configured to provide a DC supply voltage (8) at the supply output (2.1) (boost converter 301 fig. 3 provide a regulated DC supply voltage Vboost at its output to supply downstream circuit [0037]);
a first signal input (5.3), via which the voltage value (9.1) provided at the first analog output (5.1) is supplied to the voltage supply circuit (1.1) (output signal Vsense 315 fig. 3 supplied from the analog output circuitry to the supply control circuitry via 311 and 313 influencing controls of the DC/DC converter [0040-44]) and
a second signal input (5.4), via which the voltage value (9.2) provided at a second analog output (5.2) is supplied to the voltage supply circuit (1.1) and sampled by the second gate terminal (11.1) (multiple output channels each provide their respective output related voltage/current information to the supply control circuitry, enabling monitoring of more than one analog output [0040-44]),
wherein the value of the DC supply voltage (8) is formed by adding a constant surplus voltage (10) to the respective higher of the two sampled voltage values (9.1, 9.2) (the DC/DC supply voltage Vboost is set based on the weakest output channel i.e the channel requiring the highest voltage, such that sufficient headroom is provided for all channels [0047-49]).
Jin does not explicitly teach a first p-channel MOSFET (3) comprising a first gate terminal (3.1), a first source terminal (3.2) and a first drain terminal (3.3);
a second p-channel MOSFET (11) comprising a second gate terminal (11.1), a second source terminal (11.2) and a second drain terminal (11.3);
wherein the first source terminal (3.2) is connected to the supply output (2.1) via a first resistor (4.1), the first drain terminal (3.3) is connected to the second source terminal (11.2) and the second drain terminal (11.3) is connected to the feedback terminal (2.3) and to 0 volts via a second resistor (4.2), and
Mathe in a relevant art teaching techniques for controlling boost converter operation in an envelope tracking (ET) system teaches a first p-channel MOSFET (3) comprising a first gate terminal (3.1), a first source terminal (3.2) and a first drain terminal (3.3) (Mosfet based circuitry used to sample voltage and control boost converter feedback signal fig. 2, 6 where transistor based elements process the sample tracking voltage to generate a control signal for the DC/DC converter [0044-46]);;
a second p-channel MOSFET (11) comprising a second gate terminal (11.1), a second source terminal (11.2) and a second drain terminal (11.3) (control circuitry capable of processing samples voltage value to determine a target voltage for the boost converter, and extending this circuitry to includes and additional MOSFET for sampling a second voltage an obvious duplication of known structure fig. 6);
wherein the first source terminal (3.2) is connected to the supply output (2.1) via a first resistor (4.1) (resistive coupling associated with the generation of Vtarget fig. 6, which is derived from the sampled voltage and supplied to the boost converter control input, implying resistive scaling between the supply related signal and the control circuitry), the first drain terminal (3.3) is connected to the second source terminal (11.2) (combining sampled voltage processing elements within the control path, and cascading transistor elements to form a dominant voltage selection path and obvious arrangement fig. 6) and the second drain terminal (11.3) is connected to the feedback terminal (2.3) and to 0 volts via a second resistor (4.2)(supplying the generated Vtarget fig. 6 signal to the boost converter control input, referenced to ground through associated circuitry, corresponding to a resistively referenced feedback injection path [0045-49]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to apply the explicit summation-based headroom control or Mathe to the headroom control DC/DC supply of Jin in order to achieve predictable improvement in efficiency and regulator operation.
Regarding claims 3, 11, Jin as modified further teaches wherein the first analog output (5.1) is configured to output a 4-20 mA signal and/or the second analog output (5.2) is configured to output a 20-4 mA signal (the regulated output currents are selectable and adjustable by control circuitry [0038-42]).
Regarding claim 4, Jin as modified further teaches at least one current regulator for adjusting a signal to be output at the first analog output (5.1) and/or the second analog output (5.2) (LDO 304 fig. 3 for each channel output to regulate and adjust current supplied to the corresponding analog output channel [0038-42]), wherein the current regulator is connected to the supply output (2.1) (each LDO 304 is supplied directly from the DC/DC converter output Vboost 312 fig. 3, such that the current regulator is connected to the DC supply output of the boost converter [0036-39]).
Regarding claim 5, Jin as modified further teaches wherein the first resistor (4.1) and the second resistor (4.2) are configured such that the DC supply voltage (8) corresponds to the sum of the voltage (9.1) provided at the first analog output (5.1) and a constant surplus voltage (10) (Vboost fig. 3 is adjusted such that it exceeds the voltage required by the output channel by a defined headroom voltage sufficient to maintain regulation of the linear regulator [0047-49], the output voltage of the DC/DC converter is determined via a resistive feedback network R1/R2 coupled to the boost controller, such that the regulated output voltage corresponds to a desired relationship between the sensed voltage and the converter reference [0036-37]inherently resistive elements in the feedback path of a DC/DC converter to set the output voltage equal to a required output voltage plus a constant surplus) or to the sum of the voltage (9.2) provided at the second analog output (5.2) and the constant surplus voltage (10) (multiple output channels, Vboost is adjusted based on the output channel requiring the highest voltage, such that sufficient headroom is provided for all channels [0047-49]).
Regarding claim 6, Jin as modified further teaches wherein the constant surplus voltage (10) corresponds to a voltage drop at the at least one current regulator (Vboost is adjusted such that it provides sufficient headroom voltage across the linear current regulator LDO 304 to maintain regulation of the output current [0047-49] the power dissipated in the LDO is proportional of the voltage drop across the LDO, and that minimizing excess voltage while maintaining regulation is primary objective of the supply control scheme [0008-0010])).
Regarding claim 7, Jin does not explicitly teach wherein the constant surplus voltage (10) corresponds to the sum of the voltage drop across the first resistor (4.1), a gate-source voltage of the first p-channel MOSFET (3) or a gate-source voltage of the second p-channel MOSFET (11).
Mathe in a relevant art teaching techniques for controlling boost converter operation in an envelope tracking (ET) system teaches wherein the constant surplus voltage (10) corresponds to the sum of the voltage drop across the first resistor (4.1), a gate-source voltage of the first p-channel MOSFET (3) or a gate-source voltage of the second p-channel MOSFET (11) (generating a target voltage for a boost converter as a sum of multiple voltage components, including samples, programmable headroom voltage implemented using transistor based circuitry whose operation inherently includes gate source voltage contribution and resistive voltage drops [0044-46]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to apply the explicit summation-based headroom control or Mathe to the headroom control DC/DC supply of Jin in order to achieve predictable improvement in efficiency and regulator operation.
Regarding claim 8, Jin as modified further teaches wherein the constant surplus voltage (10) is between 3 and 7 V, in particular 5 V (Vboost is controlled to maintain a surplus headroom voltage sufficient to ensure proper operation of the linear current regulator LDO 304 while minimizing power dissipation [0008-10, 47-49] selecting a specific value within a range is obvious to ensure reliable regulation while balancing efficiency).
Regarding claim 9, Jin as modified further teaches at least one voltage regulator for converting the DC supply voltage (8) into an additional DC voltage at a load output for a further load (voltage supply in which DC/DC converter output Vboost supplies downstream circuitry, including control electronics such as the luminance controller 310, DAC, ADC and associated logic fig. 3 [0035-44] “Boost converter 301 receives an input voltage Vin and provides regulated power to LED strings 302”).
Regarding claim 10, Jin as modified further teaches a measuring device (fig. 3 Led driver 300 “LDO 304 comprises a feedback loop that senses the current through the LED string via Vsense and controls the pass transistor Q.sub.L to maintain the sensed current at the programmed current level set by Vref. Op-amp 306 compares Vref to Vsense” [0035-39]), comprising:
a sensor element (fig. 3 sense resistor Rs and associated circuitry producing Vsence [0038-40]);
a voltage supply circuit (voltage supply circuit 301, feedback control and headroom based regulation supplying analog outputs fig. 3 [0035-39, 49-49]) according to claim 1; and
at least one regulator for adjusting a signal to be output at the first analog output (5.1) and/or a signal to be output at the second analog output (5.2) (linear current regulators LDO 304 for each output channel, each to regulate and adjust the signal supplied to the corresponding analog output [0038-42]) which is proportional to a measured value detected by means of the sensor element (the sensed signal Vsense is used by luminance controller 310 to adjust the output current and duty cycle, such that the regulated output signal is proportional to the sensed electrical parameter [0040-44]).
Regarding claim 12, Jin as modified further teaches wherein the voltage supply circuit (1.1, 1.2) comprises at least one voltage regulator for converting the DC supply voltage (8) into an additional DC voltage at a load output for a further load; and comprising at least one further load connected to the load output (voltage supply in which DC/DC converter output Vboost supplies downstream circuitry, including control electronics such as the luminance controller 310, DAC, ADC and associated logic fig. 3 [0035-44] “Boost converter 301 receives an input voltage Vin and provides regulated power to LED strings 302”).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAQI R NASIR whose telephone number is (571)270-1425. The examiner can normally be reached 9AM-5PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAQI R NASIR/ Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858
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