DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 June 2026 has been entered.
Information Disclosure Statement
The information disclosure statement filed 23 June 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language, specifically the Chinese office action. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 8, 10, 12, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Rho et al. (US 2021/0103394) in view of Jeong (US 2015/0187426).
In regards to claims 1 and 21, Rho teaches a storage device comprising:
a nonvolatile memory device (“In the open-channel SSD, a flash translation layer (FTL) 110 may be included in the host system 100.”, paragraph 0029) including a plurality of memory blocks (“The host system 100 may perform a wear-leveling operation on the storage system 200 and evenly manage wear levels of the blocks included in the storage device 220.”, paragraph 0032); and
a memory controller (Controller 210, figure 1) configured to:
provide an external device with block count information indicating whether an erase count of each of the plurality of memory blocks is equal to or greater than a reference value (“During the initialization operation, the host system may request the transmission of erase count values of a plurality of blocks that are stored in the open-channel SSD in a non-volatile manner, and the open-channel SSD may transmit information including the erase count values of the plurality of blocks in response to the request at operation {circle around (2)}. Also, in some embodiments, the open-channel SSD may further transmit information related to a threshold value of an erase count of a block to the host system.”, paragraph 0054);
receive a write command from the external device (“The host system 100 may provide a data write request or a data read request to the storage system 200.”, paragraph 0022);
control the nonvolatile memory device to perform an erase operation on at least one memory block among the plurality of memory blocks (“Referring to FIG. 4, the host system may request an erase operation on the first block included in the storage system, and thus, the storage system may erase the first block and generate a free block at operation S21.”, paragraph 0051);
control the nonvolatile memory device to store data corresponding to the write command in the at least one memory block on which the erase operation has been performed (“A block on which the erase operation is performed may be subsequently assigned as a free block used in a data write operation.”, paragraph 0030); and
update the block count information in the external device (“Also, the host system may update an erase count value corresponding to the first block during the erase operation on the first block at operation S22.”, paragraph 0051).
Rho fails to adequately teach performing the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed. Jeong teaches perform the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed (Steps S330-S350, figure 3; See paragraphs 0052-0054) “thereby preventing the degradation of the retention characteristics of the memory cells” (paragraph 0064). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Rho with Jeong to include performing the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed “thereby preventing the degradation of the retention characteristics of the memory cells” (id.).
In regards to claim 8, Rho teaches a memory controller comprising:
a processor (Controller 210, figure 1; “Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies.”, paragraph 0091) configured to control a nonvolatile memory device (“In the open-channel SSD, a flash translation layer (FTL) 110 may be included in the host system 100.”, paragraph 0029) including a plurality of memory blocks (“The host system 100 may perform a wear-leveling operation on the storage system 200 and evenly manage wear levels of the blocks included in the storage device 220.”, paragraph 0032); and
a memory configured to store block count information indicating whether an erase count of each of the plurality of memory blocks is equal to or greater than a reference value (“During the initialization operation, the host system may request the transmission of erase count values of a plurality of blocks that are stored in the open-channel SSD in a non-volatile manner, and the open-channel SSD may transmit information including the erase count values of the plurality of blocks in response to the request at operation {circle around (2)}. Also, in some embodiments, the open-channel SSD may further transmit information related to a threshold value of an erase count of a block to the host system.”, paragraph 0054),
wherein the processor is further configured to:
provide an external device with block count information value (“During the initialization operation, the host system may request the transmission of erase count values of a plurality of blocks that are stored in the open-channel SSD in a non-volatile manner, and the open-channel SSD may transmit information including the erase count values of the plurality of blocks in response to the request at operation {circle around (2)}. Also, in some embodiments, the open-channel SSD may further transmit information related to a threshold value of an erase count of a block to the host system.”, paragraph 0054);
receive a write command from the external device (“The host system 100 may provide a data write request or a data read request to the storage system 200.”, paragraph 0022);
control the nonvolatile memory device to perform an erase operation on at least one memory block among the plurality of memory blocks (“Referring to FIG. 4, the host system may request an erase operation on the first block included in the storage system, and thus, the storage system may erase the first block and generate a free block at operation S21.”, paragraph 0051);
control the nonvolatile memory device to store data corresponding to the write command in the at least one memory block on which the erase operation has been performed (“A block on which the erase operation is performed may be subsequently assigned as a free block used in a data write operation.”, paragraph 0030); and
update the block count information stored in the external device (“Also, the host system may update an erase count value corresponding to the first block during the erase operation on the first block at operation S22.”, paragraph 0051).
Rho fails to adequately teach performing the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed. Jeong teaches perform the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed (Steps S330-S350, figure 3; See paragraphs 0052-0054) “thereby preventing the degradation of the retention characteristics of the memory cells” (paragraph 0064). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Rho with Jeong to include performing the erase operation on the at least one memory block in which data corresponding to the write command is to be stored, before the write command is executed “thereby preventing the degradation of the retention characteristics of the memory cells” (id.).
In regards to claims 3, 10, and 23, Rho further teaches that the memory controller is further configured to update the block count information in the external device by:
updating the block count information after performing the erase operation on a memory block among the plurality of memory blocks (“After the first block is erased, the host system may request an erase operation on the second block included in the storage system, and the storage system may erase the second block and generate a free block at operation S23, and the host system may update an erase count value corresponding to the second block at operation S24.”, paragraph 0051; “The host system may store information related to the erase count values of the free blocks in the open-channel SSD at specific time points or periodically at operation S93.”, paragraph 0073), and
providing the updated block count information to the external device (“In this case, the host system may request the transmission of information related to the erase count values of the free blocks to the open-channel SSD at operation S95, and the open-channel SSD may transmit information corresponding to the request to the host system at operation S96.”, paragraph 0074).
In regards to claims 5 and 12, Rho further teaches that the memory controller is further configured to:
control the nonvolatile memory device based on the write command received from the external device (“Thereafter, when a new free block is assigned for a data write operation, the erase count value of the first block may be compared with the erase count value of the second block, and it may be confirmed that the erase count value of the second block, which is generated as the free block later than the first block, is lower than the erase count value of the first block at operation S25. Thus, the host system may assign the second block for the data write operation prior to the first block at operation S26.”, paragraph 0052); and
update the block count information when an operation corresponding to the write command is completely performed (“The host system may store information related to the erase count values of the free blocks in the open-channel SSD at specific time points or periodically at operation S93. That is, the host system may temporarily store information related to the various management operations in internal random access memory (RAM), and periodically or aperiodically store the information in a non-volatile storage space of the open-channel SSD.”, paragraph 0073).
Claims 4, 6, 7, 11, 13, 14, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Rho et al. (US 2021/0103394) in view of Jeong (US 2015/0187426) and Monteleone et al. (US 2015/0347038).
In regards to claims 4 and 11, Rho in view of Jeong teaches claims 1 and 8. Rho in view of Jeong fails to teach that the block count information has a value of 1 with respect to a memory block having the erase number equal to or greater than the reference value and has a value of 0 with respect to a memory block having the erase number less than the reference value. Monteleone teaches that the block count information has a value of 1 with respect to a memory block having the erase number equal to or greater than the reference value and has a value of 0 with respect to a memory block having the erase number less than the reference value (“A local write count threshold causing the memory control unit 310 to automatically perform a wear leveling operation may exceed the local write count threshold causing the memory control unit 310 to recommend the host 110 provide a wear leveling command.”, paragraph 0025; “In another example, the memory control unit 310 may be configured to set a bit of the flag status register 350 indicating whether a wear leveling operation is recommended (e.g., the bit of the flag status register 350 having a logic state of ‘1’).”, paragraph 0023) in order to “recommend the host 110 provide a wear leveling command” (paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Rho with Jeong and Monteleone such that the block count information has a value of 1 with respect to a memory block having the erase number equal to or greater than the reference value and has a value of 0 with respect to a memory block having the erase number less than the reference value in order to “recommend the host 110 provide a wear leveling command” (id.).
In regards to claims 6, 13, and 25, Rho in view of Jeong teaches claims 5, 12, and 24. Rho in view of Jeong fails to teach that the memory controller is further configured to provide the external device with the updated block count information simultaneously together with a response message as a result obtained by executing the write command. Monteleone teaches that the memory controller is further configured to provide the external device with the updated block count information simultaneously together with a response message as a result obtained by executing the write command (“For example, the memory control unit 310 may be configured to set a bit of the flag status register 350 having a logic state indicating whether a wear leveling operation is being performed (e.g., the bit of the flag status register 350 having a logic state of ‘I’). In another example, the memory control unit 310 may be configured to set a bit of the flag status register 350 indicating whether a wear leveling operation is recommended (e.g., the bit of the flag status register 350 having a logic state of ‘1’). Acknowledgements provided to the host 110 may be based on one or more bits of the flag status register, and accordingly, whether an acknowledgement recommends the host 110 provide a wear leveling command may be based on a bit of the flag status register 350.”, paragraph 0023) in order to “recommend the host 110 provide a wear leveling command” (paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Rho with Jeong and Monteleone such that the memory controller is further configured to provide the external device with the updated block count information simultaneously together with a response message as a result obtained by executing the write command in order to “recommend the host 110 provide a wear leveling command” (id.).
In regards to claims 7, 14, and 26, Rho in view of Jeong teaches claims 5, 12, and 24. Rho in view of Jeong fails to teach that the memory controller is further configured to provide the external device with a response message as a result obtained by executing the write command and the updated block count information. Monteleone teaches that the memory controller is further configured to provide the external device with a response message as a result obtained by executing the write command and the updated block count information (“For example, the memory control unit 310 may be configured to set a bit of the flag status register 350 having a logic state indicating whether a wear leveling operation is being performed (e.g., the bit of the flag status register 350 having a logic state of ‘I’). In another example, the memory control unit 310 may be configured to set a bit of the flag status register 350 indicating whether a wear leveling operation is recommended (e.g., the bit of the flag status register 350 having a logic state of ‘1’). Acknowledgements provided to the host 110 may be based on one or more bits of the flag status register, and accordingly, whether an acknowledgement recommends the host 110 provide a wear leveling command may be based on a bit of the flag status register 350.”, paragraph 0023) in order to “recommend the host 110 provide a wear leveling command” (paragraph 0018). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Rho with Jeong and Monteleone such that the memory controller is further configured to provide the external device with a response message as a result obtained by executing the write command and the updated block count information in order to “recommend the host 110 provide a wear leveling command” (id.).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-7, 21, 25, and 26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 2, 4, 5, 1, 4, and 5 of U.S. Patent No. 12,056,356. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the claim limitations of these claims in the present application are found verbatim in the claims of the patent.
Claims 3, 8, 10-14, and 23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 1, 1, 3, 2, 4, 5, and 1 of U.S. Patent No. 12,056,356 in view of Rho et al. (US 2021/0103394).
In regards to claims 3 and 23, claim 1 of U.S. Patent No. 12,056,356 further teaches that the memory controller is further configured to update the block count information in the external device by:
updating the block count information (“update the block count information”), and
providing the updated block count information to the external device (“provide the updated block count information to the external device”).
Claim 1 of U.S. Patent No. 12,056,356 fails to teach update the block count information after performing the erase operation on a memory block among the plurality of memory blocks. Rho teaches update the block count information after performing the erase operation on a memory block among the plurality of memory blocks (“After the first block is erased, the host system may request an erase operation on the second block included in the storage system, and the storage system may erase the second block and generate a free block at operation S23, and the host system may update an erase count value corresponding to the second block at operation S24.”, paragraph 0051; “The host system may store information related to the erase count values of the free blocks in the open-channel SSD at specific time points or periodically at operation S93.”, paragraph 0073). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 1 of U.S. Patent No. 12,056,356 with Rho to include update the block count information after performing the erase operation on a memory block among the plurality of memory blocks in order to avoid losing the block count information.
In regards to claim 8, claim 1 of U.S. Patent No. 12,056,356 teaches a memory controller (“a memory controller”) comprising:
a nonvolatile memory device including a plurality of memory blocks (“a nonvolatile memory device including a plurality of memory blocks”); and
block count information indicating whether an erase count of each of the plurality of memory blocks is equal to or greater than a reference value (“block count information … representing whether an erase number of each of the plurality of memory blocks is equal to or greater than a reference value”),
wherein the processor is further configured to:
provide an external device with block count information (“provide an external device with block count information”);
receive a write command from the external device (“a write command received from the external device”);
control the nonvolatile memory device to perform an erase operation on at least one memory block among the plurality of memory blocks in which data corresponding to the write command is to be stored, before the write command is executed (“a memory controller configured to: … perform an erase operation on a memory block in which data corresponding to a write command received from the external device is to be stored before the write command is executed”),
control the nonvolatile memory device to store data corresponding to the write command in the at least one memory block on which the erase operation has been performed (“a memory controller configured to: … data corresponding to a write command received from the external device is to be stored before the write command is executed, store the data in the nonvolatile memory device”); and
update the block count information stored in the external device (“update the block count information, and provide the updated block count information to the external device“).
Claim 1 of U.S. Patent No. 12,056,356 fails to teach a processor configured to control the nonvolatile memory device; and
a memory configured to store the block count information.
Rho teaches a processor configured to control the nonvolatile memory device (Controller 210, figure 1; “Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies.”, paragraph 0091); and
a memory configured to store the block count information (“During the initialization operation, the host system may request the transmission of erase count values of a plurality of blocks that are stored in the open-channel SSD in a non-volatile manner, and the open-channel SSD may transmit information including the erase count values of the plurality of blocks in response to the request at operation {circle around (2)}. Also, in some embodiments, the open-channel SSD may further transmit information related to a threshold value of an erase count of a block to the host system.”, paragraph 0054)
“to increase a lifespan of a storage system and improve data reliability” (paragraph 0005).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine claim 1 of U.S. Patent No. 12,056,356 with Rho to include a processor configured to control the nonvolatile memory device; and
a memory configured to store the block count information
“to increase a lifespan of a storage system and improve data reliability” (id.).
In regards to claim 10, claim 1 of U.S. Patent No. 12,056,356 further teaches that the memory is further configured to:
update the block count information (“update the block count information”), and
provide the updated block count information to an external (“provide the updated block count information to the external device”).
Rho further teaches update the block count information after performing the erase operation on a memory block among the plurality of memory blocks (“After the first block is erased, the host system may request an erase operation on the second block included in the storage system, and the storage system may erase the second block and generate a free block at operation S23, and the host system may update an erase count value corresponding to the second block at operation S24.”, paragraph 0051; “The host system may store information related to the erase count values of the free blocks in the open-channel SSD at specific time points or periodically at operation S93.”, paragraph 0073).
In regards to claims 11-14, claims 3, 2, 4, and 5 of U.S. Patent No. 12,056,356 teach these limitations.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cernea (US 5,508,971) teaches communicating a write command erasing the data sector of the write command before writing the sector of data received. Hoogenboom (US 2007/0090945) teaches a write command with an erase before write option that instructs to erase the flash segment prior to writing the information. Hung (US 2010/0122043) teaches a single program command that includes an erase operation before programming a non-empty program unit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 8 September 2026
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