DETAILED ACTION
Status of Claims
This communication is in applicant’s response filed on 06/25/2026.
Claims 1, 2, 10, and 11 are amended. Claims 6 and 15 are canceled. and Claims 1-5, 7-14 and 16-18 are currently pending and have been examined.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-14, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xin (CN 103995576 A) in view of Knapton (US 2024/0345641 A1) and further in view of Wei-Gen (CN 115167640 A).
Regarding claims 1 and 10:
Xin teaches a power management system used in a computer apparatus, (10. A computer apparatus comprises a power management system;)
Xin teaches wherein the power management system comprises a power supply unit a first power supply, a second power supply, a Complex Programmable Logic Device (CPLD), and a motherboard chipset; the first power supply is electrically connected with the power supply unit and the CPLD and is configured to receive electrical energy of the power supply unit and power the CPLD; the second power supply is electrically connected with the power supply unit, the motherboard chipset, and the CPLD; the motherboard chipset is electrically connected with the CPLD; (By disclosing, 1）The computer hardware system consists of the core chip CPU, bridge chip, etc., and sensors are placed near the main chip to obtain the temperature information of the current chip. Each power supply uses a controllable power chip with an EN enable terminal. As shown in FIG. 2, the implementation method connects the SLP_S3, SLP_S4, and SLP_S5 signals representing the system state (adding GPIO custom signals according to power management requirements) to the CPLD chip, and connects the sensor to the I2C bus. The CPLD is internally programmed and implemented. Information communication of the I2C bus; 2）When the computer is powered on, the BIOS and the kernel driver bridge correspond to I/O (SLP_S3, SLP_S4, SLP_S5). The CPLD chip turns on the power sequentially by identifying the corresponding I/O state. When the computer executes the power management program, the BIOS and the kernel are also driven. The corresponding I/O of the bridge chip, the CPLD chip controls the power supply of the different power modules (power modules 1 - N) by the identification of the signals, thereby realizing the power switching of the state of the computer system S0-S5. Thereby realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, etc. of the computer system. See at least page 1-8)
Xin teaches also teaches realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, however does not specifically mention, wherein in response to a sleep function being enabled and a sleep request, the CPLD generates a sleep control signal to the second power supply, and the second power supply stops powering the motherboard chipset and the target component in response to the sleep control signal; and wherein in response to the sleep function being enabled and a wake instruction, the CPLD outputs a waking signal to the motherboard chipset and the second power supply, the second power supply powers the motherboard chipset and the target component in response to the wake signal, and
However Knapton teaches wherein in response to a sleep function being enabled and a sleep request, the CPLD generates a sleep control signal to the second power supply and wherein in response to the sleep function being enabled and a wake instruction, the CPLD outputs a waking signal to the motherboard chipset and the second power supply, the second power supply powers the motherboard chipset and the target component in response to the wake signal, and the motherboard chipset enters a standby state the motherboard chipset (By disclosing, In FIG. 1, host programmable integrated circuit 110 is configured to execute computer program instructions to perform a variety of different tasks for the information handling system. The host programmable integrated circuit 110 may be implemented using a wide variety of programmable integrated circuits (e.g., such as a controller, microcontroller, microprocessor, ASIC, etc.) and/or programmable logic devices (e.g., a field programmable gate array FPGA”, complex programmable logic device “CPLD”, etc.). In one exemplary embodiment, host programmable integrated circuit 110 may include at least one central processing unit (CPU), e.g., such as an Intel central processing unit (CPU), an Advanced Micro Devices (AMD) CPU or another type of host programmable integrated circuit. The global power states include: the working (G0) state (also referred to as the SO state), the sleeping (G1) state, the soft off (G2) state (also referred to as the S5 state) and the mechanical off (G3) state. During the working (G0/S0) state, PSU 190 supplies power to various system components and the host programmable integrated circuit 110 is executing instructions. Power is removed from the system (e.g., via a mechanical relay on the PSU) during the mechanical off (G3) state. The soft off (G2) state is similar to the mechanical off (G3) state with the exception that the PSU 190 supplies power to the power button (and possibly other components) to allow the system to return to the working (S0) state. When configured in the G3 and G2 states, the system must be restarted to return to the working (S0) state. The global sleeping (G1) state includes a plurality of lower power states that can be used to reduce power consumption within the system, while enabling the system to quickly transition from a lower power state to the active working (S0) state. The G1 sleeping states traditionally include: the S1 sleeping state (in which power is maintained to the CPU and RAM), the S2 sleeping state (in which the CPU is powered off), the S3 sleeping state (traditionally referred to as standby or sleep) and the S4 sleeping state (i.e., hibernation). As noted above, some information handling systems provide support for a seventh low power state, referred to as the modern standby (S0ix) state or low power SO idle state. The system power can be toggled on/off when operating in modern standby. This allows background activity to continue while the system appears to be “off” and provides a simplified wake process and a faster transition from a lower power state to the active working state. Host programmable integrated circuit 110 executes program instructions to control power state transitions for the information handling system 100, including system power state transitions from a higher power state to a lower power state (and vice versa). For example, the host programmable integrated circuit 110 may execute a first set of program instructions (contained, e.g., within OS 162, BIOS 172 and/or ACPI 174) to generate a modern standby (MODs) signal, which may be used to transition the information handling system 100 from a working (S0) state to a modern standby (S0ix) state (and vice versa). In some embodiments, the modern standby (MODs) signal may be asserted (e.g., high) to enter the modern standby (S0ix) state and de-asserted (e.g., low) to exit the modern standby (S0ix) state, as shown in FIG. 4 and discussed in more detail below. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Xinin view of Knapton does not specifically disclose in response to a sleep function being enabled and a sleep request, the CPLD generates a sleep control signal to the second power supply, and the second power supply stops powering the motherboard chipset.
However Wei-gen teaches wherein in response to a sleep function being enabled and a sleep request, the CPLD generates a sleep control signal to the second power supply, and the second power supply stops powering in response to the sleep control signal; and wherein in response to the sleep function being enabled and a wake instruction, the CPLD outputs a waking signal to the second power supply, the second power supply powers component in response to the wake signal (By disclosing, The notebook is connected to the CPLD pin, and the notebook enters the S0 state from the S5 state. after receiving the power-on signal, outputting a high level through the CPLD control pin according to the time-on-flight FT 2000 processor and the power-on time sequence of the bridge, and sequentially supplying power to each power conversion module to enable the notebook to work normally; when the notebook enters the sleep state, the CPLD enters the S 3 state from the S 0 state, the CPLD detects the sleep management signal, and according to the S 3 state power supply requirement, the CPLD outputs a low level to turn off the S 0 state power supply enable signal through the control pin, only reserves the S 3 state power supply, and the notebook suspends the memory; when the notebook enters the S 5 state from the S 0 state, the CPLD detects the shutdown signal, and according to the S 5 state power supply requirement, the CPLD outputs a low level to turn off the S 0 state power supply enable signal through the control pin, and only retains the S 5 state power supply and the notebook shutdown; When the notebook enters the S 0 state from the S 3 state, the CPLD detects the wake-up management signal, and enables the power supply and the notebook to work normally according to the power supply requirement of the S 0 state. As shown in FIG. 2, the charging and temperature control system module: See at least description in English translation attached with the office action) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu in view of Knapton with the technique of controlling second power supply as disclosed by Wei-gen because it will reduce power consumption between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 2 and 11:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin teaches also teaches realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, however does not specifically mention following. Knapton teaches wherein the motherboard chipset is a platform controller hub; (By disclosing, platform controller hub (PCH) 150. See at least paragraphs [0022]-[0036])
Knapton teaches the power management system further comprises a magnetic disk; the magnetic disk is electrically connected with the motherboard chipset; the motherboard chipset is further configured to store running information into the magnetic disk in response to the sleep request. (By disclosing, [0070] It will also be understood that one or more of the tasks, functions, or methodologies described herein (e.g., including those described herein for components 110, 130, 140, 150, 152, 154, 160, 170, 180, 186, 190, 192, etc.) may be implemented by circuitry and/or by a computer program of instructions (e.g., computer readable code such as firmware code or software code) embodied in a non-transitory tangible computer readable medium (e.g., optical disk, magnetic disk, non-volatile memory device, etc.). See at least paragraph [0070]) (examiner notes referring to paragraph [0070] and fig. 1 that PCH 150 is electrically connected to multiple components and capable of storing running information into any of them. Specifically paragraph 0031 disclsoe FIG. 1, the ACPI firmware 174 stored within computer readable NV memory 170 serves as an interface layer between boot firmware 172 and OS 162 and brings power management under the control of the operating system power management system (OSPM). Under the OSPM, the OS 162 directs all system, programmable integrated circuit (e.g., processor) and device power state transitions. For example, the OS 162 may use information from applications and user settings to transition the information handling system 100 between a plurality of system power states, which are defined by the ACPI specification.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 3 and 12:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the second power supply comprises a standby power supply and a motherboard chip power supply; the target component comprises a Baseboard Management Controller (BMC), and a Peripheral Component Interconnect Express (PCIE) slot, and a clock; the standby power supply is electrically connected with the power supply unit, the BMC, the PCIE slot, the clock, and the motherboard chipset; the motherboard chip power supply is electrically connected to the power supply unit and the motherboard chipset. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 4 and 13:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin further teaches wherein the power management system further comprises a main power supply; the target component further comprises a Central Processing Unit (CPU) and a Random Access Memory (RAM); the main power supply is electrically connected with the power supply unit, the CPU, and the RAM. (See at least page 1-8)
Regarding claims 5 and 14:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin further teaches wherein the power management system further comprises a power supply button; the power supply button is electrically connected with the first power supply and the CPLD; the first power supply is further configured to power the power supply button; the power supply button is configured to generate and transmit the wake instruction while being pressed. (See at least page 1-8)
Regarding claims 7 and 16:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the motherboard chipset is further configured to acquire and resume the running information from the magnetic disk in response to the waking signal. (See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of retaining a waking function and disables other functions itself in response to the sleep instruction as disclosed by Knapton because to control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 8 and 17:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the CPLD is further retains a waking function and disables other functions itself in response to the sleep instruction. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of retaining a waking function and disables other functions itself in response to the sleep instruction as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 8 and 18:
Xinin view of Knapton and Wei-gen teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the CPLD is further configured to start all functions itself in response to the waking instruction. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of start all functions itself in response to the waking instruction as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of a new ground of rejection initiated based on the current claim amendments.
Conclusion
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/NEHA PATEL/Supervisory Patent Examiner, Art Unit 3699
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