DETAILED ACTION
Status of Claims
This communication is in applicant’s response filed on 02/11/2026.
Claims 1, 7, 10, and 16 are amended. Claims 6 and 15are canceled. and Claims 1-5, 7-14 and 16-18 are currently pending and have been examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-14, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Xin (CN 103995576 A) in view of Knapton (US 2024/0345641 A1).
Regarding claims 1 and 10:
Xin teaches a power management system used in a computer apparatus, (10. A computer apparatus comprises a power management system;)
Xin teaches wherein the power management system comprises a power supply unit a first power supply, a second power supply, a Complex Programmable Logic Device (CPLD), and a motherboard chipset; the first power supply is electrically connected with the power supply unit and the CPLD and is configured to receive electrical energy of the power supply unit and power the CPLD; the second power supply is electrically connected with the power supply unit, the motherboard chipset, and the CPLD and is configured to receive the electrical energy of the power supply unit and power, the motherboard chipset, and a target component; the motherboard chipset is electrically connected with the CPLD; (By disclosing, 1）The computer hardware system consists of the core chip CPU, bridge chip, etc., and sensors are placed near the main chip to obtain the temperature information of the current chip. Each power supply uses a controllable power chip with an EN enable terminal. As shown in FIG. 2, the implementation method connects the SLP_S3, SLP_S4, and SLP_S5 signals representing the system state (adding GPIO custom signals according to power management requirements) to the CPLD chip, and connects the sensor to the I2C bus. The CPLD is internally programmed and implemented. Information communication of the I2C bus; 2）When the computer is powered on, the BIOS and the kernel driver bridge correspond to I/O (SLP_S3, SLP_S4, SLP_S5). The CPLD chip turns on the power sequentially by identifying the corresponding I/O state. When the computer executes the power management program, the BIOS and the kernel are also driven. The corresponding I/O of the bridge chip, the CPLD chip controls the power supply of the different power modules (power modules 1 - N) by the identification of the signals, thereby realizing the power switching of the state of the computer system S0-S5. Thereby realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, etc. of the computer system. See at least page 1-8)
Xin teaches also teaches realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, however does not specifically mention, the motherboard chipset is configured to enter a sleep mode in response to a sleep request and output a sleep instruction to the CPLD; the CPLD outputs a sleep control signal to the second power supply in response to the sleep instruction; the second power supply stops powering the motherboard chipset and the target component in response to the sleep control signal. wherein the motherboard chipset is a platform controller hub; the power management system further comprises a magnetic disk; the magnetic disk is electrically connected with the motherboard chipset; the motherboard chipset is further configured to store running information into the magnetic disk in response to the sleep request.
However Knapton teaches the motherboard chipset is configured to enter a sleep mode in response to a sleep request and output a sleep instruction to the CPLD; the CPLD outputs a sleep control signal to the second power supply in response to the sleep instruction; the second power supply stops powering the motherboard chipset and the target component in response to the sleep control signal. (By disclosing, In FIG. 1, host programmable integrated circuit 110 is configured to execute computer program instructions to perform a variety of different tasks for the information handling system. The host programmable integrated circuit 110 may be implemented using a wide variety of programmable integrated circuits (e.g., such as a controller, microcontroller, microprocessor, ASIC, etc.) and/or programmable logic devices (e.g., a field programmable gate array FPGA”, complex programmable logic device “CPLD”, etc.). In one exemplary embodiment, host programmable integrated circuit 110 may include at least one central processing unit (CPU), e.g., such as an Intel central processing unit (CPU), an Advanced Micro Devices (AMD) CPU or another type of host programmable integrated circuit. The global power states include: the working (G0) state (also referred to as the SO state), the sleeping (G1) state, the soft off (G2) state (also referred to as the S5 state) and the mechanical off (G3) state. During the working (G0/S0) state, PSU 190 supplies power to various system components and the host programmable integrated circuit 110 is executing instructions. Power is removed from the system (e.g., via a mechanical relay on the PSU) during the mechanical off (G3) state. The soft off (G2) state is similar to the mechanical off (G3) state with the exception that the PSU 190 supplies power to the power button (and possibly other components) to allow the system to return to the working (S0) state. When configured in the G3 and G2 states, the system must be restarted to return to the working (S0) state. The global sleeping (G1) state includes a plurality of lower power states that can be used to reduce power consumption within the system, while enabling the system to quickly transition from a lower power state to the active working (S0) state. The G1 sleeping states traditionally include: the S1 sleeping state (in which power is maintained to the CPU and RAM), the S2 sleeping state (in which the CPU is powered off), the S3 sleeping state (traditionally referred to as standby or sleep) and the S4 sleeping state (i.e., hibernation). As noted above, some information handling systems provide support for a seventh low power state, referred to as the modern standby (S0ix) state or low power SO idle state. The system power can be toggled on/off when operating in modern standby. This allows background activity to continue while the system appears to be “off” and provides a simplified wake process and a faster transition from a lower power state to the active working state. Host programmable integrated circuit 110 executes program instructions to control power state transitions for the information handling system 100, including system power state transitions from a higher power state to a lower power state (and vice versa). For example, the host programmable integrated circuit 110 may execute a first set of program instructions (contained, e.g., within OS 162, BIOS 172 and/or ACPI 174) to generate a modern standby (MODs) signal, which may be used to transition the information handling system 100 from a working (S0) state to a modern standby (S0ix) state (and vice versa). In some embodiments, the modern standby (MODs) signal may be asserted (e.g., high) to enter the modern standby (S0ix) state and de-asserted (e.g., low) to exit the modern standby (S0ix) state, as shown in FIG. 4 and discussed in more detail below. See at least paragraphs [0024]-[0048])
Knapton teaches wherein the motherboard chipset is a platform controller hub; (By disclosing, platform controller hub (PCH) 150. See at least paragraphs [0022]-[0036])
Knapton teaches the power management system further comprises a magnetic disk; the magnetic disk is electrically connected with the motherboard chipset; the motherboard chipset is further configured to store running information into the magnetic disk in response to the sleep request. (By disclosing, [0070] It will also be understood that one or more of the tasks, functions, or methodologies described herein (e.g., including those described herein for components 110, 130, 140, 150, 152, 154, 160, 170, 180, 186, 190, 192, etc.) may be implemented by circuitry and/or by a computer program of instructions (e.g., computer readable code such as firmware code or software code) embodied in a non-transitory tangible computer readable medium (e.g., optical disk, magnetic disk, non-volatile memory device, etc.). See at least paragraph [0070]) (examiner notes referring to paragraph [0070] and fig. 1 that PCH 150 is electrically connected to multiple components and capable of storing running information into any of them. Specifically paragraph 0031 disclsoe FIG. 1, the ACPI firmware 174 stored within computer readable NV memory 170 serves as an interface layer between boot firmware 172 and OS 162 and brings power management under the control of the operating system power management system (OSPM). Under the OSPM, the OS 162 directs all system, programmable integrated circuit (e.g., processor) and device power state transitions. For example, the OS 162 may use information from applications and user settings to transition the information handling system 100 between a plurality of system power states, which are defined by the ACPI specification.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 2 and 11:
Xinin view of Knapton teaches limitation shown above. Xin teaches also teaches realizing power management of functions such as power-on, standby, hibernation, wake-up, shutdown, however does not specifically mention following. Knapton teaches The power management system of claim 1, wherein the CPLD also responses to a wake instruction, and outputs a waking signal to the motherboard chipset and the second power supply; the motherboard chipset also may enter a standby state in responses to the waking signal; the second power supply also may power the motherboard chipset and the target component in response to the waking signal. (By disclosing, In FIG. 1, host programmable integrated circuit 110 is configured to execute computer program instructions to perform a variety of different tasks for the information handling system. The host programmable integrated circuit 110 may be implemented using a wide variety of programmable integrated circuits (e.g., such as a controller, microcontroller, microprocessor, ASIC, etc.) and/or programmable logic devices (e.g., a field programmable gate array “FPGA”, complex programmable logic device “CPLD”, etc.). In one exemplary embodiment, host programmable integrated circuit 110 may include at least one central processing unit (CPU), e.g., such as an Intel central processing unit (CPU), an Advanced Micro Devices (AMD) CPU or another type of host programmable integrated circuit. The global power states include: the working (G0) state (also referred to as the SO state), the sleeping (G1) state, the soft off (G2) state (also referred to as the S5 state) and the mechanical off (G3) state. During the working (G0/S0) state, PSU 190 supplies power to various system components and the host programmable integrated circuit 110 is executing instructions. Power is removed from the system (e.g., via a mechanical relay on the PSU) during the mechanical off (G3) state. The soft off (G2) state is similar to the mechanical off (G3) state with the exception that the PSU 190 supplies power to the power button (and possibly other components) to allow the system to return to the working (S0) state. When configured in the G3 and G2 states, the system must be restarted to return to the working (S0) state. The global sleeping (G1) state includes a plurality of lower power states that can be used to reduce power consumption within the system, while enabling the system to quickly transition from a lower power state to the active working (S0) state. The G1 sleeping states traditionally include: the S1 sleeping state (in which power is maintained to the CPU and RAM), the S2 sleeping state (in which the CPU is powered off), the S3 sleeping state (traditionally referred to as standby or sleep) and the S4 sleeping state (i.e., hibernation). As noted above, some information handling systems provide support for a seventh low power state, referred to as the modern standby (S0ix) state or low power SO idle state. The system power can be toggled on/off when operating in modern standby. This allows background activity to continue while the system appears to be “off” and provides a simplified wake process and a faster transition from a lower power state to the active working state. Host programmable integrated circuit 110 executes program instructions to control power state transitions for the information handling system 100, including system power state transitions from a higher power state to a lower power state (and vice versa). For example, the host programmable integrated circuit 110 may execute a first set of program instructions (contained, e.g., within OS 162, BIOS 172 and/or ACPI 174) to generate a modern standby (MODs) signal, which may be used to transition the information handling system 100 from a working (S0) state to a modern standby (S0ix) state (and vice versa). In some embodiments, the modern standby (MODs) signal may be asserted (e.g., high) to enter the modern standby (S0ix) state and de-asserted (e.g., low) to exit the modern standby (S0ix) state, as shown in FIG. 4 and discussed in more detail below. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 3 and 12:
Xinin view of Knapton teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the second power supply comprises a standby power supply and a motherboard chip power supply; the target component comprises a Baseboard Management Controller (BMC), and a Peripheral Component Interconnect Express (PCIE) slot, and a clock; the standby power supply is electrically connected with the power supply unit, the BMC, the PCIE slot, the clock, and the motherboard chipset; the motherboard chip power supply is electrically connected to the power supply unit and the motherboard chipset. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of controlling sleep control cycle as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 4 and 13:
Xinin view of Knapton teaches limitation shown above. Xin further teaches wherein the power management system further comprises a main power supply; the target component further comprises a Central Processing Unit (CPU) and a Random Access Memory (RAM); the main power supply is electrically connected with the power supply unit, the CPU, and the RAM. (See at least page 1-8)
Regarding claims 5 and 14:
Xinin view of Knapton teaches limitation shown above. Xin further teaches wherein the power management system further comprises a power supply button; the power supply button is electrically connected with the first power supply and the CPLD; the first power supply is further configured to power the power supply button; the power supply button is configured to generate and transmit the wake instruction while being pressed. (See at least page 1-8)
Regarding claims 7 and 16:
Xinin view of Knapton teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the motherboard chipset is further configured to acquire and resume the running information from the magnetic disk in response to the waking signal. (See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of retaining a waking function and disables other functions itself in response to the sleep instruction as disclosed by Knapton because to control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 8 and 17:
Xinin view of Knapton teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the CPLD is further retains a waking function and disables other functions itself in response to the sleep instruction. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of retaining a waking function and disables other functions itself in response to the sleep instruction as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Regarding claims 8 and 18:
Xinin view of Knapton teaches limitation shown above. Xin does not specifically disclose following, Howevver Knapton teaches wherein the CPLD is further configured to start all functions itself in response to the waking instruction. See at least paragraphs [0024]-[0048]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine a power management system as disclosed by Xiu with the technique of start all functions itself in response to the waking instruction as disclosed by Knapton because it will efficiently control power consumption and reduce time between power cycles. Furthermore, merely combining well known elements in the prior art with predictable results does not render an invention patentably distinct over such combination.
Response to Arguments
As to the remark, Applicant asserted that Neither Xin nor Knapton discloses the motherboard chipset outputs a sleep instruction to the CPLD, and the CPLD outputs a sleep control signal to the second power supply in response to the sleep instruction; the motherboard chipset is further configured to store running information into the magnetic disk in response to the sleep request.
Examiner respectfully traverses Applicant’s remark for the following reasons: Prior art Knapton relied upon to disclose the motherboard chipset (PCH 150) outputs a sleep instruction to the CPLD, and the CPLD outputs a sleep control signal to the second power supply (PSU 190) in response to the sleep instruction; the motherboard chipset is further configured to store running information into the magnetic disk in response to the sleep request. (By disclosing, PSU 190 converts the alternating current (AC) received from the AC mains to low voltage direct current (DC), which is used to operate various power-consuming hardware components of the information handling system 100 (such as, e.g., the system motherboard, programmable integrated circuits, memory, storage devices, video cards, network cards, peripherals and/or other external devices, etc.). As shown in FIG. 1, PSU 190 provides DC current and power to the various power-consuming hardware components via a plurality of voltage rails. For example, power supply units that comply with the ATX standard may provide three positive voltage rails (+3.3 VDC, +5 VDC and +12 VDC) and one negative voltage rail (−12 VDC). In addition, a +5V standby (SB) voltage rail may be provided to support standby functions and power certain peripherals when the information handling system 100 is in a low power state (e.g., standby, sleep and hibernation states). As shown in FIG. 1, PSU 190 includes a programmable integrated circuit (IC) 192, and a mechanical relay (referred to herein as PSU relay 194) that itself is electrically coupled to control (i.e., allow or disallow) flow of DC current and power to voltage rails from the PSU 190. The PSU programmable integrated circuit 192 is coupled to receive an active low power supply on (PS_ON #) signal from the system motherboard or SoC (via the PCH 150) and is configured to control operation of the PSU relay 194. [0044] The information handling system 100 shown in FIGS. 1 and 3 represents one embodiment of an improved information handling system that utilizes the techniques described herein to control operation of the PSU 190 during a low power state, and more specifically, to control operation of the PSU relay 194 when the information handling system 100 is entering, operating within, and exiting the modern standby (S0ix) state. [0045] The techniques described herein may generally be implemented as computer program instructions, which are locally stored and executed within an information handling system, such as but not limited to, the information handling system 100 shown in FIGS. 1 and 3 (described below). For example, the techniques described herein may be implemented as computer program instructions, which are stored within at least one non-transitory memory (such as, e.g., system memory 120, storage device 160, NV memory 170 and/or EC RAM 184) and executed by at least one programmable integrated circuit (e.g., host programmable integrated circuit 110, EC programmable integrated circuit 186 and/or PSU programmable integrated circuit 192). It will be understood that, while FIGS. 1 and 3 provide one example of information handling system components that can be used to implement the techniques described herein, the disclosed techniques are not strictly limited to only those components shown in the figures. In some embodiments, other programmable integrated circuits not shown in FIGS. 1 and 3 may be utilized to implement the techniques disclosed herein. For example, another programmable integrated circuit or out-of-band (OOB) programmable integrated circuit (e.g., a baseboard management controller (BMC)) may be utilized in place of the EC 180 that is shown in FIGS. 1 and 3. Examiner notes referring to paragraph [0070] and fig. 1 that PCH 150 is electrically connected to multiple components and capable of storing running information into any of them. Specifically paragraph 0031 disclose FIG. 1, the ACPI firmware 174 stored within computer readable NV memory 170 serves as an interface layer between boot firmware 172 and OS 162 and brings power management under the control of the operating system power management system (OSPM). Under the OSPM, the OS 162 directs all system, programmable integrated circuit (e.g., processor) and device power state transitions. For example, the OS 162 may use information from applications and user settings to transition the information handling system 100 between a plurality of system power states, which are defined by the ACPI specification.)
Conclusion
Applicant’s arguments with respect to claims have been considered but they are not persuasive. Accordingly, THIS ACTION IS MADE FINAL.
Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NEHA PATEL/Supervisory Patent Examiner, Art Unit 3699