DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tiziani et al. (US PUB 2024/0329098), hereinafter Tiziani.
With respect to claim 1, Tiziani discloses an electronic device, comprising: a multilevel package substrate (See figure 1J in view of paragraph [0005] of Tiziani) having a top level (See the surface shown in figure 1J of Tiziani comprising traces [100]) and a bottom level (See paragraph [0110] of Tiziani), the top level including a conductive U-shaped trace (See [182] in figure 2 of Tiziani), the bottom level including a conductive lead exposed along a side of the electronic device (See paragraph [0110] of Tiziani); a semiconductor die attached to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) and having a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and a package structure that encloses a portion of the semiconductor die and a portion of the U-shaped trace (See the abstract of Tiziani).
With respect to claim 2, Tiziani discloses the electronic device of claim 1, further comprising a surface mount component with terminals soldered to pads of the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 3, Tiziani discloses the electronic device of claim 1, wherein the bottom level includes conductive split pads spaced apart from the conductive lead (See paragraph [0110] of Tiziani) and exposed along the side of the electronic device (See paragraph [0110] in view of paragraph [0130] of Tiziani).
With respect to claim 4, Tiziani discloses the electronic device of claim 1, wherein the conductive lead has an indent along the side of the electronic device (See indent [101] in figure 4 of Tiziani).
With respect to claim 5, Tiziani discloses the electronic device of claim 1, wherein the conductive lead has a plated surface exposed along the side of the electronic device (See paragraphs [0063] and [0079] of Tiziani).
With respect to claim 6, Tiziani discloses the electronic device of claim 1, wherein the package structure includes a magnetic material (See paragraphs [0098] and [0124] of Tiziani).
With respect to claim 7, Tiziani discloses the electronic device of claim 6, wherein the multilevel package substrate includes a magnetic material (See paragraphs [0098] and [0124] of Tiziani).
With respect to claim 8, Tiziani discloses the electronic device of claim 1, wherein the multilevel package substrate includes a magnetic material (See paragraphs [0098] and [0124] of Tiziani).
With respect to claim 9, Tiziani discloses a system, comprising: a circuit board having a conductive trace (See paragraph [0030] of Tiziani); and an electronic device (See paragraph [0030] of Tiziani), comprising: a multilevel package substrate (See figure 1J in view of paragraph [0005] of Tiziani) having a top level (See the surface shown in figure 1J of Tiziani comprising traces [100]) and a bottom level (See paragraph [0110] of Tiziani), the top level including a conductive U-shaped trace (See [182] in figure 2 of Tiziani), the bottom level including a conductive lead exposed along a side of the electronic device (See paragraph [0110] of Tiziani) and attached to the conductive trace (See paragraph [0112] of Tiziani); a semiconductor die attached to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) and having a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and a package structure that encloses a portion of the semiconductor die and a portion of the U-shaped trace (See the abstract of Tiziani).
With respect to claim 10, Tiziani discloses the system of claim 9, wherein the electronic device further comprises a surface mount component with terminals soldered to pads of the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 11, Tiziani discloses the system of claim 9, wherein the bottom level includes conductive split pads spaced apart from the conductive lead (See paragraph [0110] of Tiziani) and exposed along the side of the electronic device (See paragraph [0110] of Tiziani).
With respect to claim 12, Tiziani discloses the system of claim 9, wherein the package structure includes a magnetic material (See paragraphs [0098] and [0124] of Tiziani).
With respect to claim 13, Tiziani discloses the system of claim 9, wherein the multilevel package substrate includes a magnetic material (See paragraphs [0098] and [0124] of Tiziani).
With respect to claim 14, Tiziani discloses a method of fabricating an electronic device (See figure 1J in view of paragraph [0005] of Tiziani), the method comprising: forming a conductive U-shaped trace (See [182] in figure 2 of Tiziani) in a top level of a multilevel package substrate (See the surface shown in figure 1J of Tiziani comprising traces [100]); forming a conductive lead in a bottom level of the multilevel package substrate (See paragraph [0110] of Tiziani); attaching a semiconductor die to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) with a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and molding a package structure that encloses the U-shaped trace (See the abstract of Tiziani).
With respect to claim 15, Tiziani discloses the method of claim 14, further comprising: forming pads in the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani); and attaching a surface mount component to the top level of the multilevel package substrate with terminals soldered to the pads (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 16, Tiziani discloses the method of claim 14, further comprising forming raised studs on the top level of the multilevel package substrate (See paragraph [0116] of Tiziani).
With respect to claim 17, Tiziani discloses the method of claim 14, comprising forming conductive split pads in the bottom level of the multilevel package substrate (See paragraph [0110] of Tiziani).
With respect to claim 18, Tiziani discloses the method of claim 14, further comprising forming an indent in the conductive lead along the side of the electronic device (See indent [101] in figure 4 of Tiziani).
With respect to claim 19, Tiziani discloses the method of claim 14, further comprising forming a plated surface on the conductive lead (See paragraphs [0063] and [0079] of Tiziani).
With respect to claim 20, Tiziani discloses the method of claim 14, comprising incorporating a magnetic material in the multilevel package substrate or the package structure (See paragraphs [0098] and [0124] of Tiziani).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PUB 2015/0179587 discloses a method for making semiconductor device for e.g. mobile phone, involves forming stress relief insulating layer over semiconductor die and encapsulant, and forming interconnect structure over stress relief insulating layer
US PUB 2005/0218486 discloses an assembly for ball grid array packaged semiconductor device, has bond wires to couple bond pads formed on die and conducting land area formed on electrically conductive layer and to couple pad to conductive trace formed on conductive layer.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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