DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments directed to claims 1-3, 5, 9-11, 14-17 and 19, filed 07/28/2026, have been fully considered but they are not persuasive. However, arguments directed to claims 4, 6, 7, 8, 12, 13, 18 and 20 are convincing and the examiner therefore withdraws the rejections of said claims respectively in view of the new grounds of rejection presented below.
With respect to the arguments directed to claim 1, the examiner maintains the rejection of record on the basis that the reference recites all essential elements claimed. For example, the “multilevel package substrate” claimed is anticipated by the structure shown in figure 1J with the bottom and top levels being interpreted as shown in the annotated figure 1J below:
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This clearly demonstrates a multilevel substrate. Furthermore, the applicant’s claim that this portion of the structure couldn’t possibly constitute a substrate because it fails to provide mechanical support, electrical pathways and thermal management; without providing any substantive evidence from the reference to support such assertion. The examiner contends that the region defined by the examiner above is configured to perform all three functions in that metallic connections provide electrical pathways and efficient thermal conductivity typical of metals, while the epoxy resin molding compound [20’] provides structural support.
With respect to applicant’s arguments directed to claim 2, they are rebutted on the same basis as claim 1 above. Furthermore, the applicant’s arguments rely on disclosure from the specification, not the claim itself and thus fails to adequately distinguish the claim from the reference. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., "the present specification clearly teaches that the top level 141, having metal contacts 121, 123, of multilevel package substrate 107 is attached to the bottom surface of package structure 108. The present specification further teaches that the bottom level 142 of multilevel package substrate 107 is attached to the circuit board 130. Thus, the present specification teaches that the component with terminals is soldered to pad on the top level 141 of multilevel
package substrate 107") are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the examiner maintains that paragraphs [0079] and [0093] of the cited reference teaches the claimed limitations.
With respect to the applicant’s arguments directed to claim 3, the examiner respectfully traverses and asserts that the cited reference indeed teaches the claimed limitations (See figure 1J in view of paragraphs [0110] and [0130]).
With respect to claim 4, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
With respect to claim 5, the claim depends from rejected claim 1 and as such is similarly rejected.
With respect to claim 6, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
Claim 7 depends from claim 6 and thus the rejection of record is withdrawn.
With respect to claim 8, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
With respect to claim 9, the examiner respectfully traverses the applicant’s arguments for the same reasons presented with respect to claim 1 above. Therefore, the rejection is maintained on this basis.
With respect to applicant’s argument directed to claim 10, they are rebutted on the same basis as claim 9 above. Furthermore, the applicant’s arguments rely on disclosure from the specification, not the claim itself and thus fails to adequately distinguish the claim from the reference. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., "the present specification clearly teaches that the top level 141, having metal contacts 121, 123, of multilevel package substrate 107 is attached to the bottom surface of package structure 108. The present specification further teaches that the bottom level 142 of multilevel package substrate 107 is attached to the circuit board 130. Thus, the present specification teaches that the component with terminals is soldered to pad on the top level 141 of multilevel
package substrate 107") are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the examiner maintains that paragraphs [0079] and [0093] of the cited reference teaches the claimed limitations. The examiner maintains that the reference citation teaches the claimed limitation.
With respect to the applicant’s arguments directed to claim 11, the examiner respectfully traverses and asserts that the cited reference indeed teaches the claimed limitations (See figure 1J in view of paragraphs [0110] and [0130]).
With respect to claim 12, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
With respect to claim 13, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
With respect to the arguments directed to claim 14, the examiner maintains the rejection of record on the basis that the reference recites all essential elements claimed. For example, the “multilevel package substrate” claimed is anticipated by the structure shown in figure 1J with the bottom and top levels being interpreted as shown in the annotated figure 1J below:
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This clearly demonstrates a multilevel substrate. Furthermore, the applicant’s claim that this portion of the structure couldn’t possibly constitute a substrate because it fails to provide mechanical support, electrical pathways and thermal management; without providing any substantive evidence from the reference to support such assertion. The examiner contends that the region defined by the examiner above is configured to perform all three functions in that metallic connections provide electrical pathways and efficient thermal conductivity typical of metals, while the epoxy resin molding compound [20’] provides structural support.
With respect to applicant’s arguments directed to claim 15, they are rebutted on the same basis as claim 1 above. Furthermore, the applicant’s arguments rely on disclosure from the specification, not the claim itself and thus fails to adequately distinguish the claim from the reference. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., "the present specification clearly teaches that the top level 141, having metal contacts 121, 123, of multilevel package substrate 107 is attached to the bottom surface of package structure 108. The present specification further teaches that the bottom level 142 of multilevel package substrate 107 is attached to the circuit board 130. Thus, the present specification teaches that the component with terminals is soldered to pad on the top level 141 of multilevel
package substrate 107") are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the examiner maintains that paragraphs [0079] and [0093] of the cited reference teaches the claimed limitations.
With respect to applicant’s arguments directed to claim 16, the examiner asserts that they are similarly rebutted in like manner to claim 14 above. Furthermore, the applicant’s arguments rely on disclosure from the specification, not the claim itself and thus fails to adequately distinguish the claim from the reference. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the present specification clearly teaches that the top level 141, having metal contacts 121, 123, of multilevel package substrate 107 is attached to the bottom surface of package structure 108. The present specification further teaches that the bottom level 142 of multilevel package substrate 107 is attached to the circuit board 130. Thus the present specification teaches that the component with terminals is soldered to pad on the top level 141 of multilevel package substrate 107") are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the examiner maintains that paragraphs [0079] and [0093] of the cited reference teaches the claimed limitations. In the arguments pertaining to claim 16, the applicant fails to directly address the application of paragraph [0116] of Tiziani by the examiner.
With respect to the applicant’s arguments directed to claim 17, the examiner respectfully traverses and asserts that the cited reference indeed teaches the claimed limitations (See figure 1J in view of paragraph [0110]).
With respect to claim 18, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
With respect to claim 19, the examiner maintains his rejection as presented in the official correspondence. Namely on the basis of paragraphs [0063] and [0079] of Tiziani. Paragraph [0079] specifically teaches a plating method step. Therefore, the examiner asserts that the reference anticipates the limitation in question.
With respect to claim 20, the examiner concedes that the reference fails to teach or suggest the claimed limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 9-11, 14-17 and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tiziani et al. (US PUB 2024/0329098), hereinafter Tiziani [Cited in previous Office Action].
With respect to claim 1, Tiziani discloses an electronic device, comprising: a multilevel package substrate (See figure 1J in view of paragraph [0005] of Tiziani) having a top level (See the surface shown in figure 1J of Tiziani comprising traces [100]) and a bottom level (See paragraph [0110] of Tiziani), the top level including a conductive U-shaped trace (See [182] in figure 2 of Tiziani), the bottom level including a conductive lead exposed along a side of the electronic device (See paragraph [0110] of Tiziani); a semiconductor die attached to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) and having a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and a package structure that encloses a portion of the semiconductor die and a portion of the U-shaped trace (See the abstract of Tiziani).
With respect to claim 2, Tiziani discloses the electronic device of claim 1, further comprising a surface mount component with terminals soldered to pads of the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 3, Tiziani discloses the electronic device of claim 1, wherein the bottom level includes conductive split pads spaced apart from the conductive lead (See paragraph [0110] of Tiziani) and exposed along the side of the electronic device (See paragraph [0110] in view of paragraph [0130] of Tiziani).
With respect to claim 5, Tiziani discloses the electronic device of claim 1, wherein the conductive lead has a plated surface exposed along the side of the electronic device (See paragraphs [0063] and [0079] of Tiziani).
With respect to claim 9, Tiziani discloses a system, comprising: a circuit board having a conductive trace (See paragraph [0030] of Tiziani); and an electronic device (See paragraph [0030] of Tiziani), comprising: a multilevel package substrate (See figure 1J in view of paragraph [0005] of Tiziani) having a top level (See the surface shown in figure 1J of Tiziani comprising traces [100]) and a bottom level (See paragraph [0110] of Tiziani), the top level including a conductive U-shaped trace (See [182] in figure 2 of Tiziani), the bottom level including a conductive lead exposed along a side of the electronic device (See paragraph [0110] of Tiziani) and attached to the conductive trace (See paragraph [0112] of Tiziani); a semiconductor die attached to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) and having a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and a package structure that encloses a portion of the semiconductor die and a portion of the U-shaped trace (See the abstract of Tiziani).
With respect to claim 10, Tiziani discloses the system of claim 9, wherein the electronic device further comprises a surface mount component with terminals soldered to pads of the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 11, Tiziani discloses the system of claim 9, wherein the bottom level includes conductive split pads spaced apart from the conductive lead (See paragraph [0110] of Tiziani) and exposed along the side of the electronic device (See paragraph [0110] of Tiziani).
With respect to claim 14, Tiziani discloses a method of fabricating an electronic device (See figure 1J in view of paragraph [0005] of Tiziani), the method comprising: forming a conductive U-shaped trace (See [182] in figure 2 of Tiziani) in a top level of a multilevel package substrate (See the surface shown in figure 1J of Tiziani comprising traces [100]); forming a conductive lead in a bottom level of the multilevel package substrate (See paragraph [0110] of Tiziani); attaching a semiconductor die to the top level of the multilevel package substrate (See paragraph [0059] of Tiziani) with a Hall sensor positioned above the U-shaped trace (See paragraph [0030] of Tiziani); and molding a package structure that encloses the U-shaped trace (See the abstract of Tiziani).
With respect to claim 15, Tiziani discloses the method of claim 14, further comprising: forming pads in the top level of the multilevel package substrate (See paragraph [0079] in view of paragraph [0093] of Tiziani); and attaching a surface mount component to the top level of the multilevel package substrate with terminals soldered to the pads (See paragraph [0079] in view of paragraph [0093] of Tiziani).
With respect to claim 16, Tiziani discloses the method of claim 14, further comprising forming raised studs on the top level of the multilevel package substrate (See paragraph [0116] of Tiziani).
With respect to claim 17, Tiziani discloses the method of claim 14, comprising forming conductive split pads in the bottom level of the multilevel package substrate (See paragraph [0110] of Tiziani).
With respect to claim 19, Tiziani discloses the method of claim 14, further comprising forming a plated surface on the conductive lead (See paragraphs [0063] and [0079] of Tiziani).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 6-8, 12, 13, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tiziani as applied to claim 1 above, and further in view of Hoegerl et al. (US PUB 2021/0088600), hereinafter Hoegerl.
With respect to claim 4, Tiziani discloses the electronic device of claim 1, but fails to disclose wherein the conductive lead has an indent along the side of the electronic device. However, Hoegerl does disclose wherein the conductive lead has an indent along the side of the electronic device (See paragraph [0063] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tiziani to include the feature disclosed by Hoegerl because doing ensures that the Hall element and its related circuitry are mounted, aligned, and electrically connected to the package leads.
With respect to claim 6, Tiziani discloses the electronic device of claim 1, but fails to disclose wherein the package structure includes a magnetic material. However, Hoegerl does disclose wherein the package structure includes a magnetic material (See paragraph [0027] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tiziani to include the feature disclosed by Hoegerl because doing ensures enhanced magnetic field detection sensitivity.
With respect to claim 7, the combination of Tiziani and Hoegerl discloses the electronic device of claim 6, wherein the multilevel package substrate includes a magnetic material (See paragraph [0027] of Hoegerl).
With respect to claim 8, Tiziani discloses the electronic device of claim 1, but fails to disclose wherein the multilevel package substrate includes a magnetic material. However, Hoegerl does disclose wherein the multilevel package substrate includes a magnetic material (See paragraph [0027] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tiziani to include the feature disclosed by Hoegerl because doing ensures enhanced magnetic field detection sensitivity.
With respect to claim 12, Tiziani discloses the system of claim 9, but fails to disclose wherein the package structure includes a magnetic material. However, Hoegerl does disclose wherein the package structure includes a magnetic material (See paragraph [0027] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tiziani to include the feature disclosed by Hoegerl because doing ensures enhanced magnetic field detection sensitivity.
With respect to claim 13, Tiziani discloses the system of claim 9, but fails to disclose wherein the multilevel package substrate includes a magnetic material. However, Hoegerl does disclose wherein the multilevel package substrate includes a magnetic material (See paragraph [0027] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device disclosed by Tiziani to include the feature disclosed by Hoegerl because doing ensures enhanced magnetic field detection sensitivity.
With respect to claim 18, Tiziani discloses the method of claim 14, but fails to disclose further comprising forming an indent in the conductive lead along the side of the electronic device. However, Hoegerl does disclose further comprising forming an indent in the conductive lead along the side of the electronic device (See paragraph [0063] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method disclosed by Tiziani to include the method step disclosed by Hoegerl because doing ensures that the Hall element and its related circuitry are mounted, aligned, and electrically connected to the package leads.
With respect to claim 20, Tiziani discloses the method of claim 14, but fails to disclose comprising incorporating a magnetic material in the multilevel package substrate or the package structure. However, Hoegerl does disclose incorporating a magnetic material in the multilevel package substrate or the package structure (See paragraph [0027] of Hoegerl). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method disclosed by Tiziani to include the method step disclosed by Hoegerl because doing ensures enhanced magnetic field detection sensitivity.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PUB 2014/0333339 discloses a board, integrated circuit testing arrangement, and
method for operating an integrated circuit.
US PUB 2019/0250221 discloses an integrated current sensor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEMILADE S RHODES-VIVOUR whose telephone number is (571)270-5814. The examiner can normally be reached M-F (flex schedule).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TEMILADE S RHODES-VIVOUR/Examiner, Art Unit 2858
/HUY Q PHAN/Supervisory Patent Examiner, Art Unit 2858
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