DETAILED ACTION
This office action is in response to communication filed on 04/15/2026. Claims 1-5 and 7-16 have been amended. Claims 1-16 are pending on this application.
Response to Arguments
2. Applicant’s arguments with respect to claims 1, 15 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aruga et al. Pub. No. 2010/0001892.
Regarding claim 1. Fig. 4 of Sutardja discloses a semiconductor device comprising: a first analog to digital (AD) converter (MAIN DAC; CMP2, CNTL3) of a charge redistribution type (switching capacitors of MAINDAC) that includes a redundant comparison operation (redundant comparison CMP2 for selection impedance of SUBDAC for least signal bit of redundant of capacitor Cp0’) in a sequential comparison operation (sequential comparison of CMP2) and outputs a first output signal (DMAIN, DSUB) in digital form (digital form of DMAIN, DSUB) by converting a first input signal of an analog differential (Vinp, Vinn) using a reference voltage (Vref); a first variable impedance circuit (selection of SELN of Resistors network) that is provided on a signal line (VSUBN, VSUBP signal line) between a first pin (pin of Vref of resistor network) to which the reference voltage (Vref) is supplied from outside and the first AD converter (MAIN DAC; CMP2, CNTL3), the first variable impedance circuit (of SELN of Resistors network) is configured to change impedance (changing impedance by SELN) , and the first variable impedance circuit (SELN of Resistors network) is disconnected from the first input signal (Vin) of the first AD converter (MAINDAC; CMP2, CNTL3) and a first control circuit (CNTL3) that controls the impedance (DSUB) of the first variable impedance circuit ( SELN of Resistors network) according to operating condition of the first AD converter (MAINDAC; CMP2, CNTL3).
Regarding claim 2. The semiconductor device according to claim 1, Fig. 4 further discloses to wherein the first control circuit (CNTL3) controls (DSUB) the impedance of the first variable impedance circuit (SELN of Resistors network) to a first impedance (first SELN for RS31) when the first AD converter (MAIN DAC; CMP2, CNTL3) performs a comparison (CMP2) operation to determine value of upper bits (upper bits MAINDAC) in a first predetermined range of multiple bits (multiple bits DMAIN and multibit of SUBDAC) representing the first output signal (DMAIN, DSUB) , and wherein the first control circuit (CNTL3) controls the impedance of the first variable impedance circuit (SELN resistor network) to a second impedance lower (RS30) than the first impedance (RS31) when the first AD (MAIN DAC, CMP2, CNTL3) converter performs a comparison operation (CMP2) to determine the value of lower bits (lower bits of SUB-DAC) other than the upper bits upper bits (upper bits of MAINDAC) in the first predetermined range of the multiple bits (multiple bits MAINDAC and multiple bits of SUBDAC) representing the first output signal (DMAIN, DSUB) and performs a first redundant comparison operation (first redundant comparison of CMP2 for selection of VSUB of least signal bit Cp0’).
Regarding claim 3. The semiconductor device according to claim 2, Fig. 4 further discloses wherein the first AD converter (MAIN DAC, CPM2, CNTL3) is configured to perform the first redundant comparison operation (first redundant comparison of CMP2 for selection of VSUB of least signal bits of SUB-DAC) with a resolution (bits resolution of MAINDAC and bits resolution SUB-DAC) equal to or higher than that of the comparison operation to determine value of least significant bit (lower order bits DSUB) among the upper bits (DMAIN bits) in the first predetermined range (range of MAINDAC and range of SUB-DAC).
Regarding claim 4. The semiconductor device according to claim 1, Fig. 4 further discloses wherein the first AD converter (MAINDAC, CMP2, CNTL3) has a first DA converter (MAIN DAC) having multiple first capacitive elements (512C….1C) and multiple first switches (SM9…SM0) , a first comparator (CMP2) , and a first sequential comparison register circuit (CNTL3) , and wherein the first DA converter (MAIN DAC) is configured to perform a sequential comparison (sequence comparison of CMP2) of a potential of the first input signal (Vinp, Vinn) and an output of the first DA converter (DMAIN, DSUB), using the first comparator (CMP2) and the first sequential comparison register circuit (CNTL3) , while redistributing charge stored in the multiple first capacitive elements (redistribution of charge of 512C….1C) by switching connections (SM9…SM0) of the multiple first capacitive elements (512C….1C) with the multiple first switches (SM9…SM0), based on the potential of the first input signal (Vinn, Vinp) and the reference voltage (Vref).
Regarding claim 5. The semiconductor device according to claim 1, Fig. 4 further discloses wherein the first variable impedance circuit (SELN resistor network) is a first variable resistance circuit (variable selection of resistor network) configured to change resistance (change resistance by SELN or SELN).
4. Claims 15 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Olieman et al. U.S. patent No. 10,938,401.
Fig. 1 of Olieman et al. discloses an SAR ADC comprising: MSB Capacitive DAC 120-1 is configure to perform most significant bit (MSB) conversion of the digital code and Restive DAC (130-1…130-4) configured to perform least significant bit (LSB) conversion of the digital code (Col. 1 lines 48-53).
Fig. 2 discloses diagram of resistive DAC in Fig. 1.
Regarding claim 15. Fig. 1 and Fig. 2 of Olieman et al. discloses a control method (CNTL3) for a semiconductor device (100), comprising: controlling (Fig. 2) an impedance of a first variable impedance circuit (232-1…232-7 in Fig. 2) to a first impedance (first impedance of 232-1 in Fig. 2), wherein the first variable impedance circuit (232-1…232-7 in Fig. 2) is provided on a signal line (signal line of 232-1…232-7) between a first pin (pin of Vrefp in Fig. 2) supplied with a reference voltage (Vrefp in Fig. 2) from outside and a first AD converter (100 ); performing a comparison operation (104) to determine a value of upper bits (MSB of Capacitive DAC) within a first predetermined range of multiple bits (Col. 4 lines 10-18) representing a first output signal outputted (Digital Code) by the first AD converter (100) of a charge redistribution type (102-1) sequential comparison type (102) that includes a redundant comparison operation (redundant of least significant bits “LSB” of resistive DAC 130) in a sequential comparison operation (104), wherein: the first output signal (Digital Code) is outputted in digital form (Digital Code) by conversion of an analog differential (Vin+, Vin-) using a reference voltage (VrefP, VrefN) wherein the first variable impedance circuit (232-1…232-7 in Fig. 2) is disconnected (146-1..146-4) from first input signal (VIN) of the first AD converter (100); and controlling (Fig. 2) the impedance of the first variable impedance circuit (232-1…232-7 in Fig. 2) is based on an operating condition of the first AD converter (100); controlling an impedance (controlling of 232-1…232-7 in Fig. 2) of a first variable impedance circuit (232-1) to a second impedance (232-1) lower than the first impedance (232-1); performing another comparison operation (comparison operation for Resistive DAC) to determine the value of lower bits (LSB of Resistive DAC) other than the upper bits (Capacitive DAC 120-1) within the first predetermined range of the multiple bits (Col. 4 lines 10-18) representing the first output signal (Digital Code) ; and performing the redundant comparison operation (redundant of least significant bits “LSB” of resistive DAC 130).
Regarding claim 16. Fig. 1 and Fig. 2 of Olieman et al. discloses a control computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a device to cause the device to for executing control processing in a semiconductor device on a computer (Col. 11 lines 20-33), comprising: controlling (Fig. 2) an impedance of a first variable impedance circuit (232-1…232-7 in Fig. 2) to a first impedance (first impedance of 232-1 in Fig. 2), wherein the first variable impedance circuit (232-1…232-7 in Fig. 2) is provided on a signal line (signal line of 232-1…232-7) between a first pin (pin of Vrefp in Fig. 2) supplied with a reference voltage (Vrefp in Fig. 2) from outside and a first AD converter (100 ); performing a comparison operation (104) to determine a value of upper bits (MSB of Capacitive DAC) within a first predetermined range of multiple bits (Col. 4 lines 10-18) representing a first output signal outputted (Digital Code) by the first AD converter (100) of a charge redistribution type (102-1) sequential comparison type (102) that includes a redundant comparison operation (redundant of least significant bits “LSB” of resistive DAC 130) in a sequential comparison operation (104), wherein: the first output signal (Digital Code) is outputted in digital form (Digital Code) by conversion of an analog differential (Vin+, Vin-) using a reference voltage (VrefP, VrefN) wherein the first variable impedance circuit (232-1…232-7 in Fig. 2) is disconnected (146-1..146-4) from first input signal (VIN+) of the first AD converter (100); and controlling (Fig. 2) the impedance of the first variable impedance circuit (232-1…232-7 in Fig. 2) is based on an operating condition of the first AD converter (100); controlling an impedance (controlling of 232-1…232-7 in Fig. 2) of a first variable impedance circuit (232-1) to a second impedance (232-1) lower than the first impedance (232-1); performing another comparison operation (comparison operation for Resistive DAC) to determine the value of lower bits (LSB of Resistive DAC) other than the upper bits (Capacitive DAC 120-1) within the first predetermined range of the multiple bits (Col. 4 lines 10-18) representing the first output signal (Digital Code) ; and performing the redundant comparison operation (redundant of least significant bits “LSB” of resistive DAC 130).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et al. applied to claim 1 above in view of Mizuno et al. Pub. No. 2013/0214957.
Regarding claim 6. Aruga et al. applied to claim 1 above, Fig. 4 of Aruga et al. further discloses wherein the first AD converter (MAIN DAC, CMO2, CNTL3) is driven by a reference supply voltage (Vref), and wherein the first variable impedance circuit (selection of resistor network) is a first selection circuit (SELN, SELP) that selects either the first pin (first pin of resistor network) or a second pin (second pin or resistor network) to which the reference supply voltage (Vref) is supplied from outside according to the operating condition of the first AD converter (MAIN DAC, CMO2, CNTL3) and supplies the reference voltage (Vref) to the first AD converter (MAIN DAC, CMO2, CNTL3).
However, Aruga et al. disclose the reference supply voltage (Vref) is not a power supply voltage as claimed.
Fig. 2 of Mizuno et al. disclose and AD converter 201 is driven by a power supply voltage (VDD/GND) and a variable impedance circuit (VR2-VR4).
Aruga et al. and Mizuno et al. are common subject matter of variable impedance reference voltage for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate power supply voltage ADC of Mizunot et al. into Aruga et al. for the purpose of a reduction in power supply voltage, an enhancement of speed, and an improvement of power efficiency (paragraph 0003 of Mizuno et al.).
Regarding claim 7. Aruga et al. and Mizuno applied to claim 6 above, Fig. 2 of Muzino et al. further disclose wherein the first variable impedance circuit (VR2, VR3) is configured to be able to select any of the formation paths of multiple parasitic inductors (paths of parasitic inductors L2 and L3).
7. Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et al. applied to claim 1 above in view of by An et al. Pub. No. 2022/0077867.
Regarding claim 8. Fig. 4 of Aruga et al. applied to claim 1 discloses a first AD converter (Fig. 4) but does not disclose a second AD converter has the same operation as the first AD converter (Fig. 4).
Fig. 27 of An et al. disclose a first ADC1 and a second ADC2 and, the second ADC2 having same operation condition as of described in Fig. 2 of An et al. (paragraph 0143).
Aruga et al. and An et al. are common subject matter of SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to combine multiple SAR ADC taught by An et al. into Aruga et al. for the purpose of providing a system-on-chip included a plurality of SAR ADCs convert the analog signal provided by the receiver into a digital signal DS via continuous approximation (paragraphs 0140-0143 of An et al.).
Regarding claim 9. Aruga et al. combined with An et al. for first ADC1 and Second ADC2 applied to claim 8 above, Fig. 4 Aruga et al. further discloses wherein the first control circuit controls (CNTL3 for the first ADC as combined with An et al. applied to claim 8 above for ADC1) the impedance of the first variable impedance circuit (selection of SELN of Resistors network for ADC1) to a first impedance (RS31 for ADC1) when the first AD converter (MAIN DAC, CMP2, CNLT3 for ADC1) performs a comparison operation (CMP2 for ADC1) to determine a value of upper bits (upper bits of MAIN DAC for ADC1) within a first predetermined range of multiple bits (multiple bits MAINDAC and multiple bits of SUBDAC for ADC1) representing the first output signal (DMAIN, DSUB for ADC1) , wherein the first control circuit (CNTL3 for ADC1) controls the impedance (SELP, SELP for ADC1) of the first variable impedance circuit (impedance of Resistor network for ADC1) to a second impedance lower (RS0 of ADC1) than the first impedance (RS31 of ADC1) when the first AD converter (MAIN DAC, CMP2, CNTL3 for ADC1) performs a comparison operation (CMP2 for ADC1) to determine the value of lower bits (lower bits of SUB-DAC for ADC1) other than the upper bits (upper bits of MAIN DAC for ADC1) within the first predetermined range of the multiple bits (multiple bits MAINDAC and multiple bits of SUBDAC for ADC1) representing the first output signal (DMAIN, DSUB for ADC1), and a comparison operation (CMP2 for ADC1) with a first redundancy (comparison operation redundant of ADC1), wherein the second control circuit controls (CLNT3 for ADC2) the impedance of the second variable impedance circuit (selection of SELN of Resistors network) to a third impedance (RS31 for ADC2) when executing a comparison operation (CMP2 of ADC2) to determine the value of the upper bits (upper bits of MAIN DAC for ADC2) within a second predetermined range (multiple bits MAINDAC and multiple bits of SUBDAC for ADC2) of the multiple bits representing the second output signal (DMAIN DSUB for ADC2) by the second AD converter (ADC2), and wherein the second control circuit controls (CLNT3 for ADC2) the impedance of the second variable impedance circuit (selection of SEL of Resistors network for ADC2) to a fourth impedance (RS0 for ADC2) lower than the third impedance (RS31 for ADC2) when the second AD converter (ADC2) executes a comparison operation (CMP2 for ADC2) to determine the value of the lower bits (lower bits of SUB-DAC for ADC2) other than the upper bits (upper bits of MAIN DAC for ADC2) within the second predetermined range of the multiple bits (multiple bits MAINDAC and multiple bits of SUBDAC for ADC2) representing the second output signal DMAIN, DSUB for ADC2), and a comparison operation with a second redundancy (CMP2 operation with redundancy for ADC2).
Regarding claim 10. Aruga combined with An et al. applied to claim 9 above, Fig. 4 of Aruga further discloses wherein the first AD converter (MAIN DAC, CPM2, CNTL3 for ADC1) is configured to perform the first redundant comparison operation (first redundant comparison of CMP2 for selection of VSUB of least signal bits of SUB-DAC for ADC1) with a resolution (bits resolution of MAINDAC and bits resolution SUB-DAC) equal to or higher than that of the comparison operation to determine value of least significant bit (lower order bits DSUB) among the upper bits (DMAIN bits) in the first predetermined range (range of MAINDAC and range of SUB-DAC) and wherein the second AD converter (MAIN DAC, CPM2, CNTL3 for ADC2) is configured to execute the comparison operation with the second redundancy (redundant comparison of CMP2 for selection of VSUB of least signal bits of SUB-DAC for ADC2) at a resolution (bits resolution of MAINDAC and bits resolution SUB-DAC for ADC2) equal to or higher than the comparison operation to determine the value of the least significant bit (lower order bits DSUB) among the upper bits (DMAIN bits for ADC2) within the second predetermined range (range of MAINDAC and range of SUB-DAC for ADC2) .
Regarding claim 11. Aruga et al. combined with An et al. for first ADC1 and Second ADC2 applied to claim 8 above, Fig. 4 of Aruga et al. further discloses wherein the first AD converter (MAIN DAC, CPM2, CNTL3 for ADC1) has a first DA converter (MAIN DAC for ADC1) with multiple first capacitive elements (capacitors of MAIN DAC for first ADC1) and multiple first switches (switches of MAIN DAC for ADC1), a first comparator (CMP2 for ADC1) , and a first sequential comparison register circuit (CNTL3 for ADC1), wherein the first DA converter (MAIN DAC for ADC1) is configured to perform a sequential comparison (CMP3 operation for ADC1) of a potential of the first input signal (Vin for ADC1) and an output of the first DA converter (output of MAIN DAC for ADC1) , using the first comparator (CMP2 for ADC1) and the first sequential comparison register circuit (CNTL1 for ADC1), while redistributing charge stored in a plurality of first capacitive elements (redistribution charge stored in capacitors of MAIN DAC for ADC1) based on the potential of the first input signal (Vin for ADC1) and the reference voltage (Vref for ADC1) , by switching (switches of MAIN DAC for ADC1 ) connection of the plurality of first capacitive elements (capacitors of MAIN DAC for ADC1) with the of multiple first switches (switches of MAIN DAC for ADC1, wherein the second AD converter has a second DA converter with multiple second capacitive elements and multiple second switches, a second comparator, and a second sequential comparison register circuit, and wherein the second DA converter (MAIN DAC, CPM2, CNTL3 for ADC2) is configured to perform a sequential comparison (comparison of CMP2 for ADC2) of the potential of the second input signal (Vin for ADC2) and the output of the second DA converter (output of MAIN DAC for ADC2) , using the second comparator(CMP2 for ADC2) and the second sequential comparison register circuit (CNTL3 for ADC2) , while redistributing charge stored in a plurality of second capacitive elements (redistribution of charge stored in capacitors of MAIN DAC for ADC2) based on the potential of the second input signal (Vin for ADC2) and the reference voltage (Vref for ADC2), by switching the connection (switches connection of MAIN DAC for ADC2) of the plurality of second capacitive elements (capacitors of MAIN DAC for ADC2) with the multiple second switches (switches of MAIN DAC for ADC2).
Regarding claim 12. Aruga et al. combined with An et al. for first ADC1 and Second ADC2 applied to claim 8 above, Fig. 4 of Aruga et al. further disclose wherein the first variable impedance circuit is a first variable resistance circuit (selection of resistor network for ADC1) configured to change a resistance value (change resistance value by selection SEL for ADC1) , and wherein the second variable impedance circuit is a second variable resistance circuit (selection of resistor network for ADC2) configured to change the resistance value ((change resistance value by selection SEL for ADC2).
8. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et al. combined with An et al. applied to claim 8 above in further view of Mizuno et al. Pub. No. 2013/0214957.
Regarding claim 13. Aruga et al. combined with An et al. applied to claim 8 above, Fig. 4 of Aruga et al. further disclose wherein the first AD converter (MAIN DAC, CMP2, CNTL3 for ADC1) is driven by a reference supply voltage (Vref for ADC1) , wherein the first variable impedance circuit (selection of resistor network for ADC1) is a first selection circuit (SELN, SELNP) that selects either the first pin (first pin of resistor network for ADC1) or a second pin (second pin of resistor network for ADC1) from which the reference supply voltage (Vref of resistor network for ADC1) is supplied from outside according to the operating condition of the first AD converter (operating condition of MAIN DAC, CMP2, CNTL3 for ADC1)) and supplies it to the first AD converter (MAIN DAC, CMP2, CNTL3 for ADC1) as the reference voltage (Vref for ADC1), wherein the second AD converter (MAIN DAC, CMP2, CNTL3 for ADC2) is driven by the reference supply voltage (Vref for ADC2) , and wherein the second variable impedance circuit (selection of resistor network for ADC2) a second selection circuit (SELN, SELP for ADC2) that selects either the first pin (firs pin of resistor network for ADC2) or the second pin (second pin of resistor network for ADC2) from which the reference supply voltage (Vref for ADC2) is supplied from outside according to the operating condition of the second AD converter (operation condition of MAIN DAC, CMP2, CNTL3 for ADC2) and supplies it to the second AD converter (MAIN DAC, CMP2, CNTL3 for ADC1) as the reference voltage (Vref for ADC2).
However, Aruga et al. disclose the reference supply voltage (Vref) is not a power supply voltage as claimed.
Fig. 2 of Mizuno et al. disclose and AD converter 201 is driven by a power supply voltage (VDD/GND) and a variable impedance circuit (VR2-VR3).
Aruga et al./An et al. and Mizuno et al. are common subject matter of variable impedance reference voltage for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate power supply voltage ADC of Mizunot et al. into Aruga et al./An et al. for the purpose of a reduction in power supply voltage, an enhancement of speed, and an improvement of power efficiency (paragraph 0003 of Mizuno et al.).
Regarding claim 14. Aruga et al./An et al. and Mizuno applied to claim 13 above, Fig. 4 of Aruga et al. further disclose wherein the first variable impedance circuit (selection of Resistor network of ADC1 of Aruga et al.) is configured to be able to select any of the formation paths (selection SLEN or SELNP formation conductor paths of resistor network for ADC1) of multiple parasitic inductors (parasitic inductance is indeed inherent to all conductor paths in real electronic systems; it is an unavoidable electrical property of any physical conductor; also see Fig. 2 of Muzino et al.), and wherein the second variable impedance circuit (Selection of resistor network for ADC2) is configured to be able to select any of the formation paths (selection SLEN or SELNP formation conductor paths of resistor network for ADC1) of the multiple parasitic inductors (parasitic inductance is indeed inherent to all conductor paths in real electronic systems; it is an unavoidable electrical property of any physical conductor; also see Fig. Fig. 2 of Muzino et al.).
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
05/15/206
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
Prosecution Insights