Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 06/25/2024. Claims 1-16 are pending on this application.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. -The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 2 -4, 9, 11 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the value" and “the upper bits” in claim 1. There is insufficient antecedent basis for these limitation in the claim.
Claim 3 depended on claim 2; thus, claim 3 is included insufficient antecedent basis of claim 2.
Claim 4 recites the limitation "the potential" in claim 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the value" and “the upper bits” in claim 8. There is insufficient antecedent basis for these limitation in the claim.
Claim 11 recites the limitation "the potential" in claim 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the value”, “the upper bits” and “the multiple bits” in the claim. There is insufficient antecedent basis for these limitation in the claim.
Claim 16 recites the limitation "the value”, “the upper bits” and “the multiple bits” in the claim. There is insufficient antecedent basis for these limitation in the claim.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-5, 8-12, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. Pub. No. 2022/0077867.
Fig. 1 of An et al. discloses a semiconductor device 1 (paragraph 0014)
Fig. 2 of An et al. discloses a circuit diagram of SAR ADC of Fig. 1 (paragraph 0015)
Fig. 3 of An et al. discloses a circuit diagram of different voltage generator 130 in Fig. 3 comprising a variable impedance circuit (16R, 8R, 4R, R).
Fig. 27 of An et al. discloses plurality of SAR ADC1, SAR ADC2… SAR ADCm; each SAR ADC implemented as an SAR ADC in Fig 1 and Fig. 2 (paragraphs 0142- 0143).
Regarding claim 1. Figs. 1 and Fig. 2 of An et al. discloses a semiconductor device (1) comprising: a first AD converter (paragraph 0015) of a charge redistribution type (charge distribution of capacitors in Fig. 2) that includes a redundant comparison (redundance of capacitors Cu ) operation in a sequential comparison operation (sequential Comparison of 300 from most significant bit 128Cu to Least significant bit Cu) and outputs a first output signal in digital form (Dout) by converting a first input signal (VINP) of an analog differential (VINP, VINN; paragraph 0074) using a reference voltage (VREFP, VREFN); and a first variable impedance circuit (Differential Voltage Generator 130; See Fig. 3 for disclose variable impedance of of130 having variable impedance 16R, 8R, 4R, R to generates variable impedance voltage references VREFP, 1/2 VREFP..1/32 VREFN; VREFN, 1/2 VREFN..1/32 VREFN) that is provided on a signal line (signal line of VREP between a first pin (PIN of VREFP, VREFN) to which the reference voltage (VREFP, VREFN) is supplied from outside (see Fig. 3 for discloses VREFP and VREFN are supplied from output side circuit 200) and the first AD converter (Fig. 2), and is configured to be able to change impedance (change impedance 16R, 8R, 4R, R by controlling switches S1…S6), a first control circuit (600, 420, 520, 420) that controls (control switches S1, S2, S4, S6) the impedance of the first variable impedance circuit (130) according to the operating condition of the first AD converter (operation of SAR ADC Fig. 2) .
Regarding claim 2. The semiconductor device according to claim 1, Fig. 2 further discloses wherein the first control circuit (600, 420, 520, 420) controls (control switches S1, S2, S3, S4, S6) the impedance of the first variable impedance circuit (130) to a first impedance (16R for VREFP, VREFN) when the first AD converter (Fig. 2) performs a comparison operation (300) to determine the value of the upper bits (most significant bits MSB of 128Cu…8Cu) in a first predetermined range (range of most significant bits) of multiple bits (bits 128 Cu…Cu) representing the first output signal (Dout), and wherein the first control circuit (600, 420, 520, 420) controls (control switches ) the impedance of the first variable impedance circuit (130) to a second impedance lower (R for VREFP/32) than the first impedance (16R) when the first AD converter (Fig. 2) r performs a comparison operation (300) to determine the value of the lower bits (least significant bits LSB 4Cu, 2Cu, 1Cu) other than the upper bits (128Cu…8Cu) in the first predetermined range (range most significant bits 128Cu…8Cu) ) of the multiple bits (bits for 128Cu…Cu) representing the first output signal (Dout) and performs a first redundant comparison operation (redundant of capacitors Cu for comparison 300) .
Regarding claim 3. The semiconductor device according to claim 2, wherein the first AD converter (Fig. 2) is configured to perform the first redundant comparison operation (Redundancy of capacitors Cu for SAR ADC) with a resolution (number of most significant bits 128Cu…8Cu) equal to or higher than that of the comparison operation (300) to determine the value of the least significant bit (number of least signal bits LSB capacitors 4Cu 2Cu and Cu ) among the upper bits (most significant bits MSBs) in the first predetermined range (range of bits for 128Cu…8Cu).
Regarding claim 4. The semiconductor device according to claim 1, Fig. 2 further discloses wherein the first AD converter (Fig. 2) has a first DA converter (110; paragraph 0042) having multiple first capacitive elements (128Cu…8Cu) and multiple first switches (switches S1, S2, S3, S4, S6), a first comparator (300), and a first sequential comparison register circuit (SAR 510, 520), and wherein the first DA converter (110) is configured to perform a sequential comparison (300) of the potential of the first input signal (VINP) and the output of the first DA converter (110) , using the first comparator (300) and the first sequential comparison register circuit (SAR 510) , while redistributing the charge stored in the multiple first capacitive elements(185Cu…Cu) by switching the connections (switches S1, S2, S3, S4, S6) of the multiple first capacitive elements (128Cu…Cu) with the multiple first switches (switches S1, S2, S3, S4, S6), based on the potential of the first input signal (VINP) and the reference voltage (VREFP).
Regarding claim 5. The semiconductor device according to claim 1, Fig. 2 further discloses wherein the first variable impedance circuit (16R, 8R, 4R, R for VREFP, 1/2 VREFP…1/32 VREFN; VREFN, 1/2 VREFN…1/32 VREFN; See Fig. 3 for disclose variable impedance of of130) is a first variable resistance circuit (16R, 8R, 4R, R in Fig. 3) configured to be able to change resistance (16R, 8R, 4R, R).
Regarding claim 8. The semiconductor device according to claim 1, Fig. 27 of An et al. further comprising: a second AD converter (ADC2) of a charge redistribution type that includes a redundant comparison operation (paragraph 0142 discloses each ADC has redundant comparison of Fig. 1 and Fig. 2 applied to claim 1 above); in a sequential comparison operation (sequence comparison of Fig. 2) and outputs a second output signal in digital form (DS output of ADC2 in Fig. 27) ) by converting a second input signal of an analog differential (VINP, VINN in Fig. 1 and Fig.2) using the reference voltage (VREFP, VREFN in Fig. 1 and Fig. 2) ; a second variable impedance circuit (second 130 in Fig. 3 for ADC2 in Fig. 27) that is provided on a signal line between the first pin (PIN of VREFP, VREFN in Fig. 2) of to which the reference voltage (VREFP and VREFN in Fig. 3) is supplied from outside and the second AD converter (ADC2 in Fig. 27) and is configured to be able to change impedance (change impedance by control switches in Fig. 2); and a second control circuit (second control circuit of 600, 420, 520, 420 in Fig. 2 for ADC2 in Fig. 27) that controls the impedance of the second variable impedance circuit (second variable Impedance 130 in Fig. 2) according to the operating condition of the second AD converter (ADC2 in Fig. 27) .
Regarding claim 9. The semiconductor device according to claim 8, Fig. 2 and Fig. 27 further disclose wherein the first control circuit (control circuit of ADC1 in Fig. 27) controls the impedance of the first variable impedance circuit (first variable impedance 130 of ADC1) to a first impedance (first impedance of 130 for ADC1 in Fig. 27) when the first AD converter (ADC1 in Fig. 27) performs a comparison operation (300 in Fig. 2) to determine the value of the upper bits (MSB bits of 128Cu…8Cu in Fig. 2) ) within a first predetermined range of the multiple bits (range of bits for 128 Cu…8Cu in Fig. 2 for ADC 1 in Fig. 27) representing the first output signal (DS is Dout of ADC1 in Fig. 27) , wherein the first control circuit (600, 420, 520, 420 in Fig. 2 of ADC1 in Fig. 27) controls (control switches S1, S2, S3, S4, S6 in Fig. 2) the impedance of the first variable impedance circuit (R16 for VREFP of 130 in Fig. 2 for ADC1 in Fig. 27) to a second impedance lower (R for 1/2 VREFP, 1/2VREFN in Fig. 2 for ADC1 in Fig. 27) than the first impedance (16R for VREFP for ADC1) when the first AD converter (ADC1 in Fig. 27) performs a comparison operation (300 in Fig. 2) to determine the value of the lower bits (values of least signal bits 4Cu, 2Cu, 1Cu) other than the upper bits (most significant bits 128Cu…8Cu) within the first predetermined range of the multiple bits (range of bits for 128 Cu…8Cu) representing the first output signal (output signal of ADC1 in Fig. 2), and a comparison operation with a first redundancy (comparison of 300 for redundance ADC1) , wherein the second control circuit (600, 420, 520, 420 in Fig. 2 for ADC2 in Fig. 27) controls the impedance of the second variable impedance circuit (16R, 8R, 4R, R of 130 in Fig. 2 for ADC2) to a third impedance (VREFP impedance of 130 in Fig. 2) when executing a comparison operation (comparison of 300 in Fig. 2 for ADC2) to determine the value of the upper bits (most significant bits 128Cu …8Cu) within a second predetermined range of the multiple bits (range 128Cu…8Cu of Fig. 2 for ADC2 in Fig. 27) representing the second output signal by the second AD converter (DS output of ADC2 in Fig. 27), and wherein the second control circuit (600, 420, 520, 420 in Fig. 2 for ADC2 in Fig. 27) controls (control Switches S2...S6 in Fig. 2) the impedance of the second variable impedance circuit (16R, 8R, 4R, R of 130 in Fig. 2 for ADC2 in Fig. 27) to a fourth impedance lower (R for 1/2 VREFP, 1/2VREFN in Fig. 2 for ADC2 in Fig. 27) than the third impedance (VREFP in Fig. 2 for ADC2 in Fig. 27) when the second AD converter (ADC2 in Fig. 27) executes a comparison operation (300 in Fig. 2) to determine the value of the lower bits (Least significant bits 4Cu, 2Cu, Cu) other than the upper bits (most significant bits 128Cu…8Cu) within the second predetermined range of the multiple bits (range of 128Cu…8Cu for ADC2 in Fig. 27) representing the second output signal (DS of ADC2 in Fig. 27) , and a comparison operation with a second redundancy (redundant capacitors Cu for comparison of 300 in ADC2 in Fig. 27).
Regarding claim 10. The semiconductor device according to claim 9, Fig. 2 and Fig. 27 further discloses wherein the first AD converter (SAR ADC1 in Fig. 27) is configured to execute the comparison operation (comparison of 300 in Fig. 2) with the first redundancy (redundancy of SAR ADC Fig. 2) at a resolution (number of most significant bits for 128Cu…8Cu) equal to or higher than the comparison operation (comparison of 300) to determine the value of the least significant bit (least significant bits 4Cu…1Cu) among the upper bits (most significant bits for 128Cu…8Cu ) within the first predetermined range (range of 128Cu…8Cu for SAR ADC1 in Fig. 27) , and wherein the second AD converter (SAR ADC2 in Fig. 27) is configured to execute the comparison operation (comparison 300 for ADC2) with the second redundancy (redundancy of Fig. 2 for ADC2) at a resolution (number of most significant bits of 128Cu…8Cu) equal to or higher than the comparison operation (comparison 300 for ADC2) to determine the value of the least significant bit (Least Significant bits 4Cu, 2Cu and 1Cu) among the upper bits (most significant bits 128Cu…8Cu) within the second predetermined range (range of most significant bits of 128Cu…8Cu).
Regarding claim 11. The semiconductor device according to claim 8, Fig. 1 and Fig. 27 further discloses wherein the first AD converter (SAR ADC1 in Fig. 27) has a first DA converter (first 110; paragraph 0042) with multiple first capacitive elements (capacitors on Fig. 2) and multiple first switches (S1…S6 in Fig. 1), a first comparator (first comparator 300), and a first sequential comparison register circuit (first 510, 520 in Fig. 2) , wherein the first DA converter (first 110) is configured to perform a sequential comparison (300) of the potential of the first input signal (potential of first input VINP) and the output of the first DA converter (output of first 110), using the first comparator (first 300) and the first sequential comparison register circuit (first 510, 520) , while redistributing the charge stored in the plurality of first capacitive elements (charge stored of capacitors in Fig. 2) based on the potential of the first input signal (potential of VINP) and the reference voltage (VREF), by switching the connection (S1…S6) of the plurality of first capacitive elements (capacitors in Fig. 2) with the plurality of first switches (first S1…S6), wherein the second AD converter (SAR ADC2) has a second DA converter (second 110 for SAR ADC2) with multiple second capacitive elements (capacitive elements in Fig. 2 for second SAR ADC1) and multiple second switches (S1…S6 for second SAR ADC), a second comparator (300 in Fig. 2 for second SAR ADC2), and a second sequential comparison register circuit (second 510, 520 for SAR ADC2) , and wherein the second DA converter (110 for second SAR ADC2) is configured to perform a sequential comparison (comparator 300 in Fig. 2) of the potential of the second input signal (second VINP for second SAR ADC2) and the output of the second DA converter (output of second 110 for second SAR ADC2) , using the second comparator (second 300 for SAR ADC2) and the second sequential comparison register circuit (second 510, 520 for SAR ADC2), while redistributing the charge stored in the plurality of second capacitive elements (redistributing the charge stored capacitors in Fig. 2 for SAR ADC2) based on the potential of the second input signal (second potential of VINP for second SAR ADC2) and the reference voltage (VREF) , by switching the connection(S1…S6) of the plurality of second capacitive elements (capacitors elements in Fig. 2 for second SAR ADC2) with the plurality of second switches (second S1…S6 for second SAR ADC2).
Regarding claim 12. The semiconductor device according to claim 8, Fig. 2 and Fig. 27 further discloses wherein the first variable impedance circuit (first 130 for SAR ADC1) is a first variable resistance circuit (first 16R, 8R, 4R, R) configured to be able to change the resistance value (change resistance value by switches S1…S6), and wherein the second variable impedance circuit (second 130 for SAR ADC2) is a second variable resistance circuit (second 16R, 8R, 4R, R) configured to be able to change the resistance value (change resistance value by switches S1…S6).
Regarding claim 15. Fig. 1, Fig. 2 and Fig. 27 of An et al. disclose a control method for a semiconductor device (1 in Fig. 1), comprising: a first AD converter (SAR ADC1 in Fig. 27; see Fig. 2) of a charge redistribution (charge redistribution of capacitors in Fig. 2) type sequential comparison type (comparator 300 in Fig. 2) that includes a redundant comparison operation (redundancy is inherent and crucial in many high-performance Successive Approximation Register (SAR) ADC designs, not as a flaw, but as a powerful technique (using extra bits/steps) to correct comparator errors, relax DAC settling time, boost speed, improve accuracy like INL/DNL ) in a sequential comparison operation (sequence comparison of SAR ADC in Fig. 2) and outputs a first output signal in digital form (Dout) by converting a first input signal (VINP) of an analog differential (VINP, VINN; paragraph 0074) using a reference voltage (VREFP) ; a first variable impedance circuit (130) provided on a signal line (signal Line of VREFP) between a first pin (pin of VREFP) supplied with the reference voltage (VREFP) from the outside (see Fig. 1 VREFP and VREFN supply from outside circuit 200) and the first AD converter (Fig. 2) , and configured to change the impedance (change impedance of 16R, 8R, 4R, R in Fig. 3); and a first control circuit (600, 420, 520, 420) that controls (control S1...S6) the impedance of the first variable impedance circuit (16R, 8R, 4R, R of 130) according to the operating condition of the first AD converter (operation condition of Fig. 2), wherein the impedance (16R, 8R, 4R, R) of the first variable impedance circuit (130) is controlled (controlled by S1...S6) to a first impedance (16R), wherein the first AD converter (Fig. 2) performs a comparison operation (300) to determine the value of the upper bits (most significant bits 128Cu…8Cu) within a first predetermined range (range of most significant bits 128Cu…8Cu) of the multiple bits (bits 128Cu….Cu) representing the first output signal (Dout) , wherein the impedance (16R) of the first variable impedance circuit (16R, 8R, 4R, R of 130 ) is controlled to a second impedance (R) lower than the first impedance (16R), and wherein the first AD converter (Fig. 2) performs a comparison operation (300) to determine the value of the lower bits Least significant bits (4Cu, 2Cu, Cu) other than the upper bits (most significant bits 128Cu…8Cu) within the first predetermined range (range of most significant bits 128Cu…8Cu) of the multiple bits (bits 128Cu….Cu) representing the first output signal (Dout) , and performs a redundant comparison operation (redundancy of SAR ADC Fig. 2).
Regarding claim 16. Fig. 1, Fig. 2, and Fig. 27 of An et al. discloses a control program for executing control processing in a semiconductor device (1) on a computer (paragraph 0161); comprising: a first AD converter (SAR ADC1 in Fig. 27; see Fig. 2) of a charge redistribution (charge redistribution of capacitors in Fig. 2) type sequential comparison type (comparator 300 in Fig. 2) that includes a redundant comparison operation (redundancy is inherent and crucial in many high-performance Successive Approximation Register (SAR) ADC designs, not as a flaw, but as a powerful technique (using extra bits/steps) to correct comparator errors, relax DAC settling time, boost speed, improve accuracy like INL/DNL ) in a sequential comparison operation (sequence comparison of SAR ADC in Fig. 2) and outputs a first output signal in digital form (Dout) by converting a first input signal (VINP) of an analog differential (VINP, VINN; paragraph 0074) using a reference voltage (VREFP); a first variable impedance circuit (130) provided on a signal line (signal line of VREFP in Fig. 3) between a first pin (pin of VREFP) supplied with the reference voltage (VREFP) from the outside (see Fig. 1 VREFP and VREFN supply from outside circuit 200) and the first AD converter (Fig. 2) , and configured to change the impedance (change impedance of 16R, 8R, 4R, R in Fig. 3); and a first control circuit (600, 420, 520, 420) that controls (control S1...S6) the impedance of the first variable impedance circuit (16R, 8R, 4R, R of 130) according to the operating condition of the first AD converter (operation condition of Fig. 2), wherein a process (510, 410, 420, 520) of controlling (S1…S6) the impedance (16R, 8R, 4R, R) of the first variable impedance circuit (130) to a first impedance (16R of VREFP) , wherein a process (300) of performing a comparison operation (300) in the first AD converter (SAR ADC of Fig. 2) to determine the value of the upper bits (most significant bits 128Cu…8Cu) in a first predetermined range (range of 128Cu…8Cu) among the multiple bits (bits of 128Cu….Cu) representing the first output signal (Dout) , wherein a process (controlling switches S1…S6 process) of controlling the impedance (16R, 8R, 4R, R) of the first variable impedance circuit (130) to a second impedance (R for VREFP/32) lower than the first impedance (16R for VREFP), and wherein a process of performing a comparison operation (process of comparator 300) in the first AD converter (SAR ADC of Fig. 2) to determine the value of the lower bits (least significant bits 4Cu…Cu) other than the upper bits ( most signal bits 128Cu….8Cu) in the first predetermined range (range of 128Cu….8Cu) among the multiple bits (bits of 128Cu….Cu) representing the first output signal (Dout) , and a redundant comparison operation (redundant comparison operation of SAR ADC Fig. 2).
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 6- 7 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over An et al. applied to claim 1 above in view of Mizuno et al. Pub. No. 2013/0214957.
Regarding claim 6. An et al. applied to claim 1 above, Fig. 2 of An et al. further discloses wherein the first AD converter (SAR ADC Fig. 2) is driven by a reference supply voltage (VREFN), and wherein the first variable impedance circuit (130) is a first selection circuit (Selection of VREFP, 1/2 VREFP..1/32 VREFN; VREFN, 1/2 VREFN..1/32 VREFN) that selects either the first pin (Pin of VREFP) or a second pin (pin of VREFN) to which the reference supply voltage (VREFN) is supplied from outside (see Fig. 1 for disclose voltage supply VREFN is from outside 200 ) according to the operating condition of the first AD converter (SAR ADC Fig. 2) and supplies the reference voltage (VREFP) to the first AD converter (SAR ADC Fig. 2).
However, An et al. disclose the reference supply voltage (VREFN) is not a power supply voltage as claimed.
Fig. 2 of Mizuno et al. disclose and AD converter 201 is driven by a power supply voltage (VDD/GND) and a variable impedance circuit (VR2-VR3).
An et al. and Mizuno et al. are common subject matter of variable impedance reference voltage for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate power supply voltage ADC of Mizunot et al. into Aa et al. for the purpose of a reduction in power supply voltage, an enhancement of speed, and an improvement of power efficiency (paragraph 0003 of Mizuno et al.).
Regarding claim 7. An et al. and Mizuno applied to claim 6 above, Fig. 2 of Muzino et al. further disclose wherein the first variable impedance circuit (VR2, VR3) is configured to be able to select any of the formation paths of multiple parasitic inductors (paths of parasitic inductors L2 and L3).
Regarding claim 13. An et al. applied to claim 8 above, Fig. 2 and Fig. 7 of An et al. further disclose a wherein the first AD converter (SAR ADC1) is driven by a reference supply voltage (VREFN) , wherein the first variable impedance circuit (fist 130 for SAR ADC1) is a first selection circuit (first S1…S6) that selects either the first pin or the second pin (pins of VREFP, VREFN, VCOM, 1/2 VREFP, 1/2 VREFN, ..1/32 VREFP, 1/32 VREFN) from which the reference supply voltage (VREFN) is supplied from the outside (see Fig. 1 discloses VREFN is supply outside from reference voltage generator circuit 200) according to the operating condition of the first AD converter (operation condition of SAR ADC1 to control the switches S1…S6) and supplies it to the first AD converter (SAR ADC 1) as the reference voltage (VREFN), wherein the second AD converter (SAR ADC2) is driven by the reference supply voltage (VREFN), and wherein the second variable impedance circuit (second 130 for SAR ADC2) is a second selection circuit (Second S1…S6 for SAR ADC2) that selects either the first pin (pin of VREFP) or the second pin (pin of VREFN) from which the reference supply voltage (VREFN) is supplied from the outside (see Fig. 1 discloses VREFN is supply outside from reference voltage generator circuit 200) according to the operating condition of the second AD converter ((operation condition of SAR ADC2 to control the second switches S1…S6) and supplies it to the second AD converter (SAR ADC2) as the reference voltage (VREFN).
However, An et al. discloses the reference supply voltage (VREFN) is not a power supply voltage as claimed.
Fig. 2 of Mizuno et al. disclose and AD converter 201 is driven by a power supply voltage (VDD/GND) and a variable impedance circuit (VR2-VR3).
An et al. and Mizuno et al. are common subject matter of variable impedance reference voltage for ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate power supply voltage ADC of Mizunot et al. into Aa et al. for the purpose of a reduction in power supply voltage, an enhancement of speed, and an improvement of power efficiency (paragraph 0003 of Mizuno et al.).
Regarding claim 14. An et al. and Mizuno et al. applied to claim 13, Fig. 2 of Muzino et al wherein the first variable impedance circuit (VR2 and VR3) is configured to be able to select any of the formation paths of multiple parasitic inductors (information paths of parasitic inductors L2 and L3), and wherein the second variable impedance circuit (second VR2 and VR3 for SAR ADC2) is configured to be able to select any of the formation paths of the multiple parasitic inductors (information paths of parasitic inductors L2 and L3).
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
12/17/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845