DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-15 are pending and have been examined.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
The following is a quotation of 35 U.S.C. 102(a)(2) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claim 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yilmaz et al. (US 20110177662 A1 – hereinafter Yilmaz).
Regarding independent claim 1, Yilmaz teaches:
A semiconductor apparatus ([0003] – “present invention relates to
semiconductor power devices,” – hereinafter “SA’) comprising:
a drift region (604 – Fig. 6 – [0047] – “drift region 604;
a body region (606 – Fig. 6 – [0043] – “body regions 406” – his equates to
region 406 of Fig. 4) formed on the drift region (604 – Fig. 6 shows this);
a body contact region (608 – Fig. 6 – [0050] – “body regions 808” – this
equates to region 808 of Fig. 8) formed on the body region (606 – Fig. 6 shows this);
a gate trench (605 – Fig. 6 – [0043] – “trench 605”) formed to penetrate both the body region (606) and the body contact region (608) and reach the drift
region (604), the gate trench (605) including a side wall (Fig. 6 annotated, see below – [0004] – “the trench sidewalls and bottom” – hereinafter ‘605A’) and a bottom wall (Fig. 6 annotated, see below – [0004] – “the trench sidewalls and bottom” – hereinafter ‘605B’);
an insulating layer (622 – Fig. 6 – [0005] – “trench 205 includes a shield electrode 220 insulated from the drift region 204 by a shield dielectric layer 222” – this equates to 222 of Fig. 2) formed in the gate trench (605);
a gate electrode (614 – Fig. 6 – [0047] – “gate electrode 614”) arranged in the gate trench (605) and separated from the side wall (605A) by the insulating layer (622);
a source region (610 – Fig. 6 – [0047] – “source regions 610 flanking the gate trench 605”) formed along part of the side wall (605A – Fig. 6 annotated shows this), the source region (610) being in contact with both the body region (606) and the body contact region (608); and
source wiring (1330 – Fig. 13L – [0041] – “source interconnect layer 1330” – although not shown in the embodiment of Fig. 6, this is in the apparatus – [0047] – “In one embodiment, MOSFET 600 is formed by integrating the process module depicted by the cross-section views in FIGS. 12A-12D with the process flow of FIGS. 13A-13L as follows”) arranged across both the gate trench (605) and the body region (606) as viewed in a depth direction ([0009] – “upper trench portion extending to a first depth” – hereinafter ‘Z’) of the gate trench (605), wherein
the source region (610) includes a source contact region (Fig. 6 annotated, see below – hereinafter ‘SCR’, the wiring has been added) that is in contact with the source wiring (1330), and
the source wiring (1330) is in contact with both a side surface of the source contact region (1322b – Fig. 13L – [0041] – “source regions 1322b”) and a front surface of the body contact region (1329 – Fig. 13L – [0041] – “body regions 1329”).
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Regarding claim 15, Yilmaz teaches claim 1 from which claim 15 depends. Yilmaz further teaches
further comprising:
an implanted electrode (620 – Fig. 6 – [0043] – “shield electrode 420” – this
equates to element 620 of Fig. 6) arranged closer to the bottom wall (Fig. 6 annotated, see above – hereinafter 605B) in the gate trench (605) than the gate electrode (614) is, the implanted electrode (620) being separated from the gate electrode (614), the side wall (605A), and the bottom wall (605B) by the insulating layer (628 – Fig. 6 – [0047] – “thin dielectric layer 628 is formed over the gate electrode 614”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz in view of Losse et al. (US 20170243970 A1 – hereinafter Losee).
Regarding claim 2, Yilmaz, as modified by Losee, teaches claim 1 from which claim 2 depends. Yilmaz does not expressly disclose the limitations of claim 2.
However, in an analogous art, Losee teaches
wherein
the entire front surface of the body contact region (22 – Fig. 3 – [0027] –
“Source/body contact 22”) is formed as a flat surface without a hole (Fig 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the body contact region structure as taught by Losee into Yilmaz.
An ordinary artisan would have been motivated to use the known technique of Losee in the manner set forth above to produce the predictable results [0027] – “During operation, an appropriate gate voltage (e.g., at or beyond a threshold voltage (V.sub.TH) of the MOSFET device 10) may cause an inversion layer to be formed in the channel region 28, as well as a conductive path to be enhanced in the junction field-effect transistor (JFET) region 29 due to accumulation of carriers, allowing current to flow between the contact 22 (i.e., the source electrode) and the drain contact 12.”
Regarding claim 3, Yilmaz, as modified by Losee, teaches claim 1 from which claim 3 depends. Yilmaz does not expressly disclose the limitations of claim 3.
However, in an analogous art, Losee teaches
wherein
the source region (42 – Fig. 3 – [0028] – “source contact region 42”) is formed
to overlap the body contact region (22) as viewed in the depth direction ([0027] – “Source/body contact 22 is disposed on top of the semiconductor layer 2, partially covering source region 20 and well/body regions 18.” – this describes a depth direction, hereinafter ‘Z’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source region structure as taught by Losee into Yilmaz.
An ordinary artisan would have been motivated to use the known technique of Losee in the manner set forth above to produce the predictable results as stated above in claim 2.
Claims 4-6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over
Yilmaz in view of Losse and Yoshimura et al. (US 20180269287 A1 – hereinafter Yoshimura-287).
Regarding claim 4, Yilmaz, as modified by Losee, teaches claim 3 from which claim 4 depends. Yilmaz does not expressly disclose the limitations of claim 4.
However, in an analogous art, Yoshimura-287 teaches
wherein
the gate electrode (106 – Fig. 3 – [0034] – “gate electrode 106”) is arranged
closer to the bottom wall ([0008] – “a gate insulating film covering a bottom surface and a side surface of an inside of the trench” – hereinafter ‘104B’) of the gate trench (104 – Fig. 4 – [0032] – “trench 104”) in the depth direction (trench 104 has a bottom which displays the depth direction – hereinafter ‘Z’) than the body contact region (109 – Fig. 4 – [0027] – “contact region 109”) is, and
the source region (108 – Fig. 4 – [0037] – “source region 108”) is formed between the body contact region (109) and the gate electrode (106) in the depth direction (Z – Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate electrode structure as taught by Yoshimura-287 into Yilmaz and Losee.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results [0010] – “the side surface of the trench positioned adjacent to the base contact region, a source region is arranged at a position deeper than the base contact region, to thereby form the channel. There is therefore no need to arrange the source region and the base contact region side by side in the surface of the semiconductor substrate in the lateral direction, and hence it is possible to downsize the device in the lateral direction. Further, the area of the source region necessary for channel formation is not sacrificially reduced in order to form the base contact region, and hence it is possible to suppress the reduction in channel formation density in the trench extending direction.”
Regarding claim 5, Yilmaz, as modified by Losee and Yoshimura-287, teaches claim 4 from which claim 5 depends. Yilmaz and Losee do not expressly disclose the limitations of claim 5.
However, in an analogous art, Yoshimura-287 teaches
wherein
one of two edges of the source region (106) closer to the bottom wall
(104B) of the gate trench (104) is positioned at a same position ([0039] – “source region 108 has a portion (one side surface) from the first height H1 to the second height H2 along the outer side surface of the trench 104”) as a front surface (H1 – Fig. 4 – this corresponds to the front surface of the gate electrode) of the gate electrode (106) in the depth direction (Z) or positioned closer to the bottom wall (104B) than the front surface (H1) of the gate electrode (106) is in the depth direction (Z).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source region structure as taught by Yoshimura-287 into Yilmaz and Losee.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results as stated above in claim 4.
Regarding claim 6, Yilmaz, as modified by Losee, and Yoshimura-287, teaches claim 4 from which claim 6 depends. Yilmaz and Losee do not expressly disclose the limitations of claim 6.
However, in an analogous art, Yoshimura-287 teaches
wherein
the source contact region (H2 – Fig. 4, this corresponds to the source contact
region) is formed at a position of the source region (108) adjacent to the body contact region (109) in the depth direction (Z).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source contact region structure as taught by Yoshimura-287 into Yilmaz and Losee.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results as stated above in claim 4.
Regarding claim 14, Yilmaz, as modified by Losee, and Yoshimura-287, teaches claim 4 from which claim 14 depends. Yilmaz further teaches
wherein
the gate electrode (614) is arranged closer to the body region (606) than the
drift region (604 – Fig. 6 shows this).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over
Yilmaz in view of Yoshimura-287.
Regarding claim 7, Yilmaz teaches claim 1 from which claim 7 depends. Yilmaz does not expressly disclose the limitations of claim 7.
However, in an analogous art, Yoshimura-287 teaches
wherein
an impurity concentration of the source region (208 – Fig. 11 – [0073] –
“source region 207”) is higher ([0073] – “The impurity concentrations of the first source region 207 and the second source region 208 are set to an impurity concentration higher than that of the base contact region 209 by about one order of magnitude”) than an impurity concentration of the body region (209 – Fig. 11 – [0073] – “the base contact region 209 by about one order of magnitude”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the impurity structure as taught by Yoshimura-287 into Yilmaz.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results as stated above in claim 4.
Regarding claim 8, Yilmaz teaches claim 1 from which claim 8 depends. Yilmaz does not expressly disclose the limitations of claim 8.
However, in an analogous art, Yoshimura-287 teaches
wherein
a width dimension (Fig. 3 annotated, see below – hereinafter ‘W1’) of the source region
(108) in a width direction (Fig. 3 annotated, see below – hereinafter ‘X’) of the gate trench is smaller than a depth dimension of the source region (108) in the depth direction (Fig. 3 annotated, see below – hereinafter ‘Z’ shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source region structure as taught by Yoshimura-287 into Yilmaz.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results as stated above in claim 4.
Regarding claim 9, Yilmaz, as modified by Yoshimura-287, teaches claim 8 from which claim 9 depends. Yilmaz does not expressly disclose the limitations of claim 9.
However, in an analogous art, Yoshimura-287 teaches
wherein
the width dimension (W1) of the source region (108) in the width direction (X) is smaller than a width dimension (Fig. 3 annotated, see above – hereinafter ‘W2’) of the body contact region (109) in the width direction (X – Fig. 3 annotated shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the impurity structure as taught by Yoshimura-287 into Yilmaz.
An ordinary artisan would have been motivated to use the known technique of Yoshimura-287 in the manner set forth above to produce the predictable results as stated above in claim 4.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over
Yilmaz in view of Losse, and Yoshimura-287, and Hsieh (US 20110068389 A1).
Regarding claim 10, Yilmaz, as modified by Losee, and Yoshimura-287, teaches claim 4 from which claim 10 depends. Yilmaz further teaches
wherein
the insulating layer (622) includes
a first insulating layer (612 – Fig. 6 – this corresponds to the first insulating layer) that covers a side surface (605A) of the gate electrode (614)
and a region between the gate electrode (614) and the bottom wall (605B), and
a second insulating layer (628 – Fig. 6 – [0047] – “thin dielectric layer 628 is formed over the gate electrode 614”) formed on the gate electrode (614),
a front surface (Fig. 6 annotated, see below – hereinafter ‘628A’) of the second insulating layer (628) is arranged closer to the gate electrode (614) than the front surface of the body contact region (628) is, and
the source wiring is fitted between the front surface of the body contact region and the front surface of the second insulating layer in the gate trench, and the source wiring includes a contact plug that is in contact with the source contact region.
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Yilmaz, Losee, and Yoshimura-287 do not expressly disclose the other limitations of claim 10.
However, in an analogous art, Hsieh teaches
the source wiring (220 – Fig. 2 – [0028] – “front metal layer 220 is formed covering the front surface of each mesa to contact said P++ heavily-doped contact region 208, while extending into the upper portion of each gate trench to contact N+ source regions 212”) is fitted between the front surface (Fig. 2 annotated, see below – hereinafter ‘208A’) of the body contact region (208 – Fig. 2 – [0028] – “heavily-doped contact region 208 on top surface of each mesa”) and the front surface (Fig. 2 annotated, see below – hereinafter ‘206A’) of the second insulating layer (206 – Fig. 2 – [0022] – “an insulation layer, for example, PSG layer 206”) in the gate trench (204 – Fig. 2 – [0022] – “gate trenches 204”), and the source wiring (220) includes a contact plug (Fig. 2 annotated, see below – hereinafter ‘220PG’) that is in contact with the source contact region (212 – Fig. 2 – [0022] – “source regions 212”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source wiring structure as taught by Hsieh into Yilmaz, Losee, and Yoshimura-287.
An ordinary artisan would have been motivated to use the known technique of Hsieh in the manner set forth above to produce the predictable results [0004] – “to provide new and improved device configuration to enhance the avalanche capability of semiconductor devices while shrinking the device.”
Regarding claim 11, Yilmaz, as modified by Losee, Yoshimura-287, and Hsieh, teaches claim 10 from which claim 11 depends. Yilmaz, Losee, and Yoshimura-287 do not expressly disclose the limitations of claim 10.
However, in an analogous art, Hsieh teaches
wherein
a thickness dimension (Fig. 2 annotated, see above – hereinafter ‘TC’) of the
contact plug (220PG) in the depth direction (Fig. 2 annotated, see above – hereinafter ‘Z’) is larger than a depth dimension (Fig. 2 annotated, see above – hereinafter ‘H2’) of the body contact region (208) in the depth direction (Fig. 2 annotated, see above, shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the source wiring structure as taught by Hsieh into Yilmaz, Losee, and Yoshimura-287.
An ordinary artisan would have been motivated to use the known technique of Hsieh in the manner set forth above to produce the predictable results as stated above in claim 10.
Regarding claim 12, Yilmaz, as modified by Losee, Yoshimura-287, and Hsieh, teaches claim 10 from which claim 12 depends. Yilmaz further teaches
wherein
a thickness dimension (Fig. 6-1 annotated, see below – hereinafter ‘TC’) of the
contact plug (630 – Fig. 6 – [0047] – “source plug 630”) in the depth direction (Fig. 6-1 annotated, see below – hereinafter ‘Z’) is smaller than the depth dimension (Fig. 6-1 annotated, see below – hereinafter ‘H3’) of the source region (610) in the depth direction (Z – Fig. 6-1 annotated shows this).
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Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over
Yilmaz in view of Losse, and Yoshimura-287, Hsieh, and Peake (US 11222974 B2).
Regarding claim 13, Yilmaz, as modified by Losee, Yoshimura-287, and Hsieh, teaches claim 10 from which claim 13 depends. Yilmaz, Losee, Yoshimura-287, and Hsieh, do not expressly disclose the limitations of claim 13.
However, in an analogous art, Peake teaches
wherein
a thickness dimension (Fig. 3 annotated, see below – hereinafter ‘TC’) of the
contact plug (316 – Fig. 3 – [7:48-52] – “The source metallisation 316 is thus arranged on the top surface of the gate dielectric 308 and is electrically connected the source region 313 and the body region 311 such that the source region 313 is aligned with the gate electrode 306”) in the depth direction (Fig. 3 annotated, see below – hereinafter ‘Z’) is equal to or smaller than 1/2 of a distance (Fig. 3 annotated, see below – hereinafter ‘DA’) between the front surface (Fig. 3 annotated, see below – hereinafter ‘311A’) of the body contact region (311 – Fig. 3 – [7:48-52] – “The source metallisation 316 is thus arranged on the top surface of the gate dielectric 308 and is electrically connected the source region 313 and the body region 311 such that the source region 313 is aligned with the gate electrode 306”) and the gate electrode (306 – Fig. 3 – [7:48-52] – “The source metallisation 316 is thus arranged on the top surface of the gate dielectric 308 and is electrically connected the source region 313 and the body region 311 such that the source region 313 is aligned with the gate electrode 306”) in the depth direction (Z – Fig. 3 annotated shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the contact plug structure as taught by Peake into Yilmaz, Losee, Yoshimura-287, and Hsieh.
An ordinary artisan would have been motivated to use the known technique of Peake in the manner set forth above to produce the predictable results of [2:27-28] – “improving the density of channels per unit area of a trench gate semiconductor device.”
Pertinent Art
For the benefits of the Applicant, US 20210367071 A1 and US 20180286970 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including the body contact region.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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