DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/25/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 recites the limitation "the 1st fin structure" in line 4 page 6. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the 1st fin structure as the 1st gate structure for further examination.
Claim 19-20 depend on the independent claim 18 so they are rejected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 12 and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHEN et al. (US Patent Appl. Pub. No. 2024/0178128 A1).
[Re claim 1] CHEN discloses the semiconductor device comprising: a 1st transistor (184-2) comprising a 1st channel structure (106a-c) and a 1st gate structure (165) on the 1st channel structure; a 2nd transistor (184-1) comprising a 2nd channel structure (106a-c) and a 2nd gate structure (163) on the 2nd channel structure; a 3rd transistor (186-1) comprising a 3rd channel structure (106a-c) and a 3rd gate structure (165) on the 3rd channel structure; an isolation wall (119-2) between the 1st channel structure and the 2nd channel structure; a gate cut structure (149) between the 1st gate structure and the 3rd gate structure; and a 1st active isolation (117 and 118) structure between the 1st channel structure and the 3rd channel structure, below a level of a bottom surface of the 1st channel structure or the 3rd channel structure, wherein the gate cut structure penetrates the 1st active isolation structure through a bottom surface of the 1st active isolation structure (see figure 15A-20A and paragraph [0056]-[0070]).
[Re claim 2] CHEN discloses the semiconductor device wherein the 1st transistor and the 2nd transistor further comprise a 1st source/drain pattern (160) and a 2nd source/drain pattern (160), respectively, and wherein the isolation wall extends to be between the 1st source/drain pattern and the 2nd source/drain pattern, and between the 1st gate structure and the 2nd gate structure (see figure 20B-C and paragraph [0052]).
[Re claim 3] CHEN discloses the semiconductor device wherein each of the 1st channel structure and the 2nd channel structure comprises a plurality of channel layers (106a-c) arranged one above another (see paragraph [0028]-[0029]).
[Re claim 6] CHEN discloses the semiconductor device wherein bottom surfaces of the isolation wall (119-2) and the gate cut structure (149) are at a same level below a level of a bottom surface of the 1st active isolation structure (117 and 118) (see figure 20A).
[Re claim 12] CHEN discloses the semiconductor device wherein the 1st active isolation structure (117 and 118) is formed in a substrate (101) between an upper portion of the substrate below the 1st channel structure (106a-c) and an upper portion of the substrate below the 3rd channel structure (106a-c) (see figure 20A).
[Re claim 18] CHEN discloses the semiconductor device comprising: a 1st transistor structure (184-2) comprising a 1st channel structure (106a-c) and a 1st gate structure (165) on the 1st channel structure; a 2nd transistor structure (186-1) comprising a 2nd channel structure (106a-c) and a 2nd gate structure (165) on the 2nd channel structure, and disposed at a side of the 1st transistor structure; a 1st isolation structure (149) between the 1st gate structure and the 2nd gate structure; and a 1st active isolation structure (117and 118) between the 1st channel structure and the 2nd channel structure, below a bottom surface of the 1st channel structure or the 2nd channel structure, wherein the 1st isolation structure (149) penetrates the 1st active isolation structure (117 and 118) through a bottom surface of the 1st active isolation structure (see figure 15A-20A and paragraph [0056]-[0070]).
Allowable Subject Matter
Claims 4-5 and 7-11are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-17 are allowed.
The following is an examiner's statement of reasons for allowance: Claim 13 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the 2nd active isolation structure is at a side of the 1st channel structure, opposite to the 1st active isolation structure, below a level of the bottom surface of the 1st channel structure. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 14-17 depend from claim 13 so they are allowable for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KYOUNG LEE/ Primary Examiner, Art Unit 2817
Prosecution Insights