Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-3, 5-10, 12-16, 18-20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIU et al (Pub. No.: US 2013/0238835).
3. Regarding independent claim 1, LIU et al teaches a method comprising: retrieving a defectivity footprint (Fig. 3, S33-S34) of a portion of memory (Fig. 2); determining (Fig. 3, S34-S35), based on the defectivity footprint (Fig. 3, S33-S34), a programming order (Fig. 3, S35) for the portion of memory (Fig. 2), wherein the programming order (Fig. 3, S35) is an order from a highest defect severity (Fig. 3, S35) to a lowest defect severity (Fig. 3, S35); and programming (Fig. 3, S36) the portion of memory (Fig. 2) according to the determined programming order (Fig. 3, S35).
4. Regarding claim 2, 9, LIU et al teaches the defectivity footprint (Fig. 3, S33-S34) comprises locations (Fig. 2, #31-#33) of one or more defects and the defect severity (Fig. 3, S35) for each of the one or more defects (Fig. 3, S33-S34).
5. Regarding claim 3, 10, 16, LIU et al teaches the portion of memory (Fig. 2) is composed of a plurality of blocks (Fig. 2, #31-#33), each block (Fig. 2, #31) is composed of a plurality of decks (Fig. 2, 1st-18th), and the programming order (Fig. 3, S35) comprises an order (Fig. 3, S34) in which the plurality of decks (Fig. 2, 1st-18th) is programmed (Fig. 3, S36).
6. Regarding claim 5, 12, 18, LIU et al teaches the plurality of decks (Fig. 2, #31-#33) includes two decks (Fig. 2, #31-#33), each deck comprising half of a block (Fig. 2, 1st, 2nd).
7. Regarding claim 6, 13, 19, LIU et al teaches updating the defectivity footprint (Fig. 3, S33-S34) based on program logs (Fig. 3, S34) indicating areas of the portion of memory (Fig. 2) determined to be defective during operation (Fig. 3, S36) of the portion of memory (Fig. 2).
8. Regarding claim 7, 14, 20, LIU et al teaches the program logs (Fig. 2, S34) comprise logs of locations of uncorrectable errors (Fig. 2, S34) in the portion of memory (Fig. 2).
9. Regarding independent claim 8, LIU teaches a non-transitory computer-readable storage medium (Fig. 2) comprising instructions that, when executed by a processing device (Fig. 1, #300), cause the processing device (Fig .1, #10) to: retrieve a defectivity footprint (Fig. 3, S33-S34) of a portion of memory (Fig. 2); determine (Fig. 3, S34-S35), based on the defectivity footprint (Fig. 3, S33-S34), a programming order (Fig. 3, S35) for the portion of memory (Fig. 2), wherein the programming order (Fig. 3, S35) is an order from a highest defect severity (Fig. 3, S35) to a lowest defect severity (Fig. 3, S35); and program (Fig. 3, S36) the portion of memory (Fig. 2) according to the determined programming order (Fig. 3, S35).
10. Regarding independent claim 15, LIU teaches a system (Fig. 1) comprising: a plurality of memory devices (Fig. 2); and a processing device (Fig. 1, #10), operatively coupled with the plurality of memory devices (Fig. 1, #300), to: retrieve a defectivity footprint (Fig. 3, S33-S34) of a portion of memory (Fig. 2); determine (Fig. 3, S34-S35), based on the defectivity footprint (Fig. 3, S33-S34), a programming order (Fig. 3, S35) for the portion of memory (Fig. 2), wherein the defectivity footprint (Fig. 3, S33-S34) comprises locations of one or more defects and a defect severity (Fig. 3, S35) for each of the one or more defects and wherein the programming order (Fig. 3, S35) is an order from a highest defect severity (Fig. 3, S35) to a lowest defect severity (Fig. 3, S35); and program (Fig. 3, S36) the portion of memory (Fig. 2) according to the determined programming order (Fig. 3, S35).
Allowable Subject Matter
11. Claims 4, 11, 17, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. With respect to claim 4, 11, 17, there is no teaching, suggestion, or motivation for combination in the prior art to each of the plurality of decks comprises a top side and a bottom side and wherein the programming order further comprises a direction in which each of the plurality of decks is programmed, the direction indicating whether each of the plurality of decks is programmed from the top side to the bottom side or the bottom side to the top side.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Venkatraman et al (Pub. No.: US 2002/0120826A1).
Venkatraman et al (Pub. No.: US 2002/0120826A1) shows map bad memory blocks.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
01/07/2026
/HAN YANG/
Primary Examiner, Art Unit 2824