DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 10 and 17.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 6/25/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR PACKAGE WITH WARPAGE REDUCTION MEMBERS.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Independent/Claim 1 (and dependent claim(s) 2-9), recite(s) the limitation "the first warpage reduction member" in claim 1, line 14, claim2, lines 1-2, claim 3, line 2, claim 3, lines 1-2, claim 5, lines 1-2, claim 6, line 2, claim 7, line 2, claim 8, lines 1-2, claim 9, line 2.
Claim 9, line 3 recite(s) the limitation “second warpage control member”. There is insufficient antecedent basis for this limitation in the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al., US PG pub. 20210151369 A1;in view of Lee et al., US Patent 8791562 B2.
Re: Independent Claim 1, Kim discloses a substrate (IL1-IL4 and 150, fig. 1) comprising:
an inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) comprising an insulating layer (IL2, IL3, fig. 1) and a wiring layer (CL1, CL2, fig. 1);
a first protective layer (IL1, fig. 1) on a first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1);
a second protective layer (IL4, fig. 1) on a second surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) that is opposite to the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1), and
a first warpage control member (left 150, fig. 1) and a second warpage reduction member (right 150, fig. 1) on the first protective layer (IL1, fig. 1);
a semiconductor chip (110, fig. 1) above the first protective layer (IL1, fig. 1) and connected to the substrate (IL1-IL4 and 150, fig. 1); and
a molding material (160, fig. 1) encapsulating the semiconductor chip (110, fig. 1),
wherein the first warpage reduction member (left 150, fig. 1) is on a first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1),
wherein the second warpage reduction member (right 150, fig. 1) is on a second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1), the second side surface (right side surface, fig. 1) being opposite to the first side surface (left side surface, fig. 1), and
Kim is silent regarding: wherein the first protective layer (IL1, fig. 1) is at least partially covered by the molding material (160, fig. 1) on a third side surface of the substrate (IL1-IL4 and 150, fig. 1) and a fourth side surface of the substrate (IL1-IL4 and 150, fig. 1), the fourth side surface being opposite to the third side surface.
Lee teach the molding material (330, fig. 1) can cover the third and fourth side surface of the substrate (110 and 120, fig. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include molding material covering all side surface of the substrate since this can prevent any moisture getting into the device preventing any breakdown or external damage.
Re: Claim 2, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) comprises an adhesive film or an insulating adhesive (¶0040; epoxy resin).
Re: Claim 3, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein a coefficient of thermal expansion (¶0040; epoxy resin has range of 40-70 ppm/°C) of at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) is 5 ppm/°C to 150 ppm/°C.
Re: Claim 4, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) are continuously and respectively provided along the first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1) and the second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1).
Re: Claim 5, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim is silent regarding : wherein the first warpage reduction member (left 150, fig. 1) comprises a plurality of warpage control portions spaced apart along the first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1), and wherein the second warpage reduction member (right 150, fig. 1) comprises a plurality of warpage control portions spaced apart along the second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1).
Lee teach the warpage reduction member 311 can comprises a plurality of warpage control portions (left 312, fig. 2b) spaced apart along the first side surface of the substrate and wherein the second warpage reduction member comprises a plurality of warpage control portions (right 312, fig. 2b) spaced apart along the second side surface of the substrate 100.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a space apart warpage control portions since this can improve the molding compound which can flow freely through the open spaces between the segments 312 such that can prevent any void risk when forming the molding film.
Re: Claim 6, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim is silent regarding :wherein a thickness of at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) is 5 µm to 20 µm.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify thickness of at least one of the warpage reduction member is 5 µm to 20 µm since such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the packaging device thereby improve the high-density integration.
Re: Claim 7, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim is silent regarding : wherein a width of at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) from an edge of the substrate (IL1-IL4 and 150, fig. 1) is 50 µm to 200 µm.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify thickness of at least one of the warpage reduction member is 50 µm to 200 µm since such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the package device thereby improve the high-density integration.
Re: Claim 8, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) includes a resin and a filler (¶0040; epoxy resin).
Re: Claim 9, Kim and Lee discloses all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the molding material (160, fig. 1) at least partially covers at least one of the first warpage reduction member (left 150, fig. 1) and the second warpage control member (right 150, fig. 1).
Re: Independent Claim 10, Kim discloses a substrate (IL1-IL4 and 150, fig. 1) comprising: an inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) comprising an insulating layer (IL2, IL3, fig. 1) and a wiring layer (CL1, CL2, fig. 1); at least one warpage reduction member (150, fig. 1) above a first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1); a first protective layer (IL1, fig. 1) on the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) and a second protective layer (IL4, fig. 1) on a second surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) that is opposite to the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1); a semiconductor chip (110, fig. 1) above the first protective layer (IL1, fig. 1) and connected to the substrate (IL1-IL4 and 150, fig. 1); and a molding material (160, fig. 1) that encapsulates the semiconductor chip (110, fig. 1), wherein the at least one warpage reduction member (150, fig. 1) is at an edge region of the substrate (IL1-IL4 and 150, fig. 1).
Kim is silent regarding: first protective layer (IL1, fig. 1) at least partially covering the at least one warpage reduction member (150, fig. 1).
Lee teaches a protective layer (350a, fig. 11) at least partially cover the at least one warpage reduction member (310 and 320, fig. 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a protective layer covering at least one warpage reduction member since this can protect external damage when another device form above.
Re: Claim 11, Kim and Lee discloses all the limitations of claim 10 on which this claim depends. Kim further discloses: wherein the at least one warpage reduction member (150, fig. 1) comprises: a first warpage reduction member (left 150, fig. 1) along a first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1); and a second warpage reduction member (right 150, fig. 1) along a second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1).
Re: Claim 12, Kim and Lee discloses all the limitations of claim 11 on which this claim depends. Kim further discloses: wherein the first warpage reduction member (left 150, fig. 1) and the second warpage reduction member (right 150, fig. 1) are continuously and respectively provided along the first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1) and the second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1).
Re: Claim 13, Kim and Lee discloses all the limitations of claim 11 on which this claim depends. Kim is silent regarding: wherein the first warpage reduction member (left 150, fig. 1) comprises a plurality of warpage control portions spaced apart along the first side surface (left side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1), and wherein the second warpage reduction member (right 150, fig. 1) comprises a plurality of warpage control portions spaced apart along the second side surface (right side surface, fig. 1) of the substrate (IL1-IL4 and 150, fig. 1).
Lee teach the warpage reduction member 311 can comprises a plurality of warpage control portions (left 312, fig. 2b) spaced apart along the first side surface of the substrate and wherein the second warpage reduction member comprises a plurality of warpage control portions (right 312, fig. 2b) spaced apart along the second side surface of the substrate 100.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a space apart warpage control portions since this can improve the molding compound which can flow freely through the open spaces between the segments 312 such that can prevent any void risk when forming the molding film.
Re: Claim 14, Kim and Lee discloses all the limitations of claim 10 on which this claim depends. Kim further discloses: wherein the at least one warpage reduction member (150, fig. 1) comprises an adhesive film or an adhesive (¶0040; epoxy resin).
Re: Claim 15, Kim and Lee discloses all the limitations of claim 10 on which this claim depends. Kim further discloses: wherein a coefficient of thermal expansion (¶0040; epoxy resin has range of 40-70 ppm/°C) of the at least one warpage reduction member (150, fig. 1) is 5 ppm/°C to 150 ppm/°C.
Re: Claim 16, Kim and Lee discloses all the limitations of claim 10 on which this claim depends. Kim further discloses: wherein the at least one warpage reduction member (150, fig. 1) comprises a resin and a filler.
Re: Independent Claim 17, Kim discloses a substrate (IL1-IL4 and 150, fig. 1) comprising: an inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) comprising an insulating layer (IL2, IL3, fig. 1) and a wiring layer (CL1, CL2, fig. 1); at least one warpage reduction member (150, fig. 1) above a first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1); and a semiconductor chip (110, fig. 1) above a second surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) that is opposite to the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1), the semiconductor chip (110, fig. 1) connected to the substrate (IL1-IL4 and 150, fig. 1); and a molding material (160, fig. 1) encapsulating the semiconductor chip (110, fig. 1), wherein the at least one warpage reduction member (150, fig. 1) is at an edge region of the substrate (IL1-IL4 and 150, fig. 1). Kim is silent regarding: conductive bumps above the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) and connected to the wiring layer (CL1, CL2, fig. 1).
Lee teaches conductive bumps (230, fig. 11) above the first surface of the inner layer wiring structure (120, fig. 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include solder bumps instead of electrical pad structure since conductive bumps can create a stress absorption and create a physical gap between chip and substrate so that underfill material can flow in underneath dramatically improves mechanical reliability.
Re: Claim 18, Kim and Lee discloses all the limitations of claim 17 on which this claim depends. Kim is silent regarding: a protective layer on the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1) and at least partially covering the at least one warpage reduction member (150, fig. 1).
Lee teaches a protective layer (350a, fig. 11) at least partially cover the at least one warpage reduction member (310 and 320, fig. 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a protective layer covering at least one warpage reduction member since this can protect external damage when another device form above.
Re: Claim 19, Kim and Lee discloses all the limitations of claim 17 on which this claim depends. Kim further discloses: a protective layer (IL1, fig. 1) on the first surface of the inner layer wiring structure (CL1,IL2,CL2,IL3, fig. 1), wherein the at least one warpage reduction member (150, fig. 1) is on the protective layer (IL1, fig. 1).
Re: Claim 20, Kim and Lee discloses all the limitations of claim 17 on which this claim depends. Kim is silent regarding: wherein the at least one warpage reduction member (150, fig. 1) is along an entire perimeter of the edge region of the substrate (IL1-IL4 and 150, fig. 1).
Lee teaches wherein the at least one warpage reduction member (311, fig. 2A) is along an entire perimeter of the edge region of the substrate (100, fig. 2A).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include warpage reduction member is along an entire perimeter of the edge region of the substrate since this have a stronger protection on external force crushing the semiconductor chip at the center region.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Huang et al., US PG pub. 20180261554 A1”) Discloses a semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.
* (“Cho US PG pub. 20180151461 A1”) discloses a wafer level chip package and method of manufacture. The wafer level chip package includes one or more semiconductor dies. A stiffener wall surrounds the one or more semiconductor dies. The stiffener wall extends from an active side to an inactive side of the semiconductor dies. There is a compliant layer encasing the one or more semiconductor dies and the stiffener wall. There is a redistribution layer disposed on the active side of the one or more semiconductor dies. The redistribution layer includes a plurality of interconnects extending to a plurality of ball pads on a surface of the redistribution layer. A plurality of solder balls is electrically connected to the plurality of ball pads.
* (“Jeong et al., US PG pub. 20170178992 A1”) discloses an electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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