Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on June 25, 2024.
2. Claims 1-15 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d),which the certified copy has been has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 03/24/2025, 02/09/2026 and 06/25/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 09/23/2024 are acceptable.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2,4-6, 8-10 and 11-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “a portion of the input voltage” in lined 20 should be “the portion of the input voltage”.
Claims 4-6 recite “the current” in their claims. There are insufficient antecedent basis for these claim limitations.
Claims 8 recites “ a or the number of active levels” should be “ a number of active levels”.
Claim 11 recites “the number of active levels” and “the ratio”. There are insufficient antecedent basis for these claim limitations.
Claim 12 recites “a or the series of phase shifted pulses”, “a or the phase shift”, “a or the number of active levels” and “a or the pulse width” should be “ a series of phase shifted pulses”, “a phase shift” “a number of active levels” and “a pulse width” respectively.
Claim 14 recites “the at least one ” of the input voltage. There is insufficient antecedent basis for this claim limitation.
Claims 9-10 dependent on 8, thus are rejected because of their dependency.
Claim 13 dependent on 12, thus is rejected because of its dependency.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Peng Fan “NPL: A Method of Reconfiguring Flying Capacitor Multilevel Input Stage for Wide Input Voltage Range Converter Design, published August, 18,2021” in a view of Margared “NPL: Dynamic Level Selection for Full Range ZVS in Flying Capacitor Multi-Level Converters, Published June 2018”. Hereafter Peng and Margaret.
In re to claim 1, Peng discloses an n-level flying capacitor multi-level buck converter (Figs. 2 and 11 shows flying capacitor multilevel Buck converter ) for converting a DC input voltage (Vin) into a DC output voltage (Vout) provided at a load (Figs.2 and 11 doesn’t shows a load. However see an introduction, page 11 section G. Light Load Operation Optimization. Furthermore, it is understood that the power converter is configured with load at the output) , comprising: an output filter (Fig. 11 shows an inductor L) comprising: an inductor (inductor L) ;
a first pair of switching elements (S1_H and S1_L) arranged in series with the DC input voltage (Vin) ; and
a second pair of switching elements (S2_H and S2_L) arranged in series with the DC input voltage (Vin) ;
wherein each of the first and second pairs of switching elements comprises a first switching element and a second switching element (S1_H & S2_H and S2_H & S2_L respectively) ;
wherein the first switching element and the second switching element of the first pair of switching elements are arranged adjacent each other ( S1_H and S1_L are adjacent ) ;
wherein the first switching element of the second pair of switching elements is arranged adjacent to the first switching element of the first pair of switching elements (S1_H and S2_H are adjacent );
wherein the second switching element of the second pair of switching elements is arranged adjacent to the second switching element of the first pair of switching elements (S2_L and S1_L are adjacent);
wherein the output filter is arranged in series with the first switching elements of the first and second pairs of switching elements (S1_H and S1_L are arranged in series with inductor L) , and in parallel with the second switching elements of the first and second pairs of switching elements (S2_H and S2_L) ;
wherein the n-level flying capacitor multi-level buck converter (Figs.1 and 11) further comprises a first flying capacitor (C1) in parallel with the first pair of switching elements (S1_H and S1_L) ; and
wherein the n-level flying capacitor multi-level buck converter is configured to: operate the first and second pairs of switching elements in a sequence to selectively apply a portion of the input voltage across the output filter (see Figs. 3,11 and Table I and II); and operate the first and second pairs of switching elements such that each switching element is switched on when a voltage across the switching element is zero (see page 11 section G, page 16, second colon lines 7-21, page 17, first colon lines 5-13 .).
Peng discloses an output filter inductor but fails to discloses an inductor is arranged in series with the output capacitor and configured to be arranged in series with the load ; and wherein the output capacitor arranged in series with the inductor and configured to be arranged in parallel with the load.
Margaret discloses multilevel flying capacitor (Fig. 2) having an output filter inductor is arranged in series with the output capacitor and configured to be arranged in series with the load (inductor L is arranged in series with the output capacitor Cout) ; and wherein the output capacitor arranged in series with the inductor and configured to be arranged in parallel with the load (Cout arranged in series with the inductor and configured to be arranged in parallel with the load resistor (R)).
Therefore, it would have been obvious to one of the ordinary skilled person in the art before the effective filing date of the claimed invention to modify the multilevel power converter of Peng to include an output capacitor in series inductor and configured to be arranged in series with the load as taught by Margaret in order to maximum improvement in power quality, efficiency, and system reliability by reducing harmonics and distortion at the load.
In re to claim 2, Peng as modified discloses (Figs. 3 and 11), wherein: the n-level flying capacitor multi-level buck converter (Figs. 3 and 110 further comprises a third pair of switching elements (S3_H and S3_L) ;
the third pair of switching elements (S3_H and S3_L) is arranged in series with the DC input voltage (Vin) ;
the third pair of switching elements comprises a first switching element (S3_H) and a second switching element (S3_L);
the first switching element of the third pair of switching elements is arranged adjacent to the first switching element of the second pair of switching elements (S3_H is adjacent to S2_H );
the second switching element of the third pair of switching elements is arranged adjacent to the second switching element of the second pair of switching elements (S3_L is adjacent to S2_L );
the output filter is arranged in series with the first switching element of the third pair of switching elements; and in parallel with the second switching element of the third pair of switching elements (it is understood that when S3_H and S3_L operate in ON and OFF state that could be arranged the switch to configure either in series or parallel to the inductor, see table II, and Figs. 3 and 11); and
wherein the n-level flying capacitor multi-level buck converter further comprises a second flying capacitor (C2) in parallel with the second pair of switching elements (S2_H and S2L) ; and
wherein the n-level flying capacitor multi-level buck converter is configured to:
operate the third pair of switching elements in a sequence to selectively apply a portion of the input voltage across the output filter (see table II and Fig. 3); and
operate the third pairs of switching elements such that each switching element is switched on when a voltage across the switching element is zero (see page 11 section G, page 16, second colon lines 7-21, page 17, first colon lines 5-13 .)
In re to claim 3, Peng as modified discloses (Figs. 3 and 11), wherein the first switching element of each pair of switching elements is arranged to be switched off before the second switching element of each pair of switching elements is switched on ; and wherein the second switching element of each pair of switching elements is arranged to be switched off before the first switching element of each pair of switching elements is switched on (S1_H and S1_L are working in a complementary fashion, see table II) .
In re to claim 4, Peng as modified discloses (Figs. 3 and 11), wherein the n-level flying capacitor multi-level buck converter is arranged such that the current through the inductor is zero when the second switching element of each pair of switching elements is switched off (see page 11 section G, and page 12 layout consideration section and Fig.11 .)
In re to claim 5, Peng as modified discloses (Figs. 3 and 11), wherein the n-level flying capacitor multi-level buck converter is arranged such that the current through the inductor is less than zero when the second switching element of each pair of switching elements is switched off (see page 11 section G, and page 12 layout consideration section and Fig.11 .)
In re to claim 6, Peng as modified discloses (Figs. 3 and 11),, wherein the n-level flying capacitor multi-level buck converter is arranged such that the current through the inductor is a predetermined value when the second switching element of each pair of switching elements is switched off (see page 11 section G, and page 12 layout consideration section and Fig.11 .)
In re to claim 7, Peng as modified discloses (Figs. 3 and 11), wherein: the pairs of switching elements are arranged to be triggered by a series of phase shifted pulses; a phase shift of the phase shifted pulses corresponds to a number of active levels of the n-level flying capacitor multi-level buck converter ; and a pulse width (see page 3, col. 1, parag. 4 and page 4, parag.1 and page 5, colon. 2 parag. 4) of the phase shifted pulses corresponds to a duty cycle of the n-level flying capacitor multi-level buck converter (It is understood that as shown in Table II and Figs.3 and 5 shows that the number of active levels of the n-level FCML buck causes a phase shift pulse corresponds to duty cycle, see pages 7-9 and 16 first and second colon) .
Furthermore, Margaret discloses of a phase shift (see page 2 col.1 and page 3 col.2) and duty cycle (whole documents).
In re to claim 8, Peng as modified discloses (Figs. 3 and 11), wherein the n-level flying capacitor multi-level buck converter is configured to operate the pairs of switching elements to change a or the number of active levels of the n-level flying capacitor multi-level buck converter (Fig. 3 shows a multilevel flying capacitor buck converter and see table II shows the operation ).
In re to claim 11 , Peng as modified discloses (Figs. 3 and 11),wherein the n-level flying capacitor multi-level buck converter is configured to change the number of active levels depending on at least one of the input voltage, the output voltage or the ratio between the input voltage and the output voltage (Fig. 6 shows the input stage is configured with a different dividing ratio as the input voltage changes from 30 to 135 V and the output voltage is 20 V. The base frequency at the switching node is 2 MHz, see page 8, col. 1 lines 3-5.)
In re to claim 12 , Peng as modified discloses (Figs. 3 and 11),wherein the n-level wherein the n-level flying capacitor multi-level buck converter further comprises a controller (Fig. 10 shows a controller) arranged to generate a or the series of phase shifted pulses to trigger the pairs of switching elements of the n-level flying capacitor multi-level buck converter (Table II and Figs.2-3 and 5) : wherein a or the phase shift of the phase shifted pulses corresponds to a or the number of active levels of the n-level flying capacitor multi-level buck converter; and wherein a or the pulse width of the phase shifted pulses corresponds to a or the duty cycle of the n-level flying capacitor multi-level buck converter (Table II and Figs.2-3 and 5 ) .
In re to claim 13 , Peng as modified discloses (Figs. 3 and 11),, wherein the controller (Fig. 10 shows a controller) further comprises a current feedback loop which adjusts a switching frequency of the switching elements based on a current through the inductor (Fig. 4 shows the pulse can be modulated with pulse width or pulse frequency, depending on the type of converter. The feedback loop automatically ensures Vout following the reference voltage, see page 5, colon: 2, parag. 4).
In re to claim 14 , Peng as modified discloses (Figs. 3 and 11),, wherein the controller (Fig. 10 shows a controller) further comprises a voltage feedback loop which adjusts the duty cycle based on the at least one of the input voltage (Fig. 4 shows the pulse can be modulated with pulse width or pulse frequency, depending on the type of converter. The feedback loop automatically ensures Vout following the reference voltage, see page 5, colon: 2, parag. 4), the output voltage or the ratio between the input voltage and the output voltage 9(Fig. 6 shows the input stage is configured with a different dividing ratio as the input voltage changes from 30 to 135 V and the output voltage is 20 V. The base frequency at the switching node is 2 MHz, see page 8, col. 1 lines 3-5.)
In re to claim 15, Peng discloses a method of operating an n-level flying capacitor multi-level buck converter (Figs. 2 and 11 shows a method for flying capacitor multilevel Buck converter ), for converting a DC input voltage (Vin) into a DC output voltage (Vout) provided at a load (Figs.2 and 11 doesn’t shows a load. However see an introduction, page 11 section G. Light Load Operation Optimization. Furthermore, it is understood that the power converter is configured with load at the output),
wherein the n-level flying capacitor multi-level buck converter comprises (Figs. 2 and 11):
an output filter (Fig. 11 shows an inductor L) comprising:
an inductor with the load (it is understood that an inductor is coupled to the load); and
wherein the n-level flying capacitor multi-level buck converter (Figs. 2 and 11comprises:
a first pair of switching elements (S1_H and S1_L) arranged in series with the DC input voltage (Vin) ; and
a second pair of switching elements (S2_H and S2_L) arranged in series with the DC input voltage (Vin) ;
wherein each of the first and second pairs of switching elements comprises a first switching element and a second switching element ((S1_H & S2_H and S2_H & S2_L respectively) ;
wherein the first switching element and the second switching element of the first pair of switching elements are arranged adjacent ( S1_H and S1_L are adjacent );
wherein the first switching element of the second pair of switching elements is arranged adjacent to the first switching element of the first pair of switching elements (S1_H and S2_H are adjacent );
wherein the second switching element of the second pair of switching elements is arranged adjacent to the second switching element of the first pair of switching elements (S2_L and S1_L are adjacent);; and
wherein the output filter is arranged in series with the first switching elements of the first and second pairs of switching elements (S1_H and S1_L are arranged in series with inductor L), and in parallel with the second switching elements of the first and second pairs of switching elements (S2_H and S2_L) ;
wherein the n-level flying capacitor multi-level buck converter (Figs.2 and 11) further comprises a first flying capacitor (C1) in parallel with the first pair of switching elements (S1_H and S1_L) ; and
wherein the method comprises:
operating the first and second pairs of switching elements in a sequence to selectively apply a portion of the input voltage across the output filter (see Figs. 3,11 and Table I and II); and
operating the first and second pairs of switching elements such that each switching element is switched on when a voltage across the switching element is zero (see page 11 section G, page 16, second colon lines 7-21, page 17, first colon lines 5-13 .)
Peng discloses an output filter inductor but fails to discloses an inductor is arranged in series with the output capacitor and configured to be arranged in series with the load ; and wherein the output capacitor arranged in series with the inductor and configured to be arranged in parallel with the load.
Margaret discloses multilevel flying capacitor (Fig. 2) having an output filter inductor is arranged in series with the output capacitor and configured to be arranged in series with the load (inductor L is arranged in series with the output capacitor Cout) ; and wherein the output capacitor arranged in series with the inductor and configured to be arranged in parallel with the load (Cout arranged in series with the inductor and configured to be arranged in parallel with the load resistor (R)).
Therefore, it would have been obvious to one of the ordinary skilled person in the art before the effective filing date of the claimed invention to modify the multilevel power converter of Peng to include an output capacitor in series inductor and configured to be arranged in series with the load as taught by Margaret in order to maximum improvement in power quality, efficiency, and system reliability by reducing harmonics and distortion at the load.
Allowable Subject Matter
8. Claims 9-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 9 is objected because the prior art in the record fails to discloses or suggest the n-level flying capacitor multilevel buck converter including the limitation of “wherein the n-level flying capacitor multi-level buck converter is configured to reduce the number of active levels by switching on both the first switching element and the second switching element of the pair of switching elements arranged proximate to the DC input voltage.”
Claim 10 dependent on claim 9, thus is objected because of its dependency.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fang “12506406” the present invention discloses a reconfigurable flying capacitor multilevel input stage accepts a wide range of input voltages. The input stage divides and inverts a DC input voltage. Generally, output voltage regulation is achieved by adjusting the power switches' duty ratio in the input stage for non-resonant converters and by adjusting the switching frequency for resonant converters.
Yoscovich “20250119066” the present invention discloses a multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.
Abdelhamid “20230216407” the present disclosure relates to the field of inverting buck-boost converters for inverting an input voltage to generate an inverted output voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838