Detailed action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on June 25,2024.
2. Claims 1-20 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 02/19/2025,01/22/2026,06/06/2025,04/11/2025,12/05/2024,11/14/2024,09/20/2024 and 06/25/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 06/25/2024 are acceptable.
Claim Rejections - 35 USC § 112
6.The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4,12 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the maximum difference”. There is insufficient antecedent basis for this claim limitation.
Claim 12 recite “a short circuit…” in line 3 should be “the short circuit..”.
Claim 16 recite “a voltage deviation ΔV” in 7 should be “the voltage deviation ΔV”.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 and 14-20 are rejected under 35 U.S.C. 102(a)(1) (a)(2) as being anticipated by Garrett “20220149725” .
In re to claim 1, Garrett discloses a system (Fig. 3) a system for circuits Examiner noted that Figures 1-15 are considered as same embodiments) comprising: a differential multilevel converter (Figure 3, differential multilevel converter 58; paragraph 63) comprising:
a differential input including a first input terminal (Figure 3, first input terminal VA) configured to be coupled to a first voltage V.sub.A and a second input terminal (Figure 3, second input terminal
VB) configured to be coupled to a second, different voltage V.sub.B; a plurality of switches S.sub.A, S.sub.A′, S.sub.B, S.sub.B′ (Figure 3, switches Ssc1, Ssc2, Ssc3 , and Ssc4; Paragraph 64) coupled between the first and second input terminals (VA and VB);
a capacitor C.sub.f (Figure 3, capacitor CT; Paragraph 64) having a first terminal coupled to a first terminal of a first one of the plurality of switches (node between Ssc1 and Ssc2) and a second terminal coupled to a first terminal of a second (node between Ssc3 and Ssc4), different one of the plurality of switches (Ssc1-Ssc4); and
an output terminal (Vc1) coupled to a first terminal of a third, different one of the plurality of switches (Ssc1-Ssc4); and a controller (a controller to control the switches, see parag. 0064 and Fig. 12) coupled to the plurality of switches and configured to control selected ones of the plurality of switches S.sub.A, S.sub.A′, S.sub.B, S.sub.B′ to switch, at points in time, between a plurality of switch states with each switch state producing an output voltage V.sub.sm corresponding to one of three discrete voltage levels L1, L2, L3 at the output terminal of the differential multilevel converter (Figure3, voltages levels VA, V 8 and V c1; paragraph 64), wherein at least two of the plurality of switch states produce an output voltage which is substantially the same (Figure 3, when the switches Sc1 and Sc3 are controlled on or when the switches Sc2 and Sc4 are controlled on, the output Vc1=(VA+VB)/2; Paragraph 64) and at those points in time when ones of the plurality of switches switch among the at least two switch states producing the substantially same output voltage, the controller seeks to maintain a voltage V.sub.cf across the capacitor C.sub.f within a voltage deviation ΔV (In the states when the switches Sc1 and Sc3 are controlled on and when the switches Sc2 and Sc4 are controlled on, the capacitor CT is charged or discharged which implies that the there is a voltage deviation of the voltage across CT. As disclosed in paragraph 64, the switches are controlled such as the voltage Vc1 remains near (VA+V8)/2) of a target voltage (Figure 3, target voltage of (VA+V8)/2) and wherein the voltage deviation ΔV determines a maximum deviation of the substantially same output voltage from an ideal output voltage (see parag. parag. 0063-0064, 0093 and 0096) .
In re to claim 2, . Garrett discloses (Fig.3) wherein the voltage deviation ΔV from a voltage corresponding to a voltage of (V.sub.B−V.sub.A)/2 determines a maximum deviation of one of the three discrete voltage levels corresponding to a voltage of (V.sub.A+V.sub.B)/2 (Figure 3, when the switches Sc1 and Sc3 are controlled on for example and when the Vc1=(VA+V8)/2, it is implicit to consider that Vct=(Vb-VA)/ 2 since Vb-Vc1=VT, see parag.0064)
In re to claim 3, Garrett discloses (Fig.3) a first one of the three discrete voltage levels corresponds to the first voltage V.sub.A; a second one of the three discrete voltage levels corresponds to one of: a voltage of V.sub.B−V.sub.cf; or a voltage of V.sub.A+V.sub.cf; and a third one of the three discrete voltage levels corresponds to the second voltage V.sub.B (see parag. 0064 and Fig.3) .
In re to claim 4, Garrett discloses (Fig.3) wherein at least some of the differential multi-level converter switches (Ssc1-Ssc4) have a unidirectional blocking characteristic to block less than or equal to the maximum difference between the first and second voltages V.sub.A, V.sub.B but more than one-half of a maximum difference between the first and second voltages V.sub.A, V.sub.B (implicitly in a flying capacitor. Furthermore. See parag. 0037 and 0123).
In re to claim 5, Garrett discloses (Fig.3) wherein the plurality of switches is provided as four switches (S.sub.A, S.sub.B, S.sub.A′, S.sub.B′) (Fig.3) coupled to provide four (4) switch states with each switch state generating a specified output voltage V.sub.sm at the output terminal of the differential multi-level converter such that: TABLE-US-00004 State Switches On v.sub.SM Level 1 S.sub.A, S.sub.B v.sub.B L3 2 S.sub.A, S.sub.B′ v.sub.B − v.sub.cf L2 3 S.sub.B, S.sub.A′ v.sub.A + v.sub.cf L2 4 S.sub.B′, S.sub.A′ v.sub.A L1 and wherein, at discrete points in time, the differential multilevel converter provides one of the three voltage levels L1, L2, L3 at the differential multilevel converter output terminal with the voltage at level L1 substantially corresponding to the first input voltage V.sub.A; the voltage at level L3 substantially corresponding to the second input voltage V.sub.B; and the voltage at level L2 substantially corresponding to a voltage of (V.sub.A+V.sub.B)/2 (see parag. 0064 and Fig.3).
In re to claim 6, Garrett discloses (Fig.3) wherein the controller (see prag. 0064 and Fig. 12) provides control signals to control ones of the plurality of switches to switch between switch states 2 and 3 on an unclocked basis (see parag. 0064 and Fig.3).
In re to claim 7, Garrett discloses (Fig.3) wherein switching between states 2 and 3 occurs when the voltage V.sub.cf across the capacitor exceeds the voltage deviation ΔV above or below (V.sub.A−V.sub.B)/2 (see parag. 0064 and Fig.3)..
In re to claim 8, Garrett discloses (Fig.3) a multi-output regulation stage having a single input coupled to receive an input voltage V.sub.IN, a first output A coupled to the first input terminal of the differential multilevel converter (Fig:3 multi-output regulation stage 56 is configured to receive Vin from the + terminal of 54) and a second output B coupled to the second input terminal of the differential multilevel converter (Fig:3 multi-output regulation stage 56 is configured to receive Vin from the - terminal of 54), the multi-output regulation stage operable to synthesize a first intermediate voltage V.sub.A at the first output and a second intermediate voltage V.sub.B at the second output (see parag.0063-0064).
In re to claim 9, Garrett discloses (Fig.3) wherein the two intermediate voltages VA and VB are independently controllable (see Fig. 3 and parag.0063-0064).
In re to claim 10, Garrett discloses (Fig.3)a multi-output regulation stage having a single input coupled to receive an input voltage V.sub.IN and a first output A coupled to the first input terminal of the differential multilevel converter (see Fig.3) , the multi-output regulation stage comprising a buck converter having an input coupled to receive the input voltage V.sub.IN and having a first output at which is provided the first output voltage VA with the first output of the buck converter coupled to the first output A of the multi-output regulation stage (see Fig. 3 and parag.0064).
In re to claim 11, Garrett discloses (Fig.3) wherein the plurality of switches corresponds to four switches (Sx, Sy,SA and SB )between the first and second input terminals of the differential multilevel converter with the four switches coupled such that with all switches in their on state (Fig. 3) , a short circuit signal path exists between the first and second input terminals of the differential multilevel converter, and wherein: a first one of the four switches has first and second terminals with the first terminal coupled to the first input terminal of the differential multilevel converter (Fig. 3 : 56); a second one of the four switches has first and second terminals with the first terminal coupled to the second terminal of the first one of the four switches; a third one of the four switches has first and second terminals with the first terminal coupled to the second terminal of the second one of the four switches; a fourth one of the four switches has first and second terminals with the first terminal coupled to the second terminal of the third one of the four switches and a second terminal coupled to the second input terminal of the differential multilevel converter; and the capacitor is a first capacitor C having first and second terminals with the first terminal of the first capacitor coupled between the second terminal of the first switch and the first terminal of the second switch and the second terminal of the first capacitor coupled between the second terminal of the third switch and the second terminal of the fourth switch (See Fig. 3 and parg. 0063-0064).
In re to claim 12, Garrett discloses (Fig.3) wherein the four switches (Sx, Sy,SA and SB ) coupled between the first and second input terminals of the differential multilevel converter (Fig.3 :56) are arranged such that with all switches in their on state, a short circuit signal path exists between the first and second input terminals of the differential multilevel converter (see Fig.3).
In re to claim 14, Garrett discloses (Fig.3) wherein the differential multilevel converter (Fig. 3) further comprises a linear circuit coupled to the capacitor to maintain voltages across the capacitor to within a desired range during time periods during which the switch state does not provide charging/discharging control of the voltage across the capacitor (Fig. 1: optional filter 16a).
In re to claim 15, Garrett discloses system comprising: a hybrid supply generator and modulator (Figure 3; Paragraphs 63-64) comprising: a differential multilevel converter (Figure 3, differential multilevel converter 58) comprising: a differential input including a first input terminal configured to be coupled to a first voltage V.sub.A (Figure 3, first input terminal
VA) and a second input terminal configured to be coupled to a second, different voltage V.sub.B (Figure 3, second input
terminal Vs); a plurality of switches (Figure 3, switches Sc1, ... , Sc4) coupled between the first and second input terminals with the plurality of switches (Fig. 3); at least one capacitor C.sub.f (Figure 3, capacitor CT) having a first terminal coupled to a first terminal of a first one of the plurality of switches (node between Ssc1 and Ssc2) and a second terminal coupled to a first terminal of a second (node between Ssc3 and Ssc4),, different one of the plurality of switches (see Fig. 3) ; and
an output terminal (Vc1) coupled to a first terminal of a third, different one of the plurality of switches (Fig. 3) ; and
a multi-output regulation stage (Figure 3, multi-output regulation stage 56) having a single input configured to receive an input voltage V.sub.IN (Figure 3, input voltage V1N),, a first output A coupled to the first input terminal of the differential multilevel converter and a second output B coupled to the second input terminal of the differential multilevel converter (see Fig. 3) , the multi-output regulation stage operable to synthesize a first intermediate voltage V.sub.A at the first output and a second intermediate voltage V.sub.B at the second output wherein, in response to control signals provided thereto, the plurality of switches of the differential multilevel converter are operable to switch between a plurality of switch states with each switch state producing an output voltage V.sub.sm corresponding to at least one of three discrete voltage levels L1, L2, L3 at the output terminal of the differential multilevel converter (Figure 3, paragraphs 63-64 with voltage levels VA, Vs and Vc1),
wherein at least two of the plurality of switch states produce an output voltage which is substantially the same (Figure 3, when the switches Sc1 and Sc3 are controlled on or when the switches Sc2 and Sc4 are controlled on, the output Vc1=(VA+VB)/2; Paragraph 64) and at those points in time when ones of the plurality of switches switch among the at least two switch states producing the substantially same output voltage, the switches are operable to seek to maintain a voltage across each of the at least one capacitors C.sub.f within a voltage deviation ΔV (In the states when the switches Sc1 and Sc3 are controlled on and when the switches Sc2 and Sc4 are controlled on, the capacitor CT is charged or discharged which implies that the there is a voltage deviation of the voltage across CT. As disclosed in paragraph 64, the switches are controlled such as the voltage Vc1 remains near (VA+V8)/2) of a target voltage (Figure 3, target voltage of (VA+V8)/2) and wherein the voltage deviation ΔV determines a maximum deviation of the substantially same output voltage from an ideal output voltage (see parag. 0063-0064 and 0093 and 0096) .
In re to claim 16, Garrett discloses (Fig.3) a controller (see praag. 0064 and Fig. 12) coupled to the plurality of switches of the differential multilevel converter, the controller operable to provide control signals to the plurality of switches (Figure 3, switches Sc1, ... , Sc4) to control the switches between on and off states such that the switches switch between the plurality of switch states and wherein when ones of the plurality of switches switch between states producing the substantially same output voltage (see prag. 0064 and Fig.3) , the controller provides control signals acts to maintain a voltage across each of the at least one capacitors within a voltage deviation ΔV of a target voltage and wherein the voltage deviation ΔV determines a maximum desired deviation of a discrete voltage level from an ideal voltage level (see parag. 0063-0064 and 0093 and 0096) .
In re to claim 17, Garrett discloses (Fig.3) the hybrid supply generator and modulator is provided as an integrated circuit comprising at least the differential multilevel converter (see prag. 0042).
In re to claim 18, Garrett discloses (Fig.3. ) comprising a radio frequency (rf) amplifier having a supply terminal coupled to the output terminal of the differential multilevel converter (Figure 1 A, radio frequency amplifier 18; Paragraph 40.)
In re to claim 19, Garrett discloses a system (Fig. 3. Examiner noted that Figures 1-15 are considered as same embodiments) comprising : a differential multilevel converter (Figure 3, differential multilevel converter 58; Paragraph 63) comprising: a differential input including a first input terminal (Figure 3, first input terminal VA) configured to be coupled to a first voltage V.sub.A and a second input terminal (Figure 3, second input terminalVB) configured to be coupled to a second, different voltage V.sub.B;
a plurality of switches (Figure 3, switches Ssc1, Ssc2, Ssc3 , and Ssc4; Paragraph 64) coupled between the first and second input terminals with the plurality of switches (VA and VB);
at least one capacitor C.sub.f (Figure 3, capacitor CT; Paragraph 64) having a first terminal coupled to a first terminal of a first one of the plurality of switches (node between Ssc1 and Ssc2) and a second terminal coupled to a first terminal of a second (node between Ssc3 and Ssc4), different one of the plurality of switches (Ssc1-Ssc4); and an output terminal (Vc1) coupled to a first terminal of a third, different one of the plurality of switches Ssc1-Ssc4);, wherein, in response to control signals provided thereto (a controller to control the switches, see parag. 0064 and Fig. 12), the plurality of switches of the differential multilevel converter are operable to switch between a plurality of switch states with each switch state producing an output voltage V.sub.sm corresponding to at least one of three discrete voltage levels L1, L2, L3 at the output terminal of the differential multilevel converter Figure3, voltages levels VA, V 8 and V c1; paragraph 64),
and wherein at least two of the plurality of switch states produce an output voltage which is substantially the same (Figure 3, when the switches Sc1 and Sc3 are controlled on or when the switches Sc2 and Sc4 are controlled on, the output Vc1=(VA+VB)/2; Paragraph 64) and at those points in time when ones of the plurality of switches switch among the at least two switch states producing the substantially same output voltage, the switches are operable to seek to maintain a voltage across each of the at least one capacitors Cr within a voltage deviation ΔV (In the states when the switches Sc1 and Sc3 are controlled on and when the switches Sc2 and Sc4 are controlled on, the capacitor CT is charged or discharged which implies that the there is a voltage deviation of the voltage across CT. As disclosed in paragraph 64, the
switches are controlled such as the voltage Vc1 remains near (VA+V8)/2) of a target voltage (Figure 3, target voltage of (VA+V8)/2) and wherein the voltage deviation ΔV determines a maximum target deviation of the substantially same output voltage from an ideal output voltage (see parag. 0063-0064, 0093 and 0096) .
In re to claim 20, Garrett discloses (Fig.3.) a controller coupled to the plurality of switches to provide control signals to control the plurality of switches which act to maintain a voltage V.sub.cf across the at least one capacitor within a voltage deviation ΔV of a first target voltage (D1, Figure 3; paragraphs 63-64).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Garrett “20220149725” in view of Szczesynski “20240305192” .
In re to claim 20, Garrett discloses (Fig.3.) the capacitor is a first capacitor C.sub.f1 (Fig. 3: CT) and the differential multilevel converter (56) but fails discloses further comprises a second capacitor C.sub.f2 and the plurality of switches corresponds to six switches and wherein: a first one of the six switches has first and second terminals with the first terminal coupled to the first input terminal of the differential multilevel converter; a second one of the six switches has first and second terminals with the first terminal coupled to the second terminal of the first one of the six switches; a third one of the four switches has first and second terminals with the first terminal coupled to the second terminal of the second one of the six switches; a fourth one of the six switches has first and second terminals with the first terminal coupled to the second terminal of the third one of the six switches; a fifth one of the four switches has first and second terminals with the first terminal coupled to the second terminal of the fourth one of the six switches; a sixth one of the six switches has first and second terminals with the first terminal coupled to the second terminal of the fifth one of the six switches and the second terminal coupled to the second input terminal of the differential multilevel converter; the first capacitor C.sub.f1 has first and second terminals with the first terminal of the first capacitor coupled to the second terminal of the second switch and the first terminal of the third switch and the second terminal coupled to the second terminal of the fourth switch and the first terminal of the fifth switch; and the second capacitor C.sub.f2 has first and second terminals with the first terminal of the second capacitor coupled to the second terminal of the first switch and the first terminal of the second switch and the second terminal coupled to the second terminal of the fifth switch and the first terminal of the sixth switch.
Whereas, Szczesynski discloses M-level multi-level converter cell 400 that may be used as the converter circuit 102 (Figs. 4A-4b) shows a set of switches, S1-S[2*(M−1)], is series-coupled between V.sub.IN and circuit ground and set of M−2 fly capacitor C2 is coupled in series with certain respective switches (see FIG. 4B), and in parallel with switches in between those switches and In terms of switch pairs, there are M−1 pairs of switches, or one more than the number of fly capacitors (see parag. 0064-0066).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the power converter of Garrett to include set of pair switches and flying capacitor as taught by Szczesynski because the additional pair of switch and second flying capacitor are increases power density, balances voltage across switches, and significantly reduces voltage and current ripple, thus improve the reliability of the power converter.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Perreanult “11637531” the present invention disclose concepts, circuits, systems and techniques directed toward N-phase control techniques useful in the design and control of supply generators configured for use in a wide variety of power management applications including, but not limited to mobile applications.
Perreanult “10840805” An integrated power supply and modulator system includes integrated power supply and modulator system includes three subsystems: a switched-capacitor voltage balancer stage; a magnetic regulation stage; and at least one output switching stage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838