Detail Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 06-25-2024 under new application; which have been placed of record in the file. Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06-25-2024, 01-16-2025, 10-22-2025, 03-04-2026, 03-10-2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. . 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c).
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over DOYLE MICHAEL et al. (US-20210090207-A1) hereinafter referenced as DOYLE et al. in view of Yang; Xile et al. (US-20210248806-A1) here in after referenced as Yang et al.
Regarding Claim 1, DOYLE et al. discloses An apparatus (para. 1. abstract) comprising: first circuitry (paras, 168, 177, 275, 267, disclosing storing memory control circuitry) configured to store quantized primitive data as one or more fixed-size data blocks (Abstract, disclosing An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure para. 304, disclosing , quantized primitive data are stored in fixed packet size data blocks, however, please notice DOYLE et al. do not recite one or more fixed-size data blocks ), wherein quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure (please see abstract, para. 336 disclosing quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure); and second circuitry configured to: receive the one or more fixed-size data blocks as input; and construct the acceleration data structure based at least in part on quantized primitive data stored in each of the one or more fixed-size data blocks (please see para. 304, disclosing ,quantized primitive data are stored in fixed packet size data blocks please see abstract, para. 336 disclosing quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure and abstract, Claims, 28-29, 35-36 and 42-43 disclosing plurality of the circuitry evaluating potential second level groupings of said first level nodes in the hierarchical ray tracing acceleration structure to determine an efficiency estimation for each said potential second level grouping; and based on said efficiency estimation for each potential second level grouping, merging the first level nodes to form second level nodes in the hierarchical ray tracing acceleration structure and further evaluating potential third level groupings of said second level nodes in the hierarchical ray tracing acceleration structure to determine an efficiency estimation for each potential third level grouping, and based on said efficiency estimation for each potential third level grouping, merging the second level nodes to form third level nodes in the hierarchical ray tracing acceleration).
However, DOYLE et al. fails to explicitly recite one or more fixed-size data blocks.
However, prior art of Yang et al. at paras. 7, 8 disclosing similar to quantizing process via disclosing primitives are grouped in to the primitive blocks by dividing rendering space into the micro regions maps to the tiles to be rendered, and grouping the transformed primitive into the primitive blocks. (If the primitive block generator 110 determines that the primitive falls, at least partially, within only one macro region, then the primitive block generator 110 may place the primitive (i.e. the transformed geometry data related to that primitive) in the primitive block for that macro region. If the primitive block generator 110 determines that the primitive falls within more than one macro region then the primitive block generator 110 may be configured to (i) select one of the macro regions the primitive falls within (e.g. the first one) and place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for the selected macro region; or (ii) place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for each of the macro regions the primitive falls, at least partially, within), paras. 17-18 reciting storing primitive fixed size primitive data block memories.
DOYLE et al. teaches An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure.
DOYLE et al. teaches a quantization factor may be employed to quantize all coordinate values associated with the BVH, primitives, and rays.
Yang et al. teaches primitive data stored in each data block corresponds to primitives that are grouped together
DOYLE et al. does not teach primitive data stored in each data block corresponds to primitives that are grouped together
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, DOYLE et al. performs the same function as it does separately of managing process primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration
Structure.
Yang et al. performs the same function as it does separately of allowing primitive data stored in each data block corresponds to primitives that are grouped together.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of DOYLE et al. to include primitive data stored in each data block corresponds to primitives that are grouped together, as disclosed by Yang et al. thereby Storing the primitives in primitive blocks may allow the transformed geometry data for a set of primitives to be stored more efficiently in memory as Yang et al. discusses at paras. 6, 157.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 2, DOYLE et al. discloses the at least one node is a bottom-level acceleration structure (BLAS) internal node of the acceleration data structure (para. 336)
Regarding Claim 3, Yang et al. discloses a predetermined number of data blocks of the one or more fixed-size data blocks together form a data node (abstract) wherein the data node represents the BLAS internal node of the acceleration data structure (para. 336).
Regarding Claim 6, DOYLE et al. discloses the second circuitry is configured to receive the one or more fixed-size data blocks as input, through a graphics application programming interface (API) (para. 115 discloses specific geometry data compute pixel color data for each geometric fragment (quantized primitive block)).
Regarding Claim 7, DOYLE et al. discloses primitives in each cluster comprise primitives that together represent a single node of the acceleration data structure (please see Abstract, disclosing An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters).
Regarding Claim 8, DOYLE et al. discloses A method of A method comprising: quantizing, by a first circuitry, primitive data corresponding to a set of primitives (para. 304) store quantized primitive data as one or more fixed-size data blocks (Abstract, disclosing An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure para. 304, disclosing , quantized primitive data are stored in fixed packet size data blocks, however, please notice DOYLE et al. do not recite one or more fixed-size data blocks ), wherein quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure (please see abstract, para. 336 disclosing quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure); and second circuitry configured to: receive the one or more fixed-size data blocks as input; and construct the acceleration data structure based at least in part on quantized primitive data stored in each of the one or more fixed-size data blocks (please see para. 304, disclosing ,quantized primitive data are stored in fixed packet size data blocks please see abstract, para. 336 disclosing quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure and abstract, Claims, 28-29, 35-36 and 42-43 disclosing plurality of the circuitry evaluating potential second level groupings of said first level nodes in the hierarchical ray tracing acceleration structure to determine an efficiency estimation for each said potential second level grouping; and based on said efficiency estimation for each potential second level grouping, merging the first level nodes to form second level nodes in the hierarchical ray tracing acceleration structure and further evaluating potential third level groupings of said second level nodes in the hierarchical ray tracing acceleration structure to determine an efficiency estimation for each potential third level grouping, and based on said efficiency estimation for each potential third level grouping, merging the second level nodes to form third level nodes in the hierarchical ray tracing acceleration).
However, DOYLE et al. fails to explicitly recite one or more fixed-size data blocks.
However, prior art of Yang et al. at paras. 7, 8 disclosing similar to quantizing process via disclosing primitives are grouped in to the primitive blocks by dividing rendering space into the micro regions maps to the tiles to be rendered, and grouping the transformed primitive into the primitive blocks. (If the primitive block generator 110 determines that the primitive falls, at least partially, within only one macro region, then the primitive block generator 110 may place the primitive (i.e. the transformed geometry data related to that primitive) in the primitive block for that macro region. If the primitive block generator 110 determines that the primitive falls within more than one macro region then the primitive block generator 110 may be configured to (i) select one of the macro regions the primitive falls within (e.g. the first one) and place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for the selected macro region; or (ii) place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for each of the macro regions the primitive falls, at least partially, within), paras. 17-18 reciting storing primitive fixed size primitive data block memories.
DOYLE et al. teaches An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure.
DOYLE et al. teaches a quantization factor may be employed to quantize all coordinate values associated with the BVH, primitives, and rays.
Yang et al. teaches primitive data stored in each data block corresponds to primitives that are grouped together
DOYLE et al. does not teach primitive data stored in each data block corresponds to primitives that are grouped together
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, DOYLE et al. performs the same function as it does separately of managing process primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration
Structure.
Yang et al. performs the same function as it does separately of allowing primitive data stored in each data block corresponds to primitives that are grouped together.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of DOYLE et al. to include primitive data stored in each data block corresponds to primitives that are grouped together, as disclosed by Yang et al. thereby Storing the primitives in primitive blocks may allow the transformed geometry data for a set of primitives to be stored more efficiently in memory as Yang et al. discusses at paras. 6, 157.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 9, DOYLE et al. discloses the second circuitry is configured to receive the one or more fixed-size data blocks as input, through a graphics application programming interface (API) (para. 115 discloses specific geometry data compute pixel color data for each geometric fragment (quantized primitive block)).
Regarding Claim 10, Yang et al. discloses a predetermined number of data blocks of the one or more fixed-size data blocks together form a data node (abstract), and wherein the data node represents at least one bottom-level acceleration structure (BLAS) internal node of the acceleration data structure (para. 336)
Regarding Claim 13, DOYLE et al. the set of primitives are clustered in one or more clusters (abstract, 435, disclosing primitives are clustered in one or more clusters in BVH (bounding volume hierarchy), prior to quantization (para. 304), based at least in part on a surface area heuristic (para. 377), such that each primitive in a cluster shares a spatial locality corresponding to a scene with other primitives within the cluster. (para. 377, please also see paras. abstract, 435,438, 443, 444, disclosing a surface area heuristic each primitive in a cluster of BVH shares a spatial locality corresponding to a scene with other primitives within the cluster of BVH),
Regarding Claim 14, DOYLE et al. discloses primitives in each cluster comprise primitives that together represent a single node of the acceleration data structure (please see Abstract)
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over DOYLE MICHAEL et al. (US-20210090207-A1) hereinafter referenced as DOYLE et al. in view of Yang; Xile et al. (US-20210248806-A1) here in after referenced as Yang et al. as applied to claims 1-3, 5-10 and 13-14 above and further in view of Burns Christopher A.( US-20230102071-A1) hereinafter referenced as Burns.
Regarding Claim 4, DOYLE et al. in view of Yang et al. fails to disclose a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width.
However, prior art of Burns discloses a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width (para. 54).
DOYLE et al. teaches An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure.
DOYLE et al. teaches a quantization factor may be employed to quantize all coordinate values associated with the BVH, primitives, and rays.
Burns teaches a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width.
DOYLE et al. does not teach a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, DOYLE et al. performs the same function as it does separately of managing process primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration
Structure.
Burns performs the same function as it does separately of generating an interpolated spatial coordinate interval to represent a moving triangle for a conservative intersection test for a given ray time in a motion blur interval. Further, disclosed techniques provide an efficient encoding and processing techniques for moving and non-moving triangle pairs of images.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of DOYLE et al. to include primitive data stored in each data block corresponds to primitives that are grouped together, as disclosed by Burns thereby to be able to reduce storage requirements for storing of encoded data as Burns discusses at para. 11.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 11 Burns discloses a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width (para. 54).
Claim(s) 15-17 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over DOYLE MICHAEL et al. (US-20210090207-A1) hereinafter referenced as DOYLE et al. in view of Yang; Xile et al. (US-20210248806-A1) here in after referenced as Yang et al. and Gies Sean Matthew et al. (US-20140333622-A1) hereinafter referenced as Gies et al.
Regarding Claim 15, DOYLE et al. discloses a processor para. 176, disclosing graphic processor para. 181, disclosing ray tracing is graphic processing) comprising: ray tracing circuitry configured to: store quantized primitive data as one or more fixed-size data blocks (para. 278, 304); and construct an acceleration data structure based at least in part on quantized primitive data stored in each of the one or more fixed-size data blocks (Abstract, disclosing An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure para. 304, disclosing , quantized primitive data are stored in fixed packet size data blocks, however, please notice DOYLE et al. do not recite one or more fixed-size data blocks ), wherein quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure (please see abstract, para. 336 disclosing quantized primitive data stored in each data block corresponds to primitives that are grouped together to represent at least one node of an acceleration data structure). However, DOYLE et al. fails to explicitly recite one or more fixed-size data blocks.
However, prior art of Yang et al. at paras. 7, 8 disclosing similar to quantizing process via disclosing primitives are grouped in to the primitive blocks by dividing rendering space into the micro regions maps to the tiles to be rendered, and grouping the transformed primitive into the primitive blocks. (If the primitive block generator 110 determines that the primitive falls, at least partially, within only one macro region, then the primitive block generator 110 may place the primitive (i.e. the transformed geometry data related to that primitive) in the primitive block for that macro region. If the primitive block generator 110 determines that the primitive falls within more than one macro region then the primitive block generator 110 may be configured to (i) select one of the macro regions the primitive falls within (e.g. the first one) and place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for the selected macro region; or (ii) place the primitive (i.e. the transformed geometry data related thereto) in the primitive block for each of the macro regions the primitive falls, at least partially, within), paras. 17-18 reciting storing primitive fixed size primitive data block memories.
DOYLE et al. teaches An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure.
DOYLE et al. teaches a quantization factor may be employed to quantize all coordinate values associated with the BVH, primitives, and rays.
Yang et al. teaches primitive data stored in each data block corresponds to primitives that are grouped together
DOYLE et al. does not teach primitive data stored in each data block corresponds to primitives that are grouped together
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, DOYLE et al. performs the same function as it does separately of managing process primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration
Structure.
Yang et al. performs the same function as it does separately of allowing primitive data stored in each data block corresponds to primitives that are grouped together.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of DOYLE et al. to include primitive data stored in each data block corresponds to primitives that are grouped together, as disclosed by Yang et al. thereby Storing the primitives in primitive blocks may allow the transformed geometry data for a set of primitives to be stored more efficiently in memory as Yang et al. discusses at paras. 6, 157.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Further regarding Claim 15, DOYLE et al. fails to disclose a plurality of computer circuits configured to render image data using the acceleration data structure.
However, prior art of Gies et al. discloses a plurality of computer circuits configured to render image data using the acceleration data structure (para. 31, disclosing acceleration structures are used and selected by a computer to abstract objects composing a 3-D scene to accelerate testing of rays for intersection with the objects, para. 25 disclosing producing an acceleration structure during preparation to render a scene, para. 93, disclosing acceleration structure builder included in a flow to prepare a scene to be rendered. Para. 43, disclosing a computer readable medium to perform the particular intersection tests described and interpret the results of the tests. Further machine components include communication links for providing the acceleration structures to the testing resources and to receive the results of the testing. The machines for intersection testing can be a component of a larger system including other input and output devices, such as a drive for reading scene description data, and a display or a computer readable medium for outputting rendered scenes. For example, the computer readable medium can be a DVD and each scene may be a frame of a motion picture).
DOYLE et al. teaches An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure.
DOYLE et al. teaches a quantization factor may be employed to quantize all coordinate values associated with the BVH, primitives, and rays.
Gies et al. teaches a plurality of computer circuits configured to render image data using the acceleration data structure.
DOYLE et al. does not teach a plurality of computer circuits configured to render image data using the acceleration data structure.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, DOYLE et al. performs the same function as it does separately of managing process primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration
Structure.
Gies et al. performs the same function as it does separately of a computer readable medium to perform the particular intersection tests described and interpret the results of the tests. Further machine components include communication links for providing the acceleration structures to the testing resources and to receive the results of the testing. The machines for intersection testing can be a component of a larger system including other input and output devices, such as a drive for reading scene description data, and a display or a computer readable medium for outputting rendered scenes. For example, the computer readable medium can be a DVD and each scene may be a frame of a motion picture.
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of DOYLE et al. to include a plurality of computer circuits configured to render image data using the acceleration data structure, as disclosed by Gies et al. thereby rendering, using ray tracing, two-dimensional representations of three-dimensional scenes, and more particularly to accelerating intersection testing of rays with acceleration structures, as Gies et al. discusses at para. 3.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 16, DOYLE et al. discloses the at least one node is a bottom-level acceleration structure (BLAS) internal node of the acceleration data structure (para. 336)
Regarding Claim 17, Yang et al. discloses a predetermined number of data blocks of the one or more fixed-size data blocks together form a data node (abstract) wherein the data node represents the BLAS internal node of the acceleration data structure (para. 336).
Regarding Claim 19, Yang et al. discloses the first data block (para. 18, discloses data block are primitive blocks, para. 135 discloses primitive consists of geometry figures)
DOYLE et al. discloses at para. 402, discloses the grid primitive represents dense geometry format.
Regarding Claim 20, Gies et al. discloses the plurality of compute circuits are configured to perform ray intersection tests using data stored in the acceleration data structure (para. 31, discloses Acceleration structures are used and selected by a computer to abstract objects composing a 3-D scene to accelerate testing of rays for intersection with the objects).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over DOYLE MICHAEL et al. (US-20210090207-A1) hereinafter referenced as DOYLE et al. in view of Yang; Xile et al. (US-20210248806-A1) here in after referenced as Yang et al. and Gies Sean Matthew et al. (US-20140333622-A1) hereinafter referenced as Gies et al. as applied to claims 15-17 and 19-20 above and further in view of Burns Christopher A (US-20230102071-A1) hereinafter referenced as Burns.
Regarding Claim 18, Burns discloses a first data block stores data encoded using a first bit width and a second data block stores data encoded using a second bit width different than the first bit width (para. 54).
Allowable Subject Matter
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant is requested to review the prior art cited on USTO 892’s.
The prior art of LUEBKE David (US 20140168238 A1) disclosure; paras. 21-84, disclosing, a method for tracing a ray within a parallel processing unit. The method includes receiving, at a first thread, at least a portion of a ray for tracing, and identifying a first node within an acceleration structure associated with at least a portion of the ray, where the first node is associated with a volume of space traversed by the ray. The method further includes identifying a plurality of nodes that comprise child nodes of the first node, where each node within the plurality of nodes is associated with a different sub-volume of space within the volume of space, and where each sub-volume of space is associated with a corresponding ray segment within at least a portion of the ray. The method further includes determining that two or more nodes within the plurality of nodes are associated with sub-volumes of space that intersect the at least a portion of the ray. The method further includes selecting a second node that comprises one node of the two or more nodes for processing by the first thread, and selecting a third node that comprises another node of the two or more nodes for processing by a second thread. The method further includes causing the second thread to process the third node. The method further includes determining that two or more nodes within the plurality of nodes are associated with ray segments that intersect at least one graphics object. The method further includes selecting a second node that comprises one node of the two or more nodes for processing by the first thread, and selecting a third node that comprises another node of the two or more nodes for processing by a second thread. The method further includes determining that the second thread is processing at least a portion of a second ray, and placing an entry associated with the third node into a first data structure. The method further includes causing the second thread to retrieve the entry associated with the third node from the first data structure when the second thread has completed processing at least a portion of the second ray.
The prior art of Morrical Nathan (US 20230066636 A1) disclosure; paras. 22-252, discloses, the efficient generation of high quality images from components such as textures and assets, where textures can provide a source of illumination for one or more assets in a scene to be rendered. In order to make such a lighting or shading process efficient, aspects of the process can be mapped to hardware units that can provide for hardware-based acceleration. An approach in accordance with at least one embodiment can determine one or more cumulative distribution functions for a texture, and can construct a geometric representation from that cumulative distribution, such that one or more rays can be traced against that geometry to perform sampling in a way that supports hardware acceleration. Large emissive textures can be utilized, which can increase the detail and overall realism of a scene, providing an effective source of environmental lighting for a scene. Importance sampling of these large emissive textures can help to reduce an amount of noise in an image that might otherwise be introduced if, for example, these textures were naively sampled, as a majority of incoming radiance may originate from a small fraction of the texels of a texture, and random sampling with equal probability may result in these small, influential texels rarely being sampled. Sampling of large emissive textures can be performed using inverse transform sampling. While traditional inverse transform sampling can be utilized with some success, this sampling performance may be unreliable due to the unpredictable nature of binary search. Moreover, traditional inverse transform sampling does not allow for control over whether, or by how much, to prioritize variance reduction or performance. Approaches in accordance with at least one embodiment can utilize a ray traversal search, such as a single hardware-accelerated ray-traversal search over cumulative probability geometry, instead of traditional binary searches performed in texture space. The use of a ray traversal search can enable the leveraging of ray tracing hardware, which can significantly improve performance of importance sampling. Such importance sampling performance improvements have been shown to translate to improved rendering performance, by up to 70% in one example, while achieving a similar reduction in variance to traditional inverse transform sampling. Moreover, the intersected cumulative probability geometry can be modified to enable prioritizing performance over variance reduction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRABODH M DHARIA whose telephone number is (571)272-7668. The examiner can normally be reached Monday -Friday 9:00 AM to 5:30 PM.
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Any response to this action should be mailed to:
Commissioner of Patents and Trademarks
P.O. Box 1450
Alexandria VA 22313-1450
/Prabodh M Dharia/
Primary Examiner
Art Unit 2629
03-16-2026