Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/25/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2-7, 9-13 and 15-20 are objected to because of the following informalities:
Claim 2 recites, “The integrated circuit of claim 1 wherein the voltage drop….” should read, “The integrated circuit of claim 1, wherein the voltage drop……”.
Claim 3 recites, “The integrated circuit of claim 2 wherein the multiplexer circuit….” should read, “The integrated circuit of claim 2, wherein the multiplexer circuit……”.
Claim 4 recites, “The integrated circuit of claim 2 wherein the multiplexer circuit….” should read, “The integrated circuit of claim 2, wherein the multiplexer circuit……”.
Claim 5 recites, “The integrated circuit of claim 3 comprising memory ….” should read, “The integrated circuit of claim 3, comprising memory ……”.
Claim 6 recites, “The integrated circuit of claim 4 wherein the control circuitry ….” should read, “The integrated circuit of claim 4, wherein the control circuitry ……”.
Claim 7 recites, “The integrated circuit of claim 4 wherein the multiplexer circuit ….” should read, “The integrated circuit of claim 4, wherein the multiplexer circuit ……”.
Appropriate correction is required.
Similar amendment for claims 9-13 and 15-20 are objected to because of the same reason as stated above.
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “voltage drop detection circuitry” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
In this application in claim 1 the recited “voltage drop detection circuitry” coupled with the functional language “to select each of a plurality of tap points from the on-chip power conductor network”.
The limitation in claim 1 have no structural meaning and are considered a generic placeholder.
In the present application (PGPUB NO: US 20250389767 A1) discloses:
In Paragraph 22-23, “[0022] FIG. 2 illustrates an example of a voltage drop detection circuit 106 connected to a standard on-chip power grid 200 with decoupling capacitors C.sub.1, C.sub.21, C.sub.3 1and C.sub.41between corresponding grid power (VRA) tap points (VRA.sub.1-41) and grid ground (AVSS) tap points AVSS.sub.1-41. [0023] In one example, the voltage drop detection circuit 106 includes a multiplexer circuit 202, a ring oscillator 204, a ring oscillator voltage supply 206 and control circuitry 208. In this example, the multiplexer circuit 202 is configured to facilitate both modes of operation. The multiplexer circuit includes a ground multiplexer 210 and a power multiplexer 212. The ground multiplexer 210 has a ring oscillator ground reference tap point input (VSS) and a plurality of tap point inputs that are coupled to the ground tap points of the power grid (AVSS.sub.1-AVSS.sub.n). The ground reference tap point input is connected to the ground reference VSS of the ring oscillator. The ground multiplexer 210 has an output 214 that provides a signal from a selected tap point and couples to the ring oscillator 204. The ground multiplexer 210 outputs the selected ground tap point input as the output 214. The power multiplexer 212 has a ring oscillator power reference tap point input (VDD) and a plurality of tap point inputs that are coupled to the power tap points of the power grid (VRA.sub.1-VRA.sub.n). The power reference tap point input is connected to the power voltage VDD of the ring oscillator. The power multiplexer 212 has an output 216 that provides a signal from the selected tap point and the output 216t also couples to the ring oscillator 204. The power multiplexer 212 outputs the selected power tap point input as the output 216. For calibration purposes, the power multiplexer also has a calibration reference input 220 as further described below.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “voltage drop detection circuitry, operative to select each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provide data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points”. Claim recites, “voltage drop circuitry”, however it is not clear what elements are in the voltage drop circuitry. The meaning of the language “select each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provide data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points” is unclear. It is not clear how a voltage drop circuitry select tap points and what element of the voltage drop circuitry is used to determine the plurality of tap points. Then it is not clear from where data is providing and how the data is calculated. It is not clear how frequency is determined corresponding to a voltage level of the each of the plurality of selected tap points. It is not clear how the voltage level is calculated. Therefore, claim language is not clear.
Clarification is required so that the scope of the claim is clear.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claim 1.
Claim 8 recites, “the ring oscillator operatively coupled to produce a frequency based on the respective signals received from the first and second outputs”. It is not clear how frequency is produced. It is not what signal is received from first and second output and from the signals how the frequency is produced. Therefore, claim language is not clear.
Claim 8 recites, “in a first mode…… in a second mode”. It is not clear when and how the first mode and second mode is created and what element is used to create first mode and second mode. Therefore, claim language is not clear.
Clarification is required so that the scope of the claim is clear.
Claims 9-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claim 8.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, because of the same reason as stated above for claim 1.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claim 14.
Claim 15 recites, “generating a voltage map of the on-chip power conductor network based on resulting data from the ring oscillator”. The meaning of the language is not clear. It is not clear how a map is generated; what data is used to generate the map and which structure is used to generate the map. It is not clear how the first input and second input is selected and which inputs are the ground tap input. Therefore, claim language is not clear.
Clarification is required so that the scope of the claim is clear.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of its dependence from claim 15.
Claim 17 recites, “in a first mode…… in a second mode”. It is not clear when and how the first mode and second mode is created and what element is used to create first mode and second mode. Therefore, claim language is not clear.
Clarification is required so that the scope of the claim is clear.
Claims 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claim 17.
It appears that claims 14-20 should have been rejected under 35 USC 112(b).
Referring to claim 14, it appears that the claim has recited insufficient structure for performing the recited method of having "two states," namely, "produce data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points". Paragraphs 22-25 of the specification teach the structure used to produce data representing a frequency, however, claim 14 only includes a multiplexing circuit. Consequently, the claim does not appear to recite the requisite structure for performing the claimed method. As such, the boundaries of the language are unclear because the claim does not provide a discernable boundary on what performs the method. The recited method does not follow from the structure recited in the claim, i.e., a multiplexing circuit, so it is unclear whether the method requires some other structure or is simply a result of operating the multiplexing circuit. Thus, one of ordinary skill would not be able to draw a clear boundary between what is and is not covered by the claim. See MPEP 2173.05(g).
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite by virtue of their dependence from claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 14 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1.
Regarding claim 1, Narayanan teaches an integrated circuit [10] (An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; Abstract; FIG. 1A is a simplified pictorial diagram of conductive lines of a power grid of an integrated circuit chip and having power grid points for electrical monitoring and testing; Paragraph [0020] Line 1-4) comprising:
at least one on-chip power conductor network [20] (power grid 20 as the on-chip power conductor network) (In FIG. 1A, an integrated circuit 10 has a power grid 20; Paragraph [0044] Line 1-2) configured to distribute electrical power to a plurality of electrical components on the integrated circuit (In FIG. 1A, an integrated circuit 10 has a power grid 20, which is a layout of a material in the integrated circuit 10 that extends to a power connection for the integrated circuit of either common (ground GND), or a positive or negative voltage connection VDD. The power grid 20 may include a portion of conductor having an intersection or tap going to circuitry to be powered; Paragraph [0044] Line 1-7); and
voltage drop detection circuitry [100.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B; Paragraph [0045] Line 7-9), operative to select each of a plurality of tap points [30.i] (In FIG. 1A, the power grid 20 on integrated circuit 10 is tapped at various points 30.i as shown by enlarged dots. In cross-section (not shown) the integrated circuit 10 may have a layer of transistors and one or more elevated layers (e.g., metal or polysilicon, etc) overlying the transistor layer and coupled to the transistor layer by vias; Paragraph [0045] Line 1-6) from the on-chip power conductor network [20](In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20; Paragraph [0045] Line 7-10) and in response to a plurality of selected tap points [30.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20 and used to detect the IR drop (voltage drop) at its tap 30.i. In some other embodiments, one or more shared IR drop monitoring circuits such as any one, some or all of circuits in any of FIGS. 2-11 and 15A is electrically coupled with at least one group of the taps (dots) 30.i and used to detect the IR drops; Paragraph [0045] Line 7-15; In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150.
[0047] In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150; Paragraph [0047] Line 1-8).
provide data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points (In FIG. 1B, note also that some embodiments couple one or more of the IR drop monitoring scan registers 120.i to a power management circuit 190. In this way, instances of excessive IR drop can not only be detected during scan test, but also the power management circuit 190 can respond to such instances of excessive drop during regular functional operation of the integrated circuit 10. Such power management response may reduce functional operating frequency or increase supply voltage, or both, such as by transitioning to a different voltage/clock frequency DVFS Operating Performance Point (OPP) or doing automatic voltage scaling AVS; Paragraph [0059] Line 1-11; depending on the voltage level of different tap points frequency is reduced or controlled and therefore data represent frequency either reduced or increased).
Regarding claim 14, Narayanan teaches a method for detecting voltage drops (An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; Abstract; FIG. 1A is a simplified pictorial diagram of conductive lines of a power grid of an integrated circuit chip and having power grid points for electrical monitoring and testing; Paragraph [0020] Line 1-4) in an on-chip power conductor network [20] (power grid 20 as the on-chip power conductor network) (In FIG. 1A, an integrated circuit 10 has a power grid 20; Paragraph [0044] Line 1-2) comprising:
selecting, by a multiplexer circuit [225.1, 225.2] in Figure 3 (In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7) each of a plurality of tap points [30.i] (In FIG. 1A, the power grid 20 on integrated circuit 10 is tapped at various points 30.i as shown by enlarged dots. In cross-section (not shown) the integrated circuit 10 may have a layer of transistors and one or more elevated layers (e.g., metal or polysilicon, etc) overlying the transistor layer and coupled to the transistor layer by vias; Paragraph [0045] Line 1-6) from the on-chip power conductor network [20](In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20; Paragraph [0045] Line 7-10); and
in response to a plurality of selected tap points [30.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20 and used to detect the IR drop (voltage drop) at its tap 30.i. In some other embodiments, one or more shared IR drop monitoring circuits such as any one, some or all of circuits in any of FIGS. 2-11 and 15A is electrically coupled with at least one group of the taps (dots) 30.i and used to detect the IR drops; Paragraph [0045] Line 7-15; In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150.
[0047] In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150; Paragraph [0047] Line 1-8),
provide data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points (In FIG. 1B, note also that some embodiments couple one or more of the IR drop monitoring scan registers 120.i to a power management circuit 190. In this way, instances of excessive IR drop can not only be detected during scan test, but also the power management circuit 190 can respond to such instances of excessive drop during regular functional operation of the integrated circuit 10. Such power management response may reduce functional operating frequency or increase supply voltage, or both, such as by transitioning to a different voltage/clock frequency DVFS Operating Performance Point (OPP) or doing automatic voltage scaling AVS; Paragraph [0059] Line 1-11; depending on the voltage level of different tap points frequency is reduced or controlled and therefore data represent frequency either reduced or increased).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan ‘824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1.
Regarding claim 2, Narayanan teaches an integrated circuit, wherein the voltage drop detection circuitry comprises:
a multiplexer circuit [225.1, 225.2] in Figure 3 comprising a first output (a first output to comparator 210.1) and a second output (a second output to comparator 210.2), each output providing a respective signal from a different selected tap point [223.i.1 and 223.i.2] from the plurality of tap points [30.i] in Figure 2 (In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7).
Narayanan fails to teach that the voltage detection circuitry comprises: a ring oscillator comprising an odd number of serially coupled inverters and at least one passgate interposed between each respective serially coupled inverter, each passgate operatively coupled to receive the respective signals from the first and second outputs from the multiplexer circuit.
Friend teaches electronic oscillators, and, more particularly, to voltage-controlled oscillators (Paragraph [0001] Line 1-3), wherein
the voltage detection circuitry (Figure 1) comprises a ring oscillator comprising an odd number of serially coupled inverters [120, 122, and 124] (3 inverters) and at least one passgate [130, 132, and 134] interposed between each respective serially coupled inverter [120, 122, and 124], each passgate operatively coupled to receive the respective signals from the first and second outputs from the multiplexer circuit (In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change; Paragraph [0034] Line 1-9). The purpose of doing so is to use an improved voltage-controlled oscillator, to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain, to provide new functionality and has minimal overhead and is less complex.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Narayanan by introducing a ring oscillator comprising an odd number of serially coupled inverters as disclosed by Friend, because Friend teaches to include a ring oscillator comprising an odd number of serially coupled inverters uses an improved voltage-controlled oscillator, controls a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain (Paragraph [0015]), provides new functionality and has minimal overhead and is less complex (Paragraph [0043]).
Allowable Subject Matter
Claim 8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 3-7, 9-13 and 15-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Corr (US 20040162693 A1) discloses, “Apparatus And Method For Determining Effect Of On-chip Noise On Signal Propagation- [0002] The present invention relates generally to testing integrated circuits and more particularly to testing the on-chip effects of noise and cross-talk on signal propagation. [0030] In FIG. 1, the testing apparatus 21 having a set of four test circuits 22, 24, 26, 28 is shown for testing IC chip 10, and more specifically for testing core logic area 12. In the current embodiment, one or more of the test circuits 22, 24, 26, 28 are located within the reserved area. [0031] It should be noted that, for simplicity, the following discussion of the present invention has been limited to a single testing apparatus 21, a portion of which is located within core logic area 12. However, the use of multiple testing apparatus 21 for testing other portions of the IC chip 10 (e.g., the other core logic areas 14, 16, 18) is within the scope of the present invention. Furthermore, the present invention encompasses IC chips having alternative layouts and an alternative number of core logic areas. For example, an IC chip containing only one core logic area for the entire chip surface is within the scope of the present invention. [0032] A group of test circuits (e.g., test circuits 22, 24, 26, 28) comprises a testing apparatus 21 for dynamically monitoring an integrated circuit 10. In one embodiment, the testing apparatus 21 contains four test circuits 22, 24, 26, 28 each functioning as ring oscillators. Each test circuit 22, 24, 26, 28 may contain elements, or cells, such as logic gates, inverters, and output dividers, among others. The elements are connected to one another via electrical traces. The element placement and trace routing of each of the four test circuits 22, 24, 26, 28 is selected to isolate specific test quantities (such as noise, cross-talk, etc.) within the IC chip 10. For example, test circuit 22, whose components are located in the reserved area 20 of the IC chip 10, measures a different quantity than test circuit 26, whose components are located within the core logic area 12. [0033] The number of inverters used by each test circuit 22, 24, 26, 28 in the current embodiment is preferably restricted such that the ring oscillator loop remains inverting and the oscillation frequency remains low enough for on-chip division. Contact pads are used to connect the test circuits 22, 24, 26, 28 to external test equipment. For example, the "run", "clr" and "output" lines of the test circuits 22, 24, 26, 28 (as shown in FIGS. 2-5) each have a contact pad that is accessible by external test equipment. Each test circuit 22, 24, 26, 28 is described in more detail below. It should be noted that additional test circuits may be added to the IC chip 10 as needed. Furthermore, non-ring oscillator test circuits may be substituted to obtain similar results-However Corr does not disclose voltage drop detection circuitry, operative to select each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provide data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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